Power Efficient Arithmetic Logic Unit Design Using Reversible Logic

International Journal of Computer Applications (0975 – 8887)Volume 128 – No.6, October 2015Power Efficient Arithmetic Logic Unit Design usingReversible LogicNaman SharmaRajat SachdevaUpanshu SaraswatBharati Vidyapeeth’s College ofEngineering, New Delhi-110063Bharati Vidyapeeth’s College ofEngineering, New Delhi-110063Bharati Vidyapeeth’s College ofEngineering, New Delhi-110063Rajat YadavGunjeet KaurBharati Vidyapeeth’s College of Engineering,New Delhi-110063Bharati Vidyapeeth’s College of Engineering,New Delhi-110063ABSTRACTReversible logic is highly useful in nanotechnology, lowpower design and quantum computing. The paper proposes apower efficient design of an ALU, using Reversible LogicGates. With power management becoming a criticalcomponent for hardware design developers, Reversible Logiccan provide a viable alternative towards creating low powerdigital circuits.KeywordsReversible logic, Arithmetic Logic Unit, Low Power DesignGeneral TermsPower Efficient Digital Logic Design1. INTRODUCTIONThe recent advancements in the field of Large ScaleIntegration, especially over the last ten years have enabledengineers to create new, more powerful devices than everbefore. The technology has become ever more portable,personalized and has tremendous built-in functionality. This isthe era of smartphone and portable computers. With the sizeof the chip being reduced, power consumption has becomethe paramount concern during design considerations. Manytechniques such as voltage scaling, to reduce the powerconsumption of circuits are suggested but their use results inincremental improvements only [11]. It is predicted that theMoore‟s law is at an end due to the inability of the designersto keep up with the power requirements of the future chips.[1]One of the solutions to meet the low-power requirement ofthe future devices is by adopting an entirely new modelknown as Reversible Logic. Reversible logic finds its originsin the concepts of Quantum Computing [12]. Researchers likeBennett showed that the devices based on reversiblecomputing consume much less power than the traditionalirreversible devices [3, 4]. Reversible logic gates use one-toone mapping between input and output vectors, therebypreventing loss of information, which in turn preventsdissipation of energy, as shown by Landauer [5, 6]. Differentarithmetic circuits such as Adders, Subtracters, Multipliers,Carry Adders etc. based on reversible are available inliterature. Toffoli demonstrated in [14] that reversible logicstructures are satisfactory for design and implementation incomputing structures and organization when those designrules ensure the logic structure is invertible. Deustch laterstated that reversible gates connected to each other by meansof unit wires can be sufficiently used for the generation of aquantum computational network [15, 16]. Quantum(reversible) gates are the generalization of classical logicgates. Deustch defined a source bit of „0‟ or „1‟ as a gatewhich, once every computational step, produces a value of „0‟or „1‟ on its output [16].In this paper, the authors propose an architecture for powerefficient Arithmetic Logic Unit circuits using ReversibleGates. The paper first briefly provides an overview of thereversibe logic and few reversible gates in section 2.Thereafter, the architecture to implement the aforementionedALU is proposed in section 3. The correctness of theproposed architectures is demonstrated through functionalverification and performance analysis in Verilog in section 4.Finally section 5 concludes the paper.2. BASIC REVERSIBLE GATESIn 1960, researcher R. Landauer demonstrated that circuitsusing irreversible hardware results in energy dissipation ofkTln2 Joules due to one bit loss of information where k isBoltzmann‟s constant and T the absolute temperature [5, 6].Bennett showed that this energy loss can be avoided byconstructing circuits using reversible logic gates [3, 4]. Areversible logic gate is an n-input, n-output logic functionthat maintains a one-to-one mapping between the two. Basedon this principle, different basic reversible gates such asFeynman [7], Toffoli [8] and Peres [10] have been proposed.A 2*2 Feynman gate with inputs (A,B) produces the output Pequal to input A while output Q as the XOR of the inputs[21]. A 3*3 Toffoli gate with inputs (A, B, C) and outputs (P,Q, R). It has outputs P and Q equal to A and B respectivelywhile the output R is complement of the input C if both Aand B are at logic 1, otherwise it is input C [21, 22] . AFredkin gate is a 3*3 gate with inputs A, B and C givingoutputs P, Q and R. The outputs are defined as P A; Q A‟B AC; and R AB A‟C [23]. A Peres gate is a 3*3reversible gate with inputs (A, B, C) and outputs (P, Q, R).The output P is equal to A; output Q is the XOR of A and Bwhile R is complement of the input C if both A and B areequal to 1, otherwise it is equal to input C [24]. A URG gateis a 3*3 gate with inputs (A, B, C) and outputs P (A B) xorC, Q B, R AB xor C [21]. A PFAG gate is also known asa Peres Full Adder Gate. It is a 4*4 gate with inputs (A, B, C,D) and outputs (P, Q, R, S). The outputs take the valuesP A; Q A xor B; R A xor B xor C and R ((A xor B) C) (AB) as described by Islam [17].36

International Journal of Computer Applications (0975 – 8887)Volume 128 – No.6, October 20153. ARITHMETIC LOGIC UNIT USINGREVERSIBLE GATES3.1 Arithmetic Unit using Reversible GatesThe arithmetic unit is the most fundamental building block ofany digital system. It has the ability to perform basicarithmetic manipulation like addition, subtraction, additionwith carry and subtraction with borrow on bits of data storedin registers. These manipulations are known as Microoperations [19]. The micro-operations which are used tocause data manipulation can be of four types – RegisterTransfer, Arithmetic, Logical, and Shift. An ALU primarilyimplements Arithmetic, Logic and Register Transfer microoperations. Hence the part of a digital circuit that causesarithmetic processing of data stored in registers is called anArithmetic Unit. An arithmetic unit, in its implantationmakes use of the basic full adder circuit. A full adder circuitcan be implemented using reversible gates in many ways.Two of the easiest methods however, is by the use of twoPeres Gate (PG) or by using a Peres Full Adder Gate (PFAG)as suggested by Islam [17]. The two methods have beenshown below.In the above figure,A S0‟I0 S0I1(1)B S0‟I2 S0I3(2)Y S1‟S0‟I0 S1‟S0I1 S1S0‟I2 S1S0I3(3)Using the above described elements, namely the Full Adderand the Multiplexer, one can fully implement the ArithmeticUnit. The following block diagram shows how this can beaccomplished.Fig 4: Block Diagram Showing the implementation of anArithmetic UnitFig 1: 1-Bit Full Adder using two Peres GatesThe authors have therefore proposed the design of anarithmetic unit for which either of the two Full Adderdesigns may be used. The most optimized form of the circuithas been discussed later in the paper. The authors would alsolike to draw the reader‟s attention to the fact that furtheroptimizations may be performed for the adder as well as themultiplexer circuit, which can yield better quantum cost,lower gate count or lesser garbage outputs.3.2 Logic Unit using Reversible GatesFig 2: 1-Bit Full Adder using a single PFAG GateThe above given circuits provide two distinctimplementations for one-bit Full Adder circuit. These 1-Bitimplementations can be made for additional number of bits,(say 4 Bit) using a Serial Adder. The other crucialcomponent required for the design of an Arithmetic Unit, is aMultiplexer. Here, the authors have used the simplestmultiplexer design available in the literature; that is bymaking use of three Fredkin Gates (FG) [21]. The circuitdiagram for a multiplexer has been given below.The next design, required to implement an ALU is the LogicUnit. It is that part of the ALU which is used to perform bitwise logical micro-operations. The proposed Logic Unit canperform logical AND, OR, NOT and XOR operations. Thiswas proposed using two architectures. The first architecturemade use of a single 3X3 Peres Gate (PG) and a single 3X3Toffoli Gate (TG) used along with a 4X1 Multiplexer circuit.The Multiplexer Circuit used here makes use of the samethree Fredkin Gate implementation that has been discussedbefore. The first proposed architecture is given as.Fig 5: 1-Bit Logic Unit using a combination of Peres Gateand Toffoli GateIn the next proposed implementation, the authors make useof a 3X3 Universal Reversible Gate (URG) used alongside abasic 2X2 Feynman Gate (FnG) along with the three FredkinGate Multiplexer used previously. The proposed architecturefor this Logic Unit is given by.Fig 3: 4X1 Multiplexer Design using three Fredkin Gates37

International Journal of Computer Applications (0975 – 8887)Volume 128 – No.6, October 2015Fig 6: 1-Bit Logic Unit using URG and Feynman GatesThe equation for O in both the circuits is defined as,O S1‟S0‟I0 S1‟S0I1 S1S0‟I2 S1S0I3where,I0 A B (4)I1 A . B (5)I3 NOT A (6)I4 A B (7)Hence either of the two implementations can be used toproduce a Logic Circuit. With both the Arithmetic and theLogic Unit implemented, onecan now look at theimplementation of the ALU.Fig 7: Block Diagram for any Arithmetic Logic UnitOne observes that the given implementation requires the useof a 2X1 Multiplexer. This can be easily implemented bymaking use of a single 3X3 Fredkin Gate.3.3 ALU design using Reversible GatesThe designs that have been suggested to implement 1-BitArithmetic Unit and 1-Bit Logic Unit are utilized to create anALU. The proposed ALU will perform the following Microoperations. [18]Table 1: Functional Table for Arithmetic Logic UnitFig 8: Implementation of a 2X1 Multiplexer using a singleFredkin GateThe authors have proposed two architectures for arithmeticlogic unit using reversible gates. The first architecture makesuse of the Peres Full Adder Gate (PFAG) for its ArithmeticUnit and uses a combination of Universal Reversible Gate(URG) and Feynman Gate (FnG) in the implementation of itsLogic Unit. The second architecture uses two Peres Gates(PG) connected together for its Arithmetic Unit and uses acombination of Peres Gate (PG) and Toffoli Gate (TG) toimplement the Logic Unit. These designs are shown below.The interfacing of the Arithmetic Unit and Logic Unit inorder to get an ALU can be described from the given blockdiagram.38

International Journal of Computer Applications (0975 – 8887)Volume 128 – No.6, October 2015Fig 9: Proposed Architecture for an Aritmetic Logic Unit (Architecture 1) implemented by using Fredkin, UniversalReversible, Feynman, and Peres Full Adder GateFig 10: Prosposed Architecture for an Arithmetic Logic Unit (Architecture 2) implemented by using Fredkin, Peres and ToffoliGates4. SIMULATION SECTIONThis section first verifies the functionality of the proposedarchitectures (Arch-1 and Arch-2) to implement an ALU Thefunctionality has been verified through Verilog Simulation.Waveforms for the various micro-operations were generated,and verified. Thereafter, the effectiveness of the proposedarchitecture is demonstrated through their synthesis onFPGA using Xilinx. The synthesis report generated has alsobeen included by the authors in their findings.Fig 12: Waveform analysis for the Addition with CarryOperation4.1 Functional VerificationThis section includes the functional verification forarchitecture correctness. Waveforms generated for testingthe correctness have been shown below.Fig 12: Waveform analysis for the Subtraction withBorrow OperationFig 11: Waveform analysis for the Addition OperationFig 12: Waveform analysis for the Subtraction Operation39