Read Disturb Errors - Carnegie Mellon University
Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery Yu Cai, Yixin Luo, Saugata Ghose, Erich F. Haratsch*, Ken Mai, Onur Mutlu Carnegie Mellon University, *Seagate Technology
Executive Summary Read disturb errors limit flash memory lifetime today – Apply a high pass-through voltage (Vpass) to multiple pages on a read We characterize read disturb on real NAND flash chips – Slightly lowering Vpass greatly reduces read disturb errors – Some flash cells are more prone to read disturb Technique 1: Mitigate read disturb errors online – Vpass Tuning dynamically finds and applies a lowered Vpass – Flash memory lifetime improves by 21% Technique 2: Recover after failure to prevent data loss – Read Disturb Oriented Error Recovery (RDR) selectively corrects cells more susceptible to read disturb errors – Reduces raw bit error rate (RBER) by up to 36% 2
Outline Background (Problem and Goal) Key Experimental Observations Mitigation: Vpass Tuning Recovery: Read Disturb Oriented Error Recovery Conclusion 3
Outline Background (Problem and Goal) Key Experimental Observations Mitigation: Vpass Tuning Recovery: Read Disturb Oriented Error Recovery Conclusion 4
NAND Flash Memory Background Flash Memory Page 256 Read Page M Page 1 Page 257 Pass Page M 1 Page 2 Page 258 Pass Page M 2 Block 0 Block 1 Block N Page 255 Page 511 Pass Page M 255 Page 0 Flash Controller 5
Flash Cell Array Row Block X Column Page Y Sense Amplifiers Sense Amplifiers 6
Flash Cell Floating Gate Drain Gate Vth 2.5 V Source Floating Gate Transistor (Flash Cell) 7
Flash Read Vread 2.5 V Vth 2V Vread 2.5 V Vth 3V Gate 1 0 8
Flash Pass-Through Vpass 5 V Vth 2V Vpass 5 V Vth 3V Gate 1 1 9
Read from Flash Cell Array Vpass 5.0 V Vread 2.5 V Vpass 5.0 V Vpass 5.0 V Correct values for page 2: 3.0V 3.8V (5V) 3.9V Pass 4.8V Page 1 3.5V 2.9V(2.5V)2.4V Read 2.1V Page 2 2.2V 4.3V (5V) 4.6V Pass 1.8V Page 3 3.5V 2.3V (5V) 1.9V Pass 4.3V Page 4 0 0 1 1 10
Read Disturb Problem: “Weak Programming” Effect 3.0V 3.8V (5V) 3.9V Pass 4.8V Page 1 3.5V 2.9V (5V) 2.4V Pass 2.1V Page 2 2.2V 4.3V(2.5V)4.6V Read 1.8V Page 3 3.5V 2.3V (5V) 1.9V Pass 4.3V Page 4 Repeatedly read page 3 (or any page other than page 2) 11
Read Disturb Problem: “Weak Programming” Effect Vpass 5.0 V Vread 2.5 V Vpass 5.0 V Vpass 5.0 V 3.0V 3.8V 3.9V 4.8V Page 1 3.5V 2.9V 2.6V 2.4V 2.1V Page 2 2.2V 4.3V 4.6V 1.8V Page 3 3.5V 2.3V 1.9V 4.3V Page 4 Incorrect values 0 0 0 1 from page 2: High pass-through voltage induces “weak-programming” effect 12
Read disturb errors: Reading from one page can alter the values stored in other unread pages Goal: Mitigate and Recover Read Disturb Errors 13
Outline Background (Problem and Goal) Key Experimental Observations Mitigation: Vpass Tuning Recovery: Read Disturb Oriented Error Recovery Conclusion 14
Methodology FPGA-based flash memory testing platform [Cai , FCCM ‘11] Real 20- to 24-nm MLC NAND flash chips 0 to 1M read disturbs 0 to 15K Program/Erase Cycles (PEC) 15
Read Disturb Effect on Vth Distribution 6 5 PDF 4 3 10-3 0 (No Read Disturbs) 0.25M Read Disturbs 0.5M Read Disturbs 1M Read Disturbs 2 1 0 0 ER state 50 100 Vth gradually increases with read disturb counts P1 state P2 state 150 200 250 300 350 Normalized Threshold Voltage P3 state 400 450 500 16
Other Experimental Observations Lower threshold voltage states are affected more by read disturb Wear-out increases read disturb effect 17
Key Observation Slightly lowering Vpass Reducing The1:Pass-Through Voltage greatly reduces read disturb errors Normalized Tolerable Read Disturb Count 1400 1300 1200 1000 800 600 470 400 200 0 1 1.7 0% 1% 6.8 22 100 2% 3% 4% 5% Percentage of Vpass Reduction 6% 18
Outline Background (Problem and Goal) Key Experimental Observations Mitigation: Vpass Tuning Recovery: Read Disturb Oriented Error Recovery Conclusion 19
Read Disturb Mitigation: Vpass Tuning Key Idea: Dynamically find and apply a lowered Vpass Trade-off for lowering Vpass Allows more read disturbs –Induces more read errors 20
Read Errors Induced by Vpass Reduction Reducing Vpass to 4.9V Vpass 4.9 V Vread 2.5 V Vpass 4.9 V Vpass 4.9 V 3.0V 3.8V 3.9V 4.8V Page 1 3.5V 2.9V 2.4V 2.1V Page 2 2.2V 4.3V 4.6V 1.8V Page 3 3.5V 2.3V 1.9V 4.3V Page 4 0 0 1 1 21
Read Errors Induced by Vpass Reduction Reducing Vpass to 4.7V Vpass 4.7 V Vread 2.5 V Vpass 4.7 V Vpass 4.7 V Incorrect values from page 2: 3.0V 3.8V 3.9V 4.8V Page 1 3.5V 2.9V 2.4V 2.1V Page 2 2.2V 4.3V 4.6V 1.8V Page 3 3.5V 2.3V 1.9V 4.3V Page 4 0 0 1 0 22
Utilizing the Unused ECC Capability 1.0 RBER 0.8 ECC Correction Capability 10-3 Unused ECC capability 0.6 0.4 0.2 0 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 N-day Retention 1. Huge unused ECC correction capability can be used to tolerate read errors 2. Unused ECC capability decreases over time Dynamically adjust Vpass so that read errors fully utilize the unused ECC capability 23
Vpass Reduction Trade-Off Summary Conservatively set Vpass to a high voltage –Accumulates more read disturb errors at the end of each refresh interval No read errors Dynamically adjust Vpass to unused ECC capability Minimize read disturb errors oControl read errors to be tolerable by ECC oIf read errors exceed ECC capability, read again with a higher Vpass to correct read errors 24
Vpass Tuning Steps Perform once for each block every day: 1. Estimate unused ECC capability 2. Aggressively reduce Vpass until read errors exceeds ECC capability 3. Gradually increase Vpass until read error just becomes less than ECC capability 25
Evaluation of Vpass Tuning 19 real workload I/O traces Assume 7-day refresh period Similar methodology as before to determine acceptable Vpass reduction Overhead for a 512 GB flash drive: –128 KB storage overhead for per-block Vpass setting and worst-case page –24.34 sec/day average Vpass Tuning overhead 26
12000 10000 8000 6000 4000 2000 0 Baseline VVpass Tuning pass Tuning homes web-vm mail mds rsrch prn web stg ts proj src wdev usr postmark hm cello99 webSearch financial prxy P/E Cycle Lifetime Vpass Tuning Lifetime Improvements Average lifetime improvement: 21.0% 27
Outline Background (Problem and Goal) Key Experimental Observations Mitigation: Vpass Tuning Recovery: Read Disturb Oriented Error Recovery Conclusion 28
Read Disturb Resistance PDF Disturb-Resistant R Disturb-Prone P N read disturbs N read disturbs Normalized Vth 29
PDF Observation 2: Some Flash Cells Are More Prone to Read Disturb After 250K read disturb: Disturb-prone cells have higher threshold voltages Disturb-resistant cells ER have lower threshold voltages P1 R R P P R Disturb-prone P ER state R Disturb-resistant P P1 state Normalized Vth 30
Read Disturb Oriented Error Recovery (RDR) Triggered by an uncorrectable flash error –Back up all valid data in the faulty block –Disturb the faulty page 100K times (more) –Compare Vth’s before and after read disturb –Select cells susceptible to flash errors (Vref σ Vth Vref σ) –Predict among these susceptible cells Cells with more Vth shifts are disturb-prone Higher Vth state Cells with less Vth shifts are disturb-resistant Lower Vth state 31
RBER RDR Evaluation 12 10 8 6 4 2 0 10-3 RDR No Recovery 0 0.2M 0.4M 0.6M 0.8M 1M Read Disturb Count Reduce total error counts up to 36% @ 1M read disturbs ECC can be used to correct the remaining errors 32
Outline Background (Problem and Goal) Key Experimental Observations Mitigation: Vpass Tuning Recovery: Read Disturb Oriented Error Recovery Conclusion 33
Executive Summary Read disturb errors limit flash memory lifetime today – Apply a high pass-through voltage (Vpass) to multiple pages on a read We characterize read disturb on real NAND flash chips – Slightly lowering Vpass greatly reduces read disturb errors – Some flash cells are more prone to read disturb Technique 1: Mitigate read disturb errors online – Vpass Tuning dynamically finds and applies a lowered Vpass – Flash memory lifetime improves by 21% Technique 2: Recover after failure to prevent data loss – Read Disturb Oriented Error Recovery (RDR) selectively corrects cells more susceptible to read disturb errors – Reduces raw bit error rate (RBER) by up to 36% 34
Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery Yu Cai, Yixin Luo, Saugata Ghose, Erich F. Haratsch*, Ken Mai, Onur Mutlu Carnegie Mellon University, *Seagate Technology
0 20K 40K 60K 80K 100K Read Disturb Count PEC 15K 10K 8K 5K 4K 3K 2K Slope 1.90 10-8 9.10 10-9 7.50 10-9 3.74 10-9 2.37 10-9 1.63 10-9 1.00 10-9 Faster 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 10-3 Slower Raw Bit Error Rate (RBER) Read Disturb Induced RBER Increases Faster with Higher PEC 36
190 189 188 187 186 185 184 183 0 0.25 0.5 0.75 1 Read Disturb Count (Millions) Norm. Vth Standard Deviation Norm. Vth Mean Threshold Voltage Increases with Read Disturb Count 27 25 23 21 19 17 15 0 0.25 0.5 0.75 1 Read Disturb Count (Millions) Showing results for P1 state @ 8K PEC, other states have similar trends 37
Lower Voltage States Are More Prone to Read Disturb 50 45 40 35 30 25 0 0.25 0.5 0.75 1 Read Disturb Count (Millions) 200 Norm. Vth Mean Norm. Vth Mean 55 ER State P1 State 195 190 185 180 175 170 0 0.25 0.5 0.75 1 Read Disturb Count (Millions) 38
Reducing Vpass Increases Tolerable Read Disturb Count 1.6 10-3 1.4 100% 99% 98% 97% 96% 95% 94% RBER 1.2 100% Vpass 99% Vpass 98% Vpass 97% Vpass 96% Vpass 95% Vpass 94% Vpass 1.0 0.8 0.6 0.4 104 105 Pct. Vpass Value Rd. Disturb. Cnt. 106 107 Read Disturb Count 108 109 100% 99% 98% 97% 96% 95% 94% 1x 1.7x 6.8x 22x 100x 470x 1300x 39
Addl. RBER Due to Reduced Vpass Pass-Through Voltage Reduction Induced Read Error 1.0 10-3 0-day 1-day 2-day 6-day 9-day 17-day 21-day 0.75 0.5 0.25 0 480 485 490 495 Relaxed Vpass 500 505 510 40
Read Errors Induced by Vpass Reduction Will generate a read error only if: –Max(Vth) Vpass –Correct read value is 1 These errors do not affect lifetime –can usually be tolerated by the unused ECC capability These errors are temporary –can be corrected (if necessary) by reading with the default Vpass 41
Illustration of Vpass Tuning Results 42
Some Flash Cells Are More Prone to Read Disturb Predict to be P1 state Predict to be ER state - Area I is correct - Area III is correct - Area II is 50/50 - Area IV is 50/50 Showing Vth with 8K PEC from 250K to 350K read disturbs 43
Read Disturb Effect on V th Distribution Normalized Threshold Voltage 10-3 6 5 4 3 2 1 0 0 50 100 150 200 250 300 350 400 450 500 PDF 0 (No Read Disturbs) 0.25M Read Disturbs 0.5M Read Disturbs 1M Read Disturbs ER state P1 state P2 state P3 state V th gradually increases with read disturb counts 16
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