PowerPC Microprocessor Family: The Programming Environments For 32-Bit .
MPCFPE32B/AD 1/97 REV. 1 PowerPC Microprocessor Family: The Programming Environments For 32-Bit Microprocessors
Motorola Inc. 1997. All rights reserved. Portions hereof International Business Machines Corp. 1991–1997. All rights reserved. This document contains information on a new product under development by Motorola and IBM. Motorola and IBM reserve the right to change or discontinue this product without notice. Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or implied copyright or patent licenses granted hereunder by Motorola or IBM to design, modify the design of, or fabricate circuits based on the information in this document. The PowerPC microprocessor family embodies the intellectual property of Motorola and of IBM. However, neither Motorola nor IBM assumes any responsibility or liability as to any aspects of the performance, operation, or other attributes of the microprocessor as marketed by the other party or by any third party. Neither Motorola nor IBM is to be considered an agent or representative of the other, and neither has assumed, created, or granted hereby any right or authority to the other, or to any third party, to assume or create any express or implied obligations on its behalf. Information such as errata sheets and data sheets, as well as sales terms and conditions such as prices, schedules, and support, for the product may vary as between parties selling the product. Accordingly, customers wishing to learn more information about the products as marketed by a given party should contact that party. Both Motorola and IBM reserve the right to modify this document and/or any of the products as described herein without further notice. NOTHING IN THIS DOCUMENT, NOR IN ANY OF THE ERRATA SHEETS, DATA SHEETS, AND OTHER SUPPORTING DOCUMENTATION, SHALL BE INTERPRETED AS THE CONVEYANCE BY MOTOROLA OR IBM OF AN EXPRESS WARRANTY OF ANY KIND OR IMPLIED WARRANTY, REPRESENTATION, OR GUARANTEE REGARDING THE MERCHANTABILITY OR FITNESS OF THE PRODUCTS FOR ANY PARTICULAR PURPOSE. Neither Motorola nor IBM assumes any liability or obligation for damages of any kind arising out of the application or use of these materials. Any warranty or other obligations as to the products described herein shall be undertaken solely by the marketing party to the customer, under a separate sale agreement between the marketing party and the customer. In the absence of such an agreement, no liability is assumed by Motorola, IBM, or the marketing party for any damages, actual or otherwise. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals,” must be validated for each customer application by customer’s technical experts. Neither Motorola nor IBM convey any license under their respective intellectual property rights nor the rights of others. Neither Motorola nor IBM makes any claim, warranty, or representation, express or implied, that the products described in this document are designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the product could create a situation where personal injury or death may occur. Should customer purchase or use the products for any such unintended or unauthorized application, customer shall indemnify and hold Motorola and IBM and their respective officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney’s fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola or IBM was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. IBM, RS/6000, and System/370 are trademarks of International Business Machines Corporation. The PowerPC name, the PowerPC logotype, PowerPC 601, PowerPC 602, PowerPC 603, PowerPC 603e, PowerPC 604, PowerPC 604e, and PowerPC 620 are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation. International Business Machines Corporation is an Equal Opportunity/Affirmative Action Employer.
Overview 1 PowerPC Register Set 2 Operand Conventions 3 Addressing Modes and Instruction Set Summary 4 Cache Model and Memory Coherency 5 Exceptions 6 Memory Management 7 Instruction Set 8 PowerPC Instruction Set Listings A POWER Architecture Cross Reference B Multiple-Precision Shifts C Floating-Point Models D Synchronization Programming Examples E Simplified Mnemonics F Glossary of Terms and Abbreviations GLO Index IND
1 Overview 2 PowerPC Register Set 3 Operand Conventions 4 Addressing Modes and Instruction Set Summary 5 Cache Model and Memory Coherency 6 Exceptions 7 Memory Management 8 Instruction Set A PowerPC Instruction Set Listings B POWER Architecture Cross Reference C Multiple-Precision Shifts D Floating-Point Models E Synchronization Programming Examples F Simplified Mnemonics GLO Glossary of Terms and Abbreviations IND Index
CONTENTS Paragraph Number Title Page Number About This Book Audience . xxvii Organization. xxvii Suggested Reading. xxviii Conventions . xxxi Acronyms and Abbreviations . xxxiii Terminology Conventions .xxxv Chapter 1 Overview 1.1 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 1.2 1.2.1 1.2.2 1.2.2.1 1.2.2.2 1.2.2.3 1.2.3 1.2.3.1 1.2.3.2 1.2.4 1.2.5 1.2.6 1.3 Contents PowerPC Architecture Overview. 1-2 The 64-Bit PowerPC Architecture and the 32-Bit Subset . 1-4 The Levels of the PowerPC Architecture . 1-5 Latitude Within the Levels of the PowerPC Architecture . 1-6 Features Not Defined by the PowerPC Architecture . 1-7 Summary of Architectural Changes in this Revision. 1-7 The PowerPC Architectural Models . 1-8 PowerPC Registers and Programming Model . 1-8 Operand Conventions . 1-9 Byte Ordering . 1-9 Data Organization in Memory and Data Transfers. 1-10 Floating-Point Conventions . 1-10 PowerPC Instruction Set and Addressing Modes . 1-10 PowerPC Instruction Set. 1-11 Calculating Effective Addresses. 1-12 PowerPC Cache Model. 1-13 PowerPC Exception Model. 1-13 PowerPC Memory Management Model . 1-14 Changes in This Revision of The Programming Environments Manual . 1-15 iii
CONTENTS Paragraph Number Title Page Number Chapter 2 PowerPC Register Set 2.1 2.1.1 2.1.2 2.1.3 2.1.3.1 2.1.3.2 2.1.3.3 2.1.4 2.1.5 2.1.6 2.1.7 2.2 2.2.1 2.2.2 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.3.8 2.3.9 2.3.10 2.3.11 2.3.12 2.3.12.1 2.3.13 2.3.13.1 2.3.13.2 2.3.14 2.3.15 2.3.16 2.3.17 iv PowerPC UISA Register Set. 2-1 General-Purpose Registers (GPRs). 2-3 Floating-Point Registers (FPRs) . 2-4 Condition Register (CR) . 2-5 Condition Register CR0 Field Definition . 2-6 Condition Register CR1 Field Definition . 2-6 Condition Register CRn Field—Compare Instruction . 2-7 Floating-Point Status and Control Register (FPSCR). 2-7 XER Register (XER) . 2-11 Link Register (LR). 2-11 Count Register (CTR). 2-12 PowerPC VEA Register Set—Time Base. 2-13 Reading the Time Base . 2-16 Computing Time of Day from the Time Base . 2-16 PowerPC OEA Register Set. 2-17 Machine State Register (MSR) . 2-20 Processor Version Register (PVR) . 2-23 BAT Registers. 2-24 SDR1. 2-27 Segment Registers. 2-28 Data Address Register (DAR) . 2-29 SPRG0–SPRG3 . 2-30 DSISR . 2-30 Machine Status Save/Restore Register 0 (SRR0) . 2-31 Machine Status Save/Restore Register 1 (SRR1) . 2-31 Floating-Point Exception Cause Register (FPECR) . 2-32 Time Base Facility (TB)—OEA . 2-32 Writing to the Time Base. 2-32 Decrementer Register (DEC). 2-33 Decrementer Operation. 2-33 Writing and Reading the DEC . 2-34 Data Address Breakpoint Register (DABR). 2-34 External Access Register (EAR). 2-35 Processor Identification Register (PIR) . 2-36 Synchronization Requirements for Special Registers and for Lookaside Buffers. 2-36 PowerPC Microprocessor Family: The Programming Environments (32-Bit)
CONTENTS Paragraph Number Title Page Number Chapter 3 Operand Conventions 3.1 3.1.1 3.1.2 3.1.2.1 3.1.2.2 3.1.3 3.1.3.1 3.1.3.2 3.1.4 3.1.4.1 3.1.4.2 3.1.4.3 3.1.4.4 3.1.4.5 3.2 3.2.1 3.2.2 3.3 3.3.1 3.3.1.1 3.3.1.2 3.3.1.3 3.3.1.4 3.3.1.5 3.3.1.6 3.3.1.7 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.6.1 3.3.6.1.1 3.3.6.1.2 3.3.6.2 3.3.6.2.1 3.3.6.2.2 3.3.6.2.3 Data Organization in Memory and Data Transfers. 3-1 Aligned and Misaligned Accesses . 3-1 Byte Ordering . 3-2 Big-Endian Byte Ordering . 3-2 Little-Endian Byte Ordering . 3-3 Structure Mapping Examples. 3-3 Big-Endian Mapping . 3-4 Little-Endian Mapping. 3-5 PowerPC Byte Ordering . 3-6 Aligned Scalars in Little-Endian Mode . 3-6 Misaligned Scalars in Little-Endian Mode . 3-9 Nonscalars. 3-10 PowerPC Instruction Addressing in Little-Endian Mode . 3-10 PowerPC Input/Output Data Transfer Addressing in Little-Endian Mode 3-11 Effect of Operand Placement on Performance—VEA . 3-12 Summary of Performance Effects. 3-12 Instruction Restart. 3-14 Floating-Point Execution Models—UISA. 3-15 Floating-Point Data Format . 3-16 Value Representation. 3-18 Binary Floating-Point Numbers. 3-19 Normalized Numbers ( NORM) . 3-19 Zero Values ( 0). 3-20 Denormalized Numbers ( DENORM). 3-20 Infinities ( ) . 3-21 Not a Numbers (NaNs) . 3-21 Sign of Result. 3-22 Normalization and Denormalization. 3-23 Data Handling and Precision . 3-24 Rounding. 3-25 Floating-Point Program Exceptions. 3-28 Invalid Operation and Zero Divide Exception Conditions . 3-35 Invalid Operation Exception Condition. 3-37 Zero Divide Exception Condition. 3-38 Overflow, Underflow, and Inexact Exception Conditions . 3-39 Overflow Exception Condition. 3-41 Underflow Exception Condition. 3-42 Inexact Exception Condition . 3-43 Contents v
CONTENTS Paragraph Number Title Page Number Chapter 4 Addressing Modes and Instruction Set Summary 4.1 4.1.1 4.1.2 4.1.3 4.1.3.1 4.1.3.2 4.1.3.2.1 4.1.3.2.2 4.1.3.2.3 4.1.3.3 4.1.3.4 4.1.4 4.1.4.1 4.1.4.2 4.1.5 4.1.5.1 4.1.5.2 4.1.6 4.2 4.2.1 4.2.1.1 4.2.1.2 4.2.1.3 4.2.1.4 4.2.1.4.1 4.2.1.4.2 4.2.2 4.2.2.1 4.2.2.2 4.2.2.3 4.2.2.4 4.2.2.5 4.2.2.6 4.2.3 4.2.3.1 4.2.3.1.1 4.2.3.1.2 4.2.3.1.3 vi Conventions . 4-3 Sequential Execution Model. 4-3 Computation Modes. 4-3 Classes of Instructions . 4-3 Definition of Boundedly Undefined . 4-4 Defined Instruction Class . 4-4 Preferred Instruction Forms. 4-4 Invalid Instruction Forms . 4-5 Optional Instructions . 4-5 Illegal Instruction Class . 4-6 Reserved Instructions. 4-6 Memory Addressing . 4-7 Memory Operands . 4-7 Effective Address Calculation . 4-7 Synchronizing Instructions . 4-8 Context Synchronizing Instructions . 4-8 Execution Synchronizing Instructions . 4-9 Exception Summary. 4-9 PowerPC UISA Instructions . 4-10 Integer Instructions . 4-10 Integer Arithmetic Instructions. 4-11 Integer Compare Instructions . 4-15 Integer Logical Instructions . 4-16 Integer Rotate and Shift Instructions . 4-18 Integer Rotate Instructions. 4-18 Integer Shift Instructions . 4-19 Floating-Point Instructions . 4-20 Floating-Point Arithmetic Instructions . 4-21 Floating-Point Multiply-Add Instructions . 4-23 Floating-Point Rounding and Conversion Instructions . 4-25 Floating-Point Compare Instructions. 4-25 Floating-Point Status and Control Register Instructions . 4-26 Floating-Point Move Instructions . 4-28 Load and Store Instructions . 4-28 Integer Load and Store Address Generation. 4-29 Register Indirect with Immediate Index Addressing for Integer Loads and Stores . 4-29 Register Indirect with Index Addressing for Integer Loads and Stores. 4-30 Register Indirect Addressing for Integer Loads and Stores. 4-30 PowerPC Microprocessor Family: The Programming Environments (32-Bit)
CONTENTS Paragraph Number 4.2.3.2 4.2.3.3 4.2.3.4 4.2.3.5 4.2.3.6 4.2.3.7 4.2.3.7.1 Title Page Number 4.2.3.8 4.2.3.9 4.2.4 4.2.4.1 4.2.4.1.1 4.2.4.1.2 4.2.4.1.3 4.2.4.1.4 4.2.4.1.5 4.2.4.1.6 4.2.4.2 4.2.4.3 4.2.4.4 4.2.4.5 4.2.4.6 4.2.4.7 4.2.5 4.2.5.1 4.2.5.2 4.2.6 4.2.7 4.3 4.3.1 4.3.2 4.3.3 4.3.3.1 4.3.4 4.4 4.4.1 4.4.2 4.4.2.1 4.4.2.2 Integer Load Instructions . 4-31 Integer Store Instructions. 4-33 Integer Load and Store with Byte-Reverse Instructions. 4-34 Integer Load and Store Multiple Instructions . 4-35 Integer Load and Store String Instructions . 4-36 Floating-Point Load and Store Address Generation . 4-37 Register Indirect with Immediate Index Addressing for Floating-Point Loads and Stores. 4-37 Register Indirect with Index Addressing for Floating-Point Loads and Stores. 4-38 Floating-Point Load Instructions . 4-38 Floating-Point Store Instructions . 4-40 Branch and Flow Control Instructions. 4-41 Branch Instruction Address Calculation . 4-41 Branch Relative Addressing Mode. 4-42 Branch Conditional to Relative Addressing Mode. 4-42 Branch to Absolute Addressing Mode. 4-43 Branch Conditional to Absolute Addressing Mode. 4-44 Branch Conditional to Link Register Addressing Mode . 4-45 Branch Conditional to Count Register Addressing Mode . 4-46 Conditional Branch Control. 4-47 Branch Instructions . 4-49 Simplified Mnemonics for Branch Processor Instructions . 4-50 Condition Register Logical Instructions . 4-50 Trap Instructions . 4-51 System Linkage Instruction—UISA. 4-52 Processor Control Instructions—UISA . 4-52 Move to/from Condition Register Instructions. 4-52 Move to/from Special-Purpose Register Instructions (UISA). 4-53 Memory Synchronization Instructions—UISA . 4-53 Recommended Simplified Mnemonics. 4-55 PowerPC VEA Instructions . 4-56 Processor Control Instructions—VEA. 4-56 Memory Synchronization Instructions—VEA . 4-57 Memory Control Instructions—VEA . 4-58 User-Level Cache Instructions—VEA . 4-58 External Control Instructions. 4-62 PowerPC OEA Instructions . 4-63 System Linkage Instructions—OEA . 4-63 Processor Control Instructions—OEA. 4-64 Move to/from Machine State Register Instructions. 4-64 Move to/from Special-Purpose Register Instructions (OEA) . 4-64 Contents vii 4.2.3.7.2
CONTENTS Paragraph Number 4.4.3 4.4.3.1 4.4.3.2 4.4.3.3 Title Page Number Memory Control Instructions—OEA . 4-65 Supervisor-Level Cache Management Instruction . 4-65 Segment Register Manipulation Instructions. 4-66 Translation Lookaside Buffer Management Instructions . 4-67 Chapter 5 Cache Model and Memory Coherency 5.1 5.1.1 5.1.1.1 5.1.1.2 5.1.2 5.1.3 5.1.4 5.1.4.1 5.1.4.1.1 5.1.4.1.2 5.1.4.1.3 5.1.4.1.4 5.1.4.1.5 5.1.4.2 5.1.5 5.1.5.1 5.1.5.1.1 5.1.5.1.2 5.1.5.1.3 5.1.5.1.4 5.1.5.2 5.1.5.2.1 5.1.5.2.2 5.2 5.2.1 5.2.1.1 5.2.1.2 5.2.1.3 5.2.1.4 5.2.1.5 5.2.1.5.1 5.2.1.5.2 5.2.1.5.3 viii The Virtual Environment . 5-1 Memory Access Ordering. 5-2 Enforce In-Order Execution of I/O Instruction . 5-2 Synchronize Instruction . 5-3 Atomicity . 5-4 Cache Model . 5-5 Memory Coherency . 5-5 Memory/Cache Access Modes . 5-6 Pages Designated as Write-Through . 5-6 Pages Designated as Caching-Inhibited. 5-6 Pages Designated as Memory Coherency Required. 5-7 Pages Designated as Memory Coherency Not Required. 5-7 Pages Designated as Guarded. 5-7 Coherency Precautions . 5-7 VEA Cache Management Instructions . 5-8 Data Cache Instructions . 5-8 Data Cache Block Touch (dcbt) and Data Cache Block Touch for Store (dcbtst) Instructions. 5-8 Data Cache Block Set to Zero (dcbz) Instruction . 5-9 Data Cache Block Store (dcbst) Instruction. 5-9 Data Cache Block Flush (dcbf) Instruction. 5-10 Instruction Cache Instructions . 5-10 Instruction Cache Block Invalidate Instruction (icbi) . 5-11 Instruction Synchronize Instruction (isync) . 5-11 The Operating Environment . 5-12 Memory/Cache Access Attributes . 5-12 Write-Through Attribute (W) . 5-13 Caching-Inhibited Attribute (I). 5-14 Memory Coherency Attribute (M). 5-15 W, I, and M Bit Combinations. 5-15 The Guarded Attribute (G) . 5-16 Performing Operations Out of Order. 5-16 Guarded Memory. 5-17 Out-of-Order Accesses to Guarded Memory. 5-18 PowerPC Microprocessor Family: The Programming Environments (32-Bit)
CONTENTS Paragraph Number 5.2.2 5.2.3 Title Page Number I/O Interface Considerations. 5-19 OEA Cache Management Instruction— Data Cache Block Invalidate (dcbi) . 5-19 Chapter 6 Exceptions 6.1 6.1.1 6.1.2 6.1.2.1 6.1.2.2 6.1.2.3 6.1.2.4 6.1.2.4.1 6.1.2.4.2 6.1.3 6.1.3.1 6.1.3.2 6.1.4 6.1.5 6.2 6.2.1 6.2.2 6.2.3 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.6.1 6.4.6.1.1 6.4.6.1.2 6.4.6.2 6.4.6.3 6.4.7 6.4.8 6.4.9 6.4.10 Exception Classes .
The PowerPC microprocessor family embodies the intellectual property of Motorola and of IBM. However, neither Motorola nor IBM assumes any responsibility or liability as to any aspects of the performance, operation, or other attributes of the microprocessor as marketed by the other party or by
a low-power, 32-bit member of the PowerPC processor family. In this document, the terms "PowerPC 603 microprocessor" and "603" are used to denote the second microprocessor from the PowerPC architecture family. The PowerPC 603 microprocessors are available from IBM as PPC603 and from Motorola as MPC603. F r e e s c a l e S e m i c o n d .
May 02, 2018 · D. Program Evaluation ͟The organization has provided a description of the framework for how each program will be evaluated. The framework should include all the elements below: ͟The evaluation methods are cost-effective for the organization ͟Quantitative and qualitative data is being collected (at Basics tier, data collection must have begun)
Silat is a combative art of self-defense and survival rooted from Matay archipelago. It was traced at thé early of Langkasuka Kingdom (2nd century CE) till thé reign of Melaka (Malaysia) Sultanate era (13th century). Silat has now evolved to become part of social culture and tradition with thé appearance of a fine physical and spiritual .
On an exceptional basis, Member States may request UNESCO to provide thé candidates with access to thé platform so they can complète thé form by themselves. Thèse requests must be addressed to esd rize unesco. or by 15 A ril 2021 UNESCO will provide thé nomineewith accessto thé platform via their émail address.
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including a block diagram showing the major functional components. It also provides an overview of the PowerPC architecture, and information about how the 601 implementation differs from the architectural definitions. This document is divided into three parts: Part 1, "PowerPC 601 Microprocessor Overview," provides an overview of the 601
“Accounting is the art of recording, classifying and summarizing in a significant manner and in terms of money, transactions and events which are, in part at least, of a financial character, and interpreting the result thereof”. Definition by the American Accounting Association (Year 1966): “The process of identifying, measuring and communicating economic information to permit informed .
