Block Diagram - Siemens
1 2 3 4 5 6 7 8 Block diagram A A B GRANT OF A PATENT OR THE REGISTRATION OF A UTILITY MODEL OR DESIGN Copyright (C) Siemens AG, 2006 Memories (P. 017-024) 018 - Level shifters 019 - Level shifters 020 - SDRAM - Micron 021 - SDRAM - ISSI 022 - Burst mode FLASH 023 - EMC connectors E Test and Debug (P. 002-008) ERTEC 200P (P. 009-014) RJ45, POF (P. 015-016) 002 - LEDs 003 - User GPIOs, octal switch 004 - Debug bus switch, TMP, EEPROM, RS485 005 - Trace MICTOR 006 - Trace, User GPIOs bus switches 007 - USB 008 - Use Case MICTORs 009 - ERTEC 200P 010 - ERTEC 200P 011 - ERTEC 200P 012 - ERTEC 200P 013 - ERTEC 200P - PWR 014 - ERTEC 200P - PWR 015 - RJ45 016 - POF 017 - POF FPGA (P. 025-027) PSU (P. 029-032) 024 - FPGA 025 - FPGA 026 - FPGA 028 - External PSU convertor 029 - Power convertors 030 - Power switching 031 - Power sensing PCIe (P. 028) RST, CFG (P. 033-034) 027 - PCIe connector 032 - Config pin headers 033 - Reset circuit COPYING OF THIS DOCUMENT AND GIVING IT TO OTHERS AND THE USE OR COMMUNICATION OF THE CONTENTS THEREOF ARE FORBIDDEN D WITHOUT EXPRESS AUTHORITY. OFFENDERS ARE LIABLE TO THE PAYMENT OF DAMAGES ALL RIGHTS ARE RESERVED IN THE EVENT OF THE C B C D E updateDate 13/02/05 updateTime 07:37:56 F Unmounted Components are displayed blue or with dashed lines 002 Ind. Rev. Modification Date 1 Date Init. Appr. Name Norm 14.1.2013 Siemens AG Item No.: EB200P Documentation Block Diagram 2 3 4 5 Sheet 1 40 Sheets A5E31374985A Circuit Diagram 6 7 8 F
1 2 3 4 5 6 7 8 User and status LEDs GPIO[0-95] 3:B2;6:B1 C2 2u2 16 V User LEDs 1 R2 EN 47 46 44 43 USER GPIO[0] USER GPIO[1] USER GPIO[2] USER GPIO[3] 2 2 3 5 6 1 750R A K PCB User GPIO 0 H20 2 LOL29K ORANGE A R3 1 750R 2 74ALVC16244 1 750R A LOL29K ORANGE K 1 WITHOUT EXPRESS AUTHORITY. OFFENDERS ARE LIABLE TO THE PAYMENT OF DAMAGES ALL RIGHTS ARE RESERVED IN THE EVENT OF THE USER GPIO[0-15] 48 2 LOL29K ORANGE A 8 9 11 12 1 750R 2 A K 2 LOL29K ORANGE A 1 2 74ALVC16244 1 750R A LOL29K ORANGE K 2 A R8 1 25 2 13 14 16 17 1 750R A LOL29K ORANGE K 2 A R10 1 750R 2 74ALVC16244 1 750R A LOL29K ORANGE K 2 A COPYING OF THIS DOCUMENT AND GIVING IT TO OTHERS AND THE USE OR COMMUNICATION OF THE CONTENTS THEREOF ARE FORBIDDEN R12 1 24 2 19 20 22 23 1 750R A LOL29K ORANGE K 2 A R14 1 750R 2 74ALVC16244 1 750R A LOL29K ORANGE K 2 A R16 K LOL29K ORANGE GND 2 1 2 1 1 750R 2 Rev. LOL29K ORANGE A K 13 14 16 17 1 750R LGA67K GREEN A A K 2 LYA67K YELLOW 1 2 A K 1 1 24 2 19 20 22 23 1 750R 1 2 D3 1 750R A K 2 LYL29K YELLOW K PCB Maintenance K PCB Diagnostic H13 2 A K LYL29K YELLOW PCB PROFIenergy H14 2 E LGL29K GREEN A K PCB Sync H15 2 A K LGL29K GREEN PCB FO-1 H16 2 D PCB Error LSL29K RED A LYL29K YELLOW A R30 K PCB FO-2 H17 750R LYL29K YELLOW GND GND PCB Power H12 R29 74ALVC16244 Bracket Error LSA67K RED A R28 750R K H11 R27 EN 30 29 27 26 GPIO[28] GPIO[29] GPIO[30] GPIO[31] 750R Bracket Maintenance H10 LGL29K GREEN Modification Date 1 Date Init. Appr. Name Norm 14.1.2013 Siemens AG GND Item No.: EB200P Test and debug LEDs 2 3 4 5 Sheet 2 40 Sheets A5E31374985A Circuit Diagram 6 7 C Bracket Power H1 R25 750R K LGA67K GREEN A R24 750R Bracket Sync H2 R23 EN FPGA INFO H3 R21 750R K Unmounted Components are displayed blue or with dashed lines 002 Ind. A H4 updateDate 13/02/05 updateTime 07:37:56 F LGL29K GREEN R20 750R FPGA DONE H36 2 750R FPGA INIT (ERROR) A K R26 PCB User GPIO 15 H35 750R 1 D3 PCB User GPIO 14 H34 LOL29K ORANGE 8 9 11 12 74ALVC16244 PCB User GPIO 13 H33 R15 D2 K A B H5 R19 EN 36 35 33 32 GPIO[25] GPIO[26] GPIO[27] PCB User GPIO 12 H32 LOL29K ORANGE 2 750R 1 25 PCB User GPIO 11 H31 R13 EN 30 29 27 26 USER GPIO[12] USER GPIO[13] USER GPIO[14] USER GPIO[15] 750R K 750R GND K R22 PCB User GPIO 10 H30 LOL29K ORANGE 750R A H6 2 R18 D3 PCB User GPIO 9 H29 R11 D2 K 1 4 10 15 21 28 34 39 45 RED P3.3V LSL29K R398 74ALVC16244 PCB User GPIO 8 H28 LOL29K ORANGE D3 R17 1 41 40 38 37 PCB User GPIO 7 H27 R9 EN 36 35 33 32 USER GPIO[8] USER GPIO[9] USER GPIO[10] USER GPIO[11] 750R K 42 31 18 7 max 40mA GND GND VCC GND VCC GND VCC GND VCC GND GND GND FPGA LEDs 1 48 PCB User GPIO 6 H26 LOL29K ORANGE 2 3 5 6 P3.3V GND 1 EN 4 10 15 21 28 34 39 45 Status LEDs PCB User GPIO 5 H25 R1 D2 K D2 74ALVC16244 PCB User GPIO 4 H24 42 31 18 7 max 40mA GND GND VCC GND VCC GND VCC GND VCC GND GND GND GND D3 PCB User GPIO 3 LOL29K ORANGE R7 750R K H23 R6 EN 41 40 38 37 USER GPIO[4] USER GPIO[5] USER GPIO[6] USER GPIO[7] 750R PCB User GPIO 2 H22 2 1 C4 100n 16 V 47 46 44 43 PCB User GPIO 1 H21 R4 D2 K 1 GPIO[0-95] 1 C E GND P3.3V GND R5 D 100n 16 V GND P3.3V USER GPIO[0-15] GRANT OF A PATENT OR THE REGISTRATION OF A UTILITY MODEL OR DESIGN Copyright (C) Siemens AG, 2006 B 2u2 16 V C3 P3.3V 1 31:B8;33:B3 4:B1;5:C2;6:B1; 8:B1;9:E1;10:A3; 16:A3;16:C3;25:A1; 26:A2;32:A5 C1 P3.3V 2 26:B6 P3.3V 2 A FPGA INITN FPGA DONE FPGA INFO PSU PG 1 5:E2;25:B6 FPGA INITN FPGA DONE FPGA INFO PSU PG 2 25:B6 8 F
1 2 3 4 5 6 7 8 User GPIOs P3.3V P3.3V P3.3V P3.3V P3.3V P3.3V 1 1 1 1 1 1 1 R53 B 2 2 470R 9 8 R40 R42 R46 R48 R52 R54 2 2 2 2 2 2 2 2 2 4K7 2 4K7 2 4K7 1 1 1 R50 4K7 2 4K7 2 4K7 1 1 1 R44 4K7 2 4K7 2 4K7 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND C5 2u2 16 V GND GND C6 100n 16 V GND C7 10n 50 V P3.3V C8 1n 50 V GND 1 R38 4K7 1 1 1 1 R37 4K7 P3.3V 2 R36 4K7 P3.3V 1 R35 4K7 D P3.3V 2 R34 4K7 1 1 1 1 R33 4K7 C 1 R32 4K7 X50 X50 X50 X50 X50 X50 X50 X50 X50 X50 X50 X50 X50 X50 X50 X50 X50 X50 X50 X50 2 R31 1 1 WITHOUT EXPRESS AUTHORITY. OFFENDERS ARE LIABLE TO THE PAYMENT OF DAMAGES ALL RIGHTS ARE RESERVED IN THE EVENT OF THE USER GPIO[0] USER GPIO[1] USER GPIO[2] USER GPIO[3] USER GPIO[4] USER GPIO[5] USER GPIO[6] USER GPIO[7] USER GPIO[8] USER GPIO[9] USER GPIO[10] USER GPIO[11] USER GPIO[12] USER GPIO[13] USER GPIO[14] USER GPIO[15] 19 20 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 1 USER GPIO[0] USER GPIO[1] USER GPIO[2] USER GPIO[3] USER GPIO[4] USER GPIO[5] USER GPIO[6] USER GPIO[7] USER GPIO[8] USER GPIO[9] USER GPIO[10] USER GPIO[11] USER GPIO[12] USER GPIO[13] USER GPIO[14] USER GPIO[15] P3.3V 2 7 S1 10 2 5 4 S1 11 2 12 2 R51 470R S1 R49 470R S1 R47 470R 13 2 3 S1 14 2 2 S1 15 2 16 1 R45 470R 6 R43 470R S1 R41 470R S1 R39 GND COPYING OF THIS DOCUMENT AND GIVING IT TO OTHERS AND THE USE OR COMMUNICATION OF THE CONTENTS THEREOF ARE FORBIDDEN E P3.3V 470R C D P3.3V 1 USER GPIO[0-15] 2:A1;6:B1 2 B A GRANT OF A PATENT OR THE REGISTRATION OF A UTILITY MODEL OR DESIGN Copyright (C) Siemens AG, 2006 A E updateDate 13/02/05 updateTime 07:37:56 F Unmounted Components are displayed blue or with dashed lines 002 Ind. Rev. Modification Date 1 Date Init. Appr. Name Norm 14.1.2013 Siemens AG Item No.: EB200P Test and debug User octal switch and GPIOs 2 3 4 5 Sheet 3 40 Sheets A5E31374985A Circuit Diagram 6 7 8 F
1 2 3 4 5 6 7 8 Test and debug circuits A A 1 1 TEST XUART EN TEST XTRACE EN TEST XTEMP EN TEST XEEPROM EN TEST XUART EN TEST XTRACE EN B GPIO[0-95] GPIO[0-95] C22 2u2 16 V GND C24 100n 16 V 1 SCL WC max 10mA EEPROM GPIO[0] 4 SDA GPIO[9] 5 R60 1K 1 R64 1K 1K 1K GND GND GND GND GND D5 Rev. 5:B8 5:B8 1 X12 RS485 SYNC R68 2 3 X12 X12 R69 100K 100K E GND GND GND GND Unmounted Components are displayed blue or with dashed lines 002 Ind. R70 100R SYNC N updateDate 13/02/05 updateTime 07:37:55 F SYNC P 2 8 VCC GND 5 8 VCC GND 4 5:B8 D 6 7 1 1 D7 5:B8 5:D8 100K P3.3V P3.3V R66 PIPESTAT[0] PIPESTAT[1] PIPESTAT[2] TRACESYNC TRACECLK D7 24C16 7:D7 R67 SN65HVD10 D5 R59 1 C 7:D7 P3.3V GPIO[16] GPIO[17] NC GND 1 GND 1n 50 V 2 1 1 2 GND P3.3V C27 1 GND P3.3V 10n 50 V 1 1 2 1 GND 100n 16 V C25 6 7 1 2 3 EEPROM SCL P3.3V 2 GND C23 P3.3V 2 1n 50 V User EEPROM 7:D7 7:C7 1 1 2 1 2 2u2 16 V P3.3V 2 GND C21 GND P3.3V C20 4K7 2 10n 50 V P3.3V 1 C17 R65 UART TX UART RX UART RTS UART CTS 2 5 6 9 10 15 16 19 20 23 D6 RS485 sync max 100mA 3 EN1 2 EN2 EEPROM SDA 2 GND P3.3V 2 1 2 1 1n 50 V P3.3V GND 4K7 1 10n 50 V GPIO[35] GPIO[36] GPIO[37] GPIO[34] GPIO[54] 1 2 1B 3 4 5 1 2 2B 3 4 5 2 P3.3V D4 R63 GND P3.3V C19 2 1 C16 GND 2 GND 100n 16 V 1n 50 V GND P3.3V GND P3.3V C14 C18 TMP123 GND P3.3V 2 1 2 2u2 16 V 10n 50 V 1 100n 16 V 2 1 C13 GND P3.3V C11 C15 GND P3.3V 1 COPYING OF THIS DOCUMENT AND GIVING IT TO OTHERS AND THE USE OR COMMUNICATION OF THE CONTENTS THEREOF ARE FORBIDDEN 2u2 16 V 2 C10 P3.3V 2 100n 16 V 2 C12 1 P3.3V 2 2 C9 2u2 16 V 1 P3.3V U3 1 2 3 1A 4 5 1 2 3 2A 4 5 1 4K7 3 4 7 8 11 14 17 18 21 22 2 R62 GPIO[14] GPIO[15] GPIO[13] GPIO[12] 1 TEMP XCS TEMP SCK TEMP SO 1 2 5 6 9 10 15 16 19 20 23 TEMP-SENS U SO 6 CS SCK NC U- 3 5 4 2 1 2 10K 74CB3Q3384 VCC GND OE1 OE2 2 R61 GPIO[0-95] 1 2 1B 3 4 5 1 2 2B 3 4 5 max 10mA 1 1 2 3 1A 4 5 1 2 3 2A 4 5 GND GND P3.3V E 3 4 7 8 11 14 17 18 21 22 P3.3V 24 12 1 13 Temperature sensor 1 WITHOUT EXPRESS AUTHORITY. OFFENDERS ARE LIABLE TO THE PAYMENT OF DAMAGES ALL RIGHTS ARE RESERVED IN THE EVENT OF THE GPIO[15] GPIO[14] 74CB3Q3384 VCC GND OE1 OE2 max 5mA P3.3V 1 GPIO[17] GPIO[16] GPIO[19] C 24 12 1 13 P3.3V 2 TEST XTEMP EN TEST XEEPROM EN D max 5mA P3.3V 2 2:A1;5:C2;6:B1;32:B8 8:B1;9:E1;10:A3; 16:A3;16:C3;25:A1; 26:A2;32:A5 10K 1 32:B8 R58 10K 2 6:B1;25:D7;32:B8 R57 2 2 10K 2 R56 10K P3.3V 2 R55 32:B8 P3.3V 1 1 P3.3V 2 B GRANT OF A PATENT OR THE REGISTRATION OF A UTILITY MODEL OR DESIGN Copyright (C) Siemens AG, 2006 P3.3V Modification Date 1 Date Init. Appr. Name Norm 14.1.2013 Siemens AG Item No.: EB200P Test and debug Debug bus switch, TMP, EEPROM, RS485 2 3 4 5 Sheet 4 40 Sheets A5E31374985A Circuit Diagram 6 7 8 F
1 2 3 4 5 6 7 8 Trace and JTAG conectors P3.3V 17 JTAG DBGRQ X31 19 JTAG DBACK X30 33 TRACEPKT[10] X30 34 PIPESTAT[2] X31 10 X30 31 TRACEPKT[11] X30 32 TRACEPKT[12] X30 30 TRACEPKT[0] X31 X30 29 12 TRACEPKT[13] X30 28 TRACEPKT[1] X31 X30 27 14 TRACEPKT[14] X30 26 TRACEPKT[2] X31 X30 25 16 23 TRACEPKT[15] TRACEPKT[3] 18 X30 24 X31 X30 X30 22 TRACEPKT[4] X31 X30 21 ERTEC XTRST 20 X30 19 ERTEC TDI X30 20 TRACEPKT[5] X30 17 ERTEC TMS X30 18 TRACEPKT[6] X30 15 ERTEC TCK X30 16 TRACEPKT[7] X30 13 ERTEC RTCK X30 14 X30 11 ERTEC TDO X30 12 X30 9 ERTEC XSRST X30 10 X30 7 TRACE DBGRQ X30 8 TRACE DBACK X30 5 X30 6 TRACECLK X30 4 X30 2 GND GPIO[0-95] 1 GPIO[3] 2 R406 R71 1 GPIO[2] 10K 2 R72 GND COPYING OF THIS DOCUMENT AND GIVING IT TO OTHERS AND THE USE OR COMMUNICATION OF THE CONTENTS THEREOF ARE FORBIDDEN GND 2:A1;25:B6 24:B1 24:B1 24:B1 24:B1 GND 10n 50 V GND TRACESYNC TRACESYNC 4:D8 C P3.3V 1n 50 V 1 C32 R407 10K D 2 P3.3V 2 C31 1 P3.3V 2 100n 16 V 1 C30 1 C29 P3.3V 2 P3.3V FPGA JTAG connector P3.3V GND X32 1 X32 2 X30 3 X32 3 X32 4 X30 1 X32 5 X32 6 X32 7 X32 8 X32 9 X32 10 X30 X30 X30 X30 X30 FPGA DONE FPGA TDO FPGA TDI FPGA TMS FPGA TCK FPGA PROGRAMN GND P3.3V C33 S1 S2 S3 S4 S5 GND 2u2 16 V GND C34 2u2 16 V P3.3V C35 100n 16 V P3.3V C37 10n 50 V P3.3V C39 1n 50 V GND GND GND GND P3.3V P3.3V P3.3V P3.3V C36 100n 16 V GND C38 10n 50 V GND GND C40 1n 50 V TRACECLK 4:D8 E GND 25:B6 updateDate 13/02/05 updateTime 07:37:56 F Unmounted Components are displayed blue or with dashed lines 002 Ind. B 2 0R 0R 2u2 16 V E X31 8 1 X31 PIPESTAT[1] 1 X31 15 X30 36 4:C8 2 X31 13 TRACEPKT[9] PIPESTAT[0-2] PIPESTAT[0] 1 X31 11 38 2 X31 9 6 X30 35 6:B8 X30 TRACEPKT[8] 1 X31 7 X31 37 2 5 X30 1 X31 X31 4 TRACEPKT[0-15] TRACEPKT[0-15] 2 X31 3 X31 2 1 X31 1 2 D WITHOUT EXPRESS AUTHORITY. OFFENDERS ARE LIABLE TO THE PAYMENT OF DAMAGES ALL RIGHTS ARE RESERVED IN THE EVENT OF THE C P3.3V 2 ERTEC 200P JTAG connector 2:A1;4:B1;6:B1; 8:B1;9:E1;10:A3; 16:A3;16:C3;25:A1; 26:A2;32:A5 ERTEC 200P trace connector 1 9:B1 2 GRANT OF A PATENT OR THE REGISTRATION OF A UTILITY MODEL OR DESIGN Copyright (C) Siemens AG, 2006 B 9:C1 1 9:B1 9:C1 2 9:C1 9:C1 A 1 9:C1 2 6:E8 A TRACE DBACK TRACE DBGRQ ERTEC XSRST ERTEC TDO ERTEC RTCK ERTEC TCK ERTEC TMS ERTEC TDI ERTEC XTRST 1 6:E8 Rev. Modification Date 1 Date Init. Appr. Name Norm 14.1.2013 Siemens AG Item No.: EB200P Debug Trace Mictor, FPGA JTAG, ERTEC JTAG 2 3 4 5 Sheet 5 40 Sheets A5E31374985A Circuit Diagram 6 7 8 F
1 2 3 4 5 6 7 8 Bus switheches for user GPIOs and trace interface P3.3V A 1 A R73 32:B8 4:B1;25:D7;32:B8 2:A1;4:B1;5:C2; 8:B1;9:E1;10:A3; 16:A3;16:C3;25:A1; 26:A2;32:A5 TEST XUSERGPIO EN TEST XTRACE EN Bus switheches for user GPIOs TRACEPKT[0-15] 5:B8 2:A1;3:B2 max 5mA 74CB3Q3384 VCC GND OE1 OE2 3 4 7 8 11 14 17 18 21 22 1 2 3 1A 4 5 1 2 3 2A 4 5 1 2 1B 3 4 5 1 2 2B 3 4 5 P3.3V 2 5 6 9 10 15 16 19 20 23 USER GPIO[0] USER GPIO[1] USER GPIO[2] USER GPIO[3] USER GPIO[4] USER GPIO[5] USER GPIO[6] USER GPIO[7] USER GPIO[8] USER GPIO[9] D8 GPIO[18] GPIO[19] GPIO[20] GPIO[21] GPIO[22] GPIO[23] 24 12 1 13 74CB3Q3384 VCC GND OE1 OE2 3 4 7 8 11 14 17 18 21 22 1 2 3 1A 4 5 1 2 3 2A 4 5 1 2 1B 3 4 5 1 2 2B 3 4 5 2 5 6 9 10 15 16 19 20 23 GPIO[0-95] GPIO[0-95] WITHOUT EXPRESS AUTHORITY. OFFENDERS ARE LIABLE TO THE PAYMENT OF DAMAGES ALL RIGHTS ARE RESERVED IN THE EVENT OF THE 24 12 1 13 max 5mA COPYING OF THIS DOCUMENT AND GIVING IT TO OTHERS AND THE USE OR COMMUNICATION OF THE CONTENTS THEREOF ARE FORBIDDEN GPIO[38] GPIO[39] GPIO[40] GPIO[41] GPIO[42] GPIO[43] GPIO[44] GPIO[45] GPIO[46] GPIO[47] 24 12 1 13 74CB3Q3384 VCC GND OE1 OE2 3 4 7 8 11 14 17 18 21 22 1 2 3 1A 4 5 1 2 3 2A 4 5 1 2 1B 3 4 5 1 2 2B 3 4 5 TRACEPKT[0] TRACEPKT[1] TRACEPKT[2] TRACEPKT[3] TRACEPKT[4] TRACEPKT[5] TRACEPKT[6] TRACEPKT[7] TRACEPKT[8] TRACEPKT[9] C USER GPIO[10] USER GPIO[11] USER GPIO[12] USER GPIO[13] USER GPIO[14] USER GPIO[15] GPIO[48] GPIO[49] GPIO[50] GPIO[51] GPIO[52] GPIO[53] GPIO[3] GPIO[2] 24 12 1 13 74CB3Q3384 VCC GND OE1 OE2 3 4 7 8 11 14 17 18 21 22 1 2 3 1A 4 5 1 2 3 2A 4 5 1 2 1B 3 4 5 1 2 2B 3 4 5 2 5 6 9 10 15 16 19 20 23 D TRACEPKT[10] TRACEPKT[11] TRACEPKT[12] TRACEPKT[13] TRACEPKT[14] TRACEPKT[15] TRACE DBACK TRACE DBGRQ 5:A2 5:A2 D11 GND E GND GND GND GND GND GND GND GND GND GND GND GND GND Rev. GND 10n 50 V GND C56 1n 50 V 1 C55 P3.3V 2 100n 16 V 1 C54 P3.3V 2 2u2 16 V 1 C53 P3.3V 2 1n 50 V 1 C52 P3.3V 2 10n 50 V 1 C51 P3.3V 2 100n 16 V 1 C50 P3.3V 2 2u2 16 V 1 C49 P3.3V 2 1n 50 V 1 C48 2 10n 50 V P3.3V 1 C47 P3.3V 2 100n 16 V 1 C46 P3.3V 2 2u2 16 V 1 C45 P3.3V 2 1n 50 V 1 C44 P3.3V 2 10n 50 V 1 C43 P3.3V 2 100n 16 V 1 C42 P3.3V 2 2u2 16 V P3.3V 1 C41 1 P3.3V GND Unmounted Components are displayed blue or with dashed lines 002 Ind. 2 5 6 9 10 15 16 19 20 23 max 5mA updateDate 13/02/05 updateTime 07:37:56 F B D10 D9 GND 2 E GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[16] GPIO[17] max 5mA USER GPIO[0-15] P3.3V C D Bus switheches for trace interface GPIO[0-95] USER GPIO[0-15] 2 B GRANT OF A PATENT OR THE REGISTRATION OF A UTILITY MODEL OR DESIGN Copyright (C) Siemens AG, 2006 2 10K Modification Date 1 Date Init. Appr. Name Norm 14.1.2013 Siemens AG Item No.: EB200P Test and debug Trace and user GPIOs bus switches 2 3 4 5 Sheet 6 40 Sheets A5E31374985A Circuit Diagram 6 7 8 F
1 2 3 4 5 6 7 8 USB to serial converter 100n 16 V 1K 1 2 1 K A R79 GND 1 1 1 2 2 2 2 1 1 P3.3V C70 2u2 16 V 2 1K5 2 D12 GND C72 10n 50 V P3.3V C73 1n 50 V GND GND R83 10K GND GND GND GND GND 100n 16 V GND C68 10n 50 V GND C69 1n 50 V GND 1 C67 P3.3V 2 1n 50 V 1 C66 P3.3V 2 10n 50 V P3.3V 1 C65 P3.3V 2 100n 16 V 1 C64 P3.3V 2 2u2 16 V 1 C61 GND P3.3V 2 GND 1 P3.3V GND updateDate 13/02/05 updateTime 07:37:55 F Unmounted Components are displayed blue or with dashed lines 002 Ind. Rev. D 2 2 GND 100n 16 V P3.3V 1 GND P3.3V C71 4:C8 4:C8 E 2 GND GND 2 100n 1 kV 1M 22 5 2 4:C8 4:C8 1 R74 15K UART RX UART TX UART CTS UART RTS UART RX UART TX UART CTS UART RTS GND 2 C57 D13 19 17 25 VCC GND 8 4 VDD18 GND 18 3 VCC GND 28 R81 C 8 VCC GND 4 TUSB3410 USB P1.8V 24C256 P3.3V D12 GND 1 1 R80 15K 1 COPYING OF THIS DOCUMENT AND GIVING IT TO OTHERS AND THE USE OR COMMUNICATION OF THE CONTENTS THEREOF ARE FORBIDDEN GND D13 GND R82 S X11 Note: Preprogrammed EEPROM will be used (A5E03799388) max 10mA 1 A0 EEPROM 2 A1 3 A2/NC 6 SCL 7 WP 5 SDA 1 VREGEN SOUT/IR SOUT SIN/IR SIN WAKEUP CLKOUT PUR SUSPEND 12 C62 P3.3V USB6B1 E TEST0 TEST1 1 V1 B 4K7 2 8 7 6 5 1 2 3 4 16 RESET 2 1 3 2 5 RI/CP R87 4K7 1 9 1 WITHOUT EXPRESS AUTHORITY. OFFENDERS ARE LIABLE TO THE PAYMENT OF DAMAGES ALL RIGHTS ARE RESERVED IN THE EVENT OF THE X11 X11 X11 X11 20 13 21 14 15 P3.3V 2 GND 2 GND RTS CTS DTR DSR DCD R86 10K 1 GND 1 4 11 10 R355 2 C60 V2 330R BZX84C3V3 3.3 V SCL SDA P3.3V 1 6 7 23 24 R78 DP DPM 10K P3.3V 2 50 V 33p 12 MHz C 1 32 31 30 29 R354 10K 2 B1 USB-SP-CTRL X1/CLKI 0 X2 1 P3 3 4 P3.3V 2 S 1 33p 50 V 3 2 C58 1 1 X11 R85 10K 2 2 27 26 GND D R84 max 30mA 10K 2 R77 10K P3.3V 1 P3.3V 1 R76 10K P3.3V 2 R75 1 P3.3V 1 P3.3V 2 B A GRANT OF A PATENT OR THE REGISTRATION OF A UTILITY MODEL OR DESIGN Copyright (C) Siemens AG, 2006 A Modification Date 1 Date Init. Appr. Name Norm 14.1.2013 Siemens AG Item No.: EB200P Test and debug Serial over USB 2 3 4 5 Sheet 7 40 Sheets A5E31374985A Circuit Diagram 6 7 8 F
1 2 3 4 5 6 7 8 Use case connectors 1 P3.3V R366 1K A 2 A PM FLASH XRESET 33:C7 ERTEC REF CLK GPIO[0-95] X22 38 GPIO[64] GPIO[81] X22 36 GPIO[65] X21 34 GPIO[34] X22 33 GPIO[82] X22 34 GPIO[66] GPIO[3] X21 31 GPIO[51] X21 32 GPIO[35] X22 31 GPIO[83] X22 32 GPIO[67] X20 29 GPIO[20] X20 30 GPIO[4] X21 29 GPIO[52] X21 30 GPIO[36] X22 29 GPIO[84] X22 30 GPIO[68] X20 27 GPIO[21] X20 28 GPIO[5] X21 27 GPIO[53] X21 28 GPIO[37] X22 27 GPIO[85] X22 28 GPIO[69] X20 25 GPIO[22] X20 26 GPIO[6] X21 25 GPIO[54] X21 26 GPIO[38] X22 25 GPIO[86] X22 26 GPIO[70] X20 23 GPIO[23] X20 24 GPIO[7] X21 23 GPIO[55] X21 24 GPIO[39] X22 23 GPIO[87] X22 24 GPIO[71] X20 21 GPIO[24] X20 22 GPIO[8] X21 21 GPIO[56] X21 22 GPIO[40] X22 21 GPIO[88] X22 22 GPIO[72] X20 19 GPIO[25] X20 20 GPIO[9] X21 19 GPIO[57] X21 20 GPIO[41] X22 19 GPIO[89] X22 20 GPIO[73] X20 17 GPIO[26] X20 18 GPIO[10] X21 17 GPIO[58] X21 18 GPIO[42] X22 17 GPIO[90] X22 18 GPIO[74] X20 15 GPIO[27] X20 16 GPIO[11] X21 15 GPIO[59] X21 16 GPIO[43] X22 15 GPIO[91] X22 16 GPIO[75] X20 13 GPIO[28] X20 14 GPIO[12] X21 13 GPIO[60] X21 14 GPIO[44] X22 13 GPIO[92] X22 14 GPIO[76] X20 11 GPIO[29] X20 12 GPIO[13] X21 11 GPIO[61] X21 12 GPIO[45] X22 11 GPIO[93] X22 12 GPIO[77] X20 9 GPIO[30] X20 10 GPIO[14] X21 9 GPIO[62] X21 10 GPIO[46] X22 9 GPIO[94] X22 10 GPIO[78] X20 7 GPIO[31] X20 8 GPIO[15] X21 7 GPIO[63] X21 8 GPIO[47] X22 7 GPIO[95] X22 8 GPIO[79] X20 5 PM FLASH XRESET P3.3V 3 X20 6 X21 5 ERTEC REF CLK P3.3V X21 6 X22 5 X22 6 X20 4 X21 3 X21 4 X22 3 X22 4 1 X20 2 P3.3V X21 1 X21 2 P3.3V X22 1 X22 2 P3.3V GND P5.0V GND C75 2u2 16 V GND P5.0V C77 100n 16 V GND GND 1n 50 V C79 10n 50 V GND 1 1 GND P5.0V 2 10n 50 V C80 GND P5.0V C81 1n 50 V X21 X21 X21 X21 X21 P5.0V P3.3V S1 S2 S3 S4 S5 C82 2u2 16 V C84 100n 16 V GND P5.0V GND 1 100n 16 V C78 P3.3V C83 2u2 16 V 2 2u2 16 V C76 2 C74 P3.3V 1 S1 S2 S3 S4 S5 1 X20 X20 X20 X20 X20 P3.3V 2 E COPYING OF THIS DOCUMENT AND GIVING IT TO OTHERS AND THE USE OR COMMUNICATION OF THE CONTENTS THEREOF ARE FORBIDDEN X20 2 X20 P5.0V GND GND P3.3V C86 10n 50 V GND P5.0V C85 100n 16 V P3.3V C88 1n 50 V GND P5.0V C87 10n 50 V GND GND GND P5.0V C89 1n 50 V P3.3V P3.3V S1 S2 S3 S4 S5 X22 X22 X22 X22 X22 C90 2u2 16 V C92 100n 16 V GND P5.0V GND C91 2u2 16 V GND 1 32 2 X20 1 GPIO[19] 2 31 1 X20 GND 100n 16 V 10n 50 V Rev. C96 1n 50 V GND P5.0V C95 10n 50 V GND P3.3V E GND P5.0V C97 1n 50 V GND GND Unmounted Components are displayed blue or with dashed lines 002 Ind. P3.3V C94 updateDate 13/02/05 updateTime 07:37:56 F D P5.0V GND P5.0V C93 C 1 GPIO[50] 2 33 2 X21 1 GPIO[2] 2 34 1 X20 2 GPIO[18] 1 33 1 X20 B 1 35 1 X22 2 GPIO[33] 1 36 2 X21 1 GPIO[49] 2 35 1 X21 2 GPIO[1] 1 36 2 X20 1 GPIO[17] 2 35 1 X20 2 X22 1 GPIO[32] 2 X21 2 X21 1 GPIO[0] 2 X20 Use case 2 37 GPIO[80] 38 2 GPIO[16] Use case 1 37 GPIO[48] 38 1 D WITHOUT EXPRESS AUTHORITY. OFFENDERS ARE LIABLE TO THE PAYMENT OF DAMAGES ALL RIGHTS ARE RESERVED IN THE EVENT OF THE C X20 37 2 Use case 0 2 GRANT OF A PATENT OR THE REGISTRATION OF A UTILITY MODEL OR DESIGN Copyright (C) Siemens AG, 2006 B 9:C8 2:A1;4:B1;5:C2; 6:B1;9:E1;10:A3; 16:A3;16:C3;25:A1; 26:A2;32:A5 Modification Date 1 Date Init. Appr. Name Norm 14.1.2013 Siemens AG Item No.: EB200P Interfaces Use case MICTORs 2 3 4 5 Sheet 8 40 Sheets A5E31374985A Circuit Diagram 6 7 8 F
1 2 3 4 5 6 7 8 ERTEC 200P A ERTEC P1.2V A 1 33:B7 1 2u2 16 V 100n 16 V GND 2:A1;4:B1;5:C2; 6:B1;8:B1;10:A3; 16:A3;16:C3;25:A1; 26:A2;32:A5 GND C724 10n 50 V GND P3.3V C725 1n 50 V 1 P3.3V 1 1 1 C723 D43 74LVC1G07 P3.3V 2 C722 4 2 0R 2 P3.3V 2 R92 GND 2 D43 2 max5mA 5 VCC GND 3 GND GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] GPIO[11] GPIO[12] GPIO[13] GPIO[14] GPIO[15] X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 V9 U7 U8 U9 U10 U11 U12 U13 R16 R17 T16 T17 T18 U17 U18 V17 V9 U7 U8 U9 U10 U11 U12 U13 R16 R17 T16 T17 T18 U17 U18 V17 1 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GPIO/INT GPIO 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 D0 1 Rev. 1 2 2 22R ERTEC REF CLK 8:A1 10R P3.3V X70 X70 X70 X70 1K GPIO[16] GPIO[17] GPIO[18] GPIO[19] GPIO[20] GPIO[21] GPIO[22] GPIO[23] GPIO[24] GPIO[25] GPIO[26] GPIO[27] GPIO[28] GPIO[29] GPIO[30] GPIO[31] R95 R101 R100 1K GND GND GND R104 1K 1K 1K GND GND GND D E GPIO[0-95] Unmounted Components are displayed blue or with dashed lines Modification Date 1 C R103 ERTEC200 002 Ind. GND R102 2 R96 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 GND 1 updateDate 13/02/05 updateTime 07:37:56 F 2 GND 1 TEST TMC1 TMC2 TACT CTRL STBY0 CTRL STBY1 CTRL STBY2 GND 2 XRESET 1 1 NC X70 X70 X70 X70 C107 1 GND M15 M15 J15 J15 F9 F9 XCLK1 XCLK2 BYP CLK REF CLK X70 X70 50 V 15p 2 GND W15 W15 V15 V14 V15 V14 Y14 W14 Y14 T11 W14 W16 T11 W16 P6 P6 R9 F12 R9 R14 F12 R12 R14 R12 T9 T10 T9 T14 T10 T15 T14 U14 T15 U15 U14 R18 U15 U16 R18 W19 U16 W18 W19 W17 W18 V20 W17 Y18 V20 Y17 Y18 V19 Y17 V18 V19 V18 AVDD AGND XTRST TCK RTCK TDI TMS TDO XSRST TAP SEL B2 25 MHz 1 GND X70 X70 X70 P4 P4 P3 P3 W7 W7 W8 W8 T8 T8 R7 R7 R10 R10 T7 T7 S 2 2 GND ERTEC200 15p 50 V 1 2 1K ERTEC XRST P3.3V X70 X70 X70 X70 X70 X70 X70 X70 X70 2 10K GND 3 2 1 1 1 1 4K7 R90 2 4K7 R88 1 1 33R C WITHOUT EXPRESS AUTHORITY. OFFENDERS ARE LIABLE TO THE PAYMENT OF DAMAGES ALL RIGHTS ARE RESERVED IN THE EVENT OF THE 2 R405 R404 GND B 1 C106 1 R403 1n 50 V 10K 5:A2 COPYING OF THIS DOCUMENT AND GIVING IT TO OTHERS AND THE USE OR COMMUNICATION OF THE CONTENTS THEREOF ARE FORBIDDEN GND C104 1 5:A2 100n 16 V 2 5:A2 5:A2 C100 R91 10K 2 2 R93 1K 2u2 16 V 2 R89 4K7 1 1 R402 10K 2 2 1 R401 10K ERTEC XTRST ERTEC TCK ERTEC RTCK ERTEC TDI ERTEC TMS ERTEC TDO ERTEC XSRST 5:B2 5:A2 E C98 P3.3V ERTEC PXHIF 2 R400 10K P3.3V 2 R399 P3.3V 1 P3.3V 1 P3.3V 1 P3.3V 2 R386 0R 5:A2 D 2 2 GRANT OF A PATENT OR THE REGISTRATION OF A UTILITY MODEL OR DESIGN Copyright (C) Siemens AG, 2006 B A Date Init. Appr. Name Norm 14.1.2013 Siemens AG Item No.: EB200P ERTEC 200P ERTEC 200P 2 3 4 5 Sheet 9 40 Sheets A5E31374985A Circuit Diagram 6 7 8 F
1 2 3 4 5 6 7 8 ERTEC 200P - XHIF A A B GPIO[0-95] GRANT OF A PATENT OR THE REGISTRATION OF A UTILITY MODEL OR DESIGN Copyright (C) Siemens AG, 2006 2:A1;4:B1;5:C2; 6:B1;8:B1;9:E1; 16:A3;16:C3;25:A1; 26:A2;32:A5 GPIO[64] GPIO[65] GPIO[66] GPIO[67] GPIO[68] GPIO[69] GPIO[70] GPIO[71] GPIO[72] GPIO[73] GPIO[74] GPIO[75] GPIO[76] GPIO[77] GPIO[78] GPIO[79] GPIO[80] GPIO[81] GPIO[82] GPIO[83] GPIO[84] GPIO[85] GPIO[86] GPIO[87] GPIO[88] GPIO[89] GPIO[90] GPIO[91] GPIO[92] GPIO[93] GPIO[94] GPIO[95] D WITHOUT EXPRESS AUTHORITY. OFFENDERS ARE LIABLE TO THE PAYMENT OF DAMAGES ALL RIGHTS ARE RESERVED IN THE EVENT OF THE C X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 GPIO[55] GPIO[54] G17 L17 P17 G16 H17 L16 M16 K16 K17 M17 N17 J16 H16 N16 J17 P16 E8 F7 E9 D7 D8 E12 D11 D9 D10 E7 D13 E10 D14 D12 E11 E13 G15 G15 L15 L15 XHIF A XHIF D A16 C15 B16 E15 D15 C17 E16 B14 E17 B19 C18 C19 B15 C13 D17 C16 A15 B18 D19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A16 C15 B16 E15 D15 C17 E16 B14 E17 B19 C18 C19 B15 C13 D17 C16 A15 B18 D19 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 GPIO[32] GPIO[33] GPIO[34] GPIO[35] GPIO[36] GPIO[37] GPIO[38] GPIO[39] GPIO[40] GPIO[41] GPIO[42] GPIO[43] GPIO[44] GPIO[45] GPIO[46] GPIO[47] GPIO[48] GPIO[49] GPIO[50] E18 D18 D16 F16 F17 E14 F14 B17 A17 X70 X70 X70 X70 X70 X70 X70 X70 X70 GPIO[52] GPIO[53] GPIO[51] GPIO[60] GPIO[61] GPIO[62] GPIO[63] GPIO[58] GPIO[59] D20 C20 D20 C20 X70 X70 GPIO[56] GPIO[57] E18 D18 D16 F16 F17 E14 F14 B17 A17 XHIF SEG 0 XHIF SEG 1 XHIF SEG 2 XHIF BE0 XHIF BE1 XHIF BE2 XHIF BE3 XHIF XCS R A20 XHIF XCS M XHIF XWR XHIF XRD B C D XHIF XIRQ XHIF XRDY ERTEC200 R385 COPYING OF THIS DOCUMENT AND GIVING IT TO OTHERS AND THE USE OR COMMUNICATION OF THE CONTENTS THEREOF ARE FORBIDDEN E ERTEC200 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 D0 1 X70 X70 G17 L17 P17 G16 H17 L16 M16 K16 K17 M17 N17 J16 H16 N16 J17 P16 E8 F7 E9 D7 D8 E12 D11 D9 D10 E7 D13 E10 D14 D12 E11 E13 2 4K7 E GND updateDate 13/02/05 updateTime 07:37:56 F Unmounted Components are displayed blue or with dashed lines 002 Ind. Rev. Modification Date 1 Date Init. Appr. Name Norm 14.1.2013 Siemens AG Item No.: EB200P ERTEC 200P ERTEC 200P 2 3 4 5 Sheet 10 40 Sheets A5E31374985A Circuit Diagram 6 7 8 F
1 2 3 4 5 6 7 8 ERTEC 200P - EMC A XBE DQM J3 J4 K3 K4 X70 X70 X70 X70 EMC XCS SDRAM EMC XRAS SDRAM EMC XCAS SDRAM EMC XWE SDRAM U6 T6 X70 X70 ERTEC EMC 1 1 1 R447 R446 R448 10K 10K 2 2 10K 2 10K ERTEC EMC C R439 1 2 3 4 ERTEC EMC R440 10K 8 7 6 5 10K 18:E1;22:E1 18:E1 D 19:B4 19:B4 18:E1;22:E1 18:E1;22:E1 20:D1;21:E2 20:D1;21:E2 20:D1;21:F2 20:D1;21:F2 1 1 ERTEC EMC D44 To boot from burst mode flash in legacy mode keep it as is, to boot from legacy mode flash in legacy mode move R416 to R415 position EMC DTXR EMC XOE DRIVER 2 18:A4;19:C4;32:A5 18:A4;19:C4;32:A5 R415 6 G1 3 1 1 1 Rev. 1 U6 T6 EMC XWR EMC XRD ERTEC200 0R Modification Date 1 Date Init. Appr. Name Norm 14.1.2013 Siemens AG R416 MUX 0R 4 ERTEC EMC ERTEC EMC 74LVC1G157 5 VCC GND 2 D44 GND C733 2u2 16 V ERTEC EMC C734 100n 16 V GND ERTEC EMC C735 10n 50 V GND GND ERTEC EMC C736 1n 50 V GND Item No.: EB200P ERTEC 200P ERTEC 200P 3 4 5 Sheet 11 40 Sheets A5E31374985A Circuit Diagram 2 E 2 Unmounted Components are displayed blue or with dashed lines 002 Ind. DTXR XOE DRIVER X70 X70 D0 updateDate 13/02/05 updateTime 07:37:56 F J3 J4 K3 K4 N1 M1 R445 10K 2 XRDY PER XCS SDRAM XRAS SDRAM XCAS SDRAM XWE SDRAM EMC XCS PER0 EMC XCS PER1 EMC XCS PER2 EMC XCS PER3 R444 ERTEC EMC 1 2 3 4 G6 N1 M1 X70 X70 X70 X70 ERTEC EMC ERTEC EMC 1 G6 XWR XRD XCS PER T4 R5 D6 E6 B 2 X70 0 1 2 3 T4 R5 D6 E6 D X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 1 EMC XRDY PER 19:C4 T5 T3 E5 D3 0 1 2 3 A EMC AB[0] EMC AB[1] EMC AB[2] EMC AB[3] EMC AB[4] EMC AB[5] EMC AB[6] EMC AB[7] EMC AB[8] EMC AB[9] EMC AB[10] EMC AB[11] EMC AB[12] EMC AB[13] EMC AB[14] EMC AB[15] EMC AB[16] EMC AB[17] EMC AB[18] EMC AB[19] EMC AB[20] EMC AB[21] EMC AB[22] EMC AB[23] H4 G4 F4 F5 E4 E3 G1 G2 F3 H1 H2 J2 J1 K2 L2 M4 M2 N2 N4 P1 P2 P5 R3 R4 2 18:E1;20:D1;21:E2 T5 T3 E5 D3 H4 G4 F4 F5 E4 E3 G1 G2 F3 H1 H2 J2 J1 K2 L2 M4 M2 N2 N4 P1 P2 P5 R3 R4 1 E COPYING OF THIS DOCUMENT AND GIVING IT TO OTHERS AND THE USE OR COMMUNICATION OF THE CONTENTS THEREOF ARE FORBIDDEN 18:E1;20:D1;21:E2 X70 X70 X70 X70 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 2 18:E1;20:D1;21:E2 EMC XBE0 DQM0 EMC XBE1 DQM1 EMC XBE2 DQM2 EMC XBE3 DQM3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 18:E1;20:D1;21:E2 ERTEC200 Y4 V4 V5 W4 V6 U4 U3 U5 U2 V2 U1 W2 V1 W3 V3 Y3 D4 C4 D5 B5 C5 A5 B4 A4 A3 B3 B2 C2 C1 D1 C3 D2 2 8 7 6 5 10K X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 X70 Y4 V4 V5 W4 V6 U4 U3 U5 U2 V2 U1 W2 V1 W3 V3 Y3 D4 C4 D5 B5 C5 A5 B4 A4 A3 B3 B2 C2 C1 D1 C3 D2 1 R441 EMC DB[0] EMC DB[1] EMC DB[2] EMC DB[3] EMC DB[4] EMC DB[5] EMC DB[6] EMC DB[7] EMC DB[8] EMC DB[9] EMC DB[10] EMC DB[11] EMC DB[12] EMC DB[13] EMC DB[14] EMC DB[15] EMC DB[16] EMC DB[17] EMC DB[18] EMC DB[19] EMC DB[20] EMC DB[21] EMC DB[22] EMC DB[23] EMC DB[24] EMC DB[25] EMC DB[26] EMC DB[27] EMC DB[28] EMC DB[29] EMC DB[30] EMC DB[31] 18:A1;20:A1;21:A2; 22:A1;32:B5 2 1 2 3 4 ERTEC EMC EMC AB[0-23] 8 7 6 5 EMC DB[0-31] WITHOUT EXPRESS AUTHORITY. OFFENDERS ARE LIABLE TO THE PAYMENT OF DAMAGES ALL RIGHTS ARE RESERVED IN THE EVENT OF THE C D EMC DB[0-31] EMC AB[0-23] 18:A4;20:A1;21:A2; 22:A1 GRANT OF A PATENT OR THE REGISTRATION OF A UTILITY MODEL OR DESIGN Copyright (C) Siemens AG, 2006 B A 6 7 8 F
2 3 P1.5V A SEP GND 16:E1 GND P1 TDXP P1 TDXN P1 RDXP P1 RDXN P1 RDXP P1 RDXN GND GND 1n 50 V 1 C123 15:C1 2 10n 50 V 1 C119 2 100n 16 V 2 1 C115 2 2u2 16 V 1 16:E1 C111 GND GND GND GND 15:C1 1n 50 V P1 RXP P1 RXN P1 FXEN P1 RXP P1 RXN 1 0R 2 R122 1 C121 P1 TXP P1 TXN 16:E1 2 10n 50 V 1 C117 2 1 2 1 100n 16 V 2 2u2 16 V C113 P1 TXP P1 TXN 15:C1 15:C1 C109 GND GND 15:C1;17:F3 15:E1;17:E3 15:C1;17:E3 P1 ACT P2 ACT P1 LINK P2 LINK P1 ACT P2 ACT P1 LINK P2 LINK GND GND 1n 50 V GND EMC XRDY BF 22:E1 P1RDXP P1RDXN P2RDXP P2RDXN J19 J20 P1TXP P1TXN P2TXP P2TXN P1RXP P1RXN P1FXEN T13 T13 T12 T12 U20 U20 U19 U19 X70 X70 X70 X70 G5 L5 K5 L4 X70 X70 P2RXP P2RXN P2FXEN A PHY1 A PHY2 L PHY1 L PHY2 G5 L5 K5 L4 TESTOUT5 TESTOUT6 TESTOUT7 CLK O SDRAM0 CLK O SDRAM1 CLK I SDRAM CLK O SDRAM2 CLK I BF CLK O BF0 XAV BF CLK O BF1 XRDY BF CLK O BF2 D0 P2 SDXP P2 SDXN X70 X70 P2 TDXP P2 TDXN P2 TDXP P2 TDXN X70 X70 P2 RDXP P2 RDXN P2 RDXP P2 RDXN X70 X70 P2 TXP P2 TXN P2 TXP P2 TXN X70 X70 X70 X70 X70 X70 X70 X70 X70 1 2 1 1 1 2 2 GND 2 GND 16:B1 16:B1 16:C1 P2 RXP P2 RXN P2 FXEN 15:E1 D ERTEC EMC ERTEC EMC 15:E1 15:E1 R125 16:B1 R123 R127 10K 0R EMC CLK O SDRAM1 EMC CLK O SDRAM2 20:D1;21:E2 C140 15p 50 V 20:D1;21:E2 X70 X70 X70 C 10K EMC CLK O BF1 EMC CLK O BF2 C143 15p 50 V 22:E1 R126 22:E1 R128 49R9 1 E 49R9 GND GND R436 10K EMC XAV BF 22:E1 Unmounted Components are displayed blue or wi
14.1.2013 siemens ag a5e31374985a 002 40 2 test and debug leds eb200p yellow lya67k h2 a k red lsa67k h1 a k 750r r19 1 2 750r r20 1 2 750r r21 1 2 750r r22 1 2 green lgl29k h10 a k green lgl29k h14 a k green lgl29k h15 a k red lsl29k h11 a k yellow lyl29k h12 a k yellow lyl29k h13 a k yellow lyl29k h17 yellow a k lyl29k h16 a k 750r r23 1 2 .
WIRING DIAGRAM DIRECTORY WARNING: Wiring direct to battery not recommended. Install actuator after ignition switch, or master power switch. Diagram 1 Diagram 2 Diagram 3 Diagram 4 Diagram 5 Diagram 6 Diagram 7 Diagram 8 Diagram 9 Diagram 10 Diagram 11 Diagram 12 Diagram 13 Diagram 14 Diagram 15 On/Off, 12VDC, 3-wire/3-pin, SPST On/Off, 12VDC, 3 .
Snatch Block, Shackle 6:24 Snatch Block, Hook 6:24 Snatch Block, others (page 6:29) 6:25 Tilt Wall Block 6:26 Oilfield Blocks 6:27 - 6:30 Tubing Block 6:27 Manhandler Block 6:28 Derrick Block 6:28 Laydown Block 6:29 Tong Line Block 6:30 Hay Fork Pulley 6:30 Guyline Block 6:30 J-Latches 6:31 T
Structured analysis Object-oriented analysis System boundary Context diagram Use case diagram Functionality Data flow diagram Activity diagram Interaction diagrams Data Entity-relationship diagram Class diagram Object diagram Control State diagram State diagram Structured methods System as a set of nested processes accessing system data.
Note: The diagram shown above is for reference only. Use the instructions beginning on the next page to draw your Package diagram. Creating a Package Diagram from the Use Case Diagram The package diagram is a type of class diagram and can be created from a use case diagram. 1. Make sure the Use Case diagram c
Figure 2: A sequence diagram that has incoming and outgoing messages Notice that in Figure 2 the diagram's label begins with the letters "sd," for Sequence Diagram. When using a frame element to enclose a diagram, the diagram's label needs to follow the format of: Diagram Type Diagram Name UML basics: The sequence diagram Page 3 of 24 http .
Spring 2018 :: CSE 502 Simple Interleaved Main Memory Divide memory into n banks, “interleave” addresses across them so that cache-block A is –in bank “A mod n” –at block “A div n” Can access one bank while another one is busy Bank 0 Bank 1 Bank 2 Bank n Block in bank Bank Block 0 Block n Block 2n Block 1 Block n 1 Block .
new, 3000 rpm, 50 HZ, 13 MW Siemens SST 300 steam turbine with 5000 hours. Plant was commissioned and put into operation in 2012. Brief Description (refer to full description below) Siemens T3000 Main DCS Siemens 65 MVA & 18 MVA Transformers Sub Station Siemens HV System Siem
3.1 Siemens Private Communication Systems (PN) 15 3.2 Siemens Automation (AUT) 18 3.3 Siemens Nixdorf Informationssysteme (SNI) 18 3.4 Siemens Stromberg-Carlson (SSC) 19 3.5 Siemens Industrial Automation (SIA) 20 3.6 Electromedical Group (SME) of Siemens Medical Systems 2
