Design Example: Level-to-Pulse

Design Example: Level-to-Pulse A level-to-pulse converter produces a singlecycle pulse each time its input goes high. It’s a synchronous rising-edge detector. Sample uses:– Buttons and switches pressed by humans forarbitrary periods of time– Single-cycle enable signals for countersLevel toLPPulseConverterWhenever input L goesfrom low to high.6.111 Fall 2007CLK.output P produces asingle pulse, one clockperiod wide.Lecture 7, Slide 1

Step 1: State Transition Diagram Block diagram of desired system:unsynchronizeduser inputSynchronizerEdge DetectorD QLD QLevel toPulseFSMPCLK State transition diagram is a useful FSM representation anddesign aid:“if L 1 at the clock edge,then jump to state 01.”L 000“if L 0 at the clock edge,then stay in state 00.”L 1High input,Waiting for fallEdge Detected!P 1L 0Binary values of states1101Low input,Waiting for riseP 06.111 Fall 2007L 1L 1P 0L 0This is the output that results fromthis state. (Moore or Mealy?)Lecture 7, Slide 2

Step 2: Logic DerivationCurrenInt StateTransition diagram is readily converted to astate transition table (just a truth table)L 1L 1L 000P 0Edge Detected!P 1L 0S0L000011001111010101L 11101Low input,Waiting for riseS1High input,Waiting for fallP 0L 0NextStateOutS1 S0 P000101010101001100 Combinational logic may be derived using Karnaugh maps S1S0 for S1 :00 01 11 10L0 0 0 0 X1 0 1 1 X :S1S0 for S000 01 11 10L0 0 0 0 X1 1 1 1 X6.111 Fall 2007LS Comb.LogicS1 LS0S0 LnCLKD Flip- QComb.LogicFlopsnSP S1S0PS0S1for P:0 10 0 X1 1 0Lecture 7, Slide 3

Moore Level-to-Pulse Converterinputsx0.xnnextstateS Comb.LogicDnFlip- QFlopsComb.LogicCLKS1 LS0S0 L outputsyk fk(S)npresent state SP S1S0Moore FSM circuit implementation of level-to-pulse converter:LS0 DCLKS1 6.111 Fall 2007QS0PQDQQS1Lecture 7, Slide 4

Design of a Mealy Level-to-Pulsedirect combinational path!S Comb.LogicnComb.LogicD Flip- QFlopsCLKnS Since outputs are determined by state and inputs, Mealy FSMs mayneed fewer states than Moore FSM implementations1. When L 1 and S 0, this output isasserted immediately and until thestate transition occurs (or L changes).LPL 1 P 1L 0 P 012Clock01Input is lowInput is highL 0 P 0L 1 P 0StateOutput transitions immediately.State transitions at the clock edge.2. While in state S 1 and as long as Lremains at 1, this output is asserted.6.111 Fall 2007Lecture 7, Slide 5

Mealy Level-to-Pulse ConverterL 1 P 101Input is lowInput is highL 0 P 0L 0 P 0L 1 P 0Pres.StateInS0011L0101NextOutStateS 0101P0100Mealy FSM circuit implementation of level-to-pulse converter:PLS CLKDQSQS FSM’s state simply remembers the previous value of L Circuit benefits from the Mealy FSM’s implicit singlecycle assertion of outputs during state transitions6.111 Fall 2007Lecture 7, Slide 6

Moore/Mealy Trade-Offs How are they different?– Moore: outputs f( state ) only– Mealy outputs f( state and input )– Mealy outputs generally occur one cycle earlier than a Moore:Moore: delayed assertion of PMealy: immediate assertion of PLLPPClockClockState[0]State Compared to a Moore FSM, a Mealy FSM might.– Be more difficult to conceptualize and design– Have fewer states6.111 Fall 2007Lecture 7, Slide 7

Light Switch Revisited01BUTTOND QLIGHTD QQCLKLevel-to-PulseFSM6.111 Fall 2007Light SwitchFSMLecture 7, Slide 8

FSM ExampleGOAL:Build an electronic combination lock with a resetbutton, two number buttons (0 and 1), and anunlock output. The combination should be 01011.RESET“0”“1”UNLOCKSTEPS:1.Design lock FSM (block diagram, state transitions)2.Write Verilog module(s) for FSM6.111 Fall 2007Lecture 7, Slide 9

Step 1A: Block DiagramlockClockgeneratorfsmunlockButtonEnterreset buttonresetButton0b0 in buttonb0Button16.111 Fall 2007fsm clockb1 instatebuttonUnlockLEDLEDDISPLAYb1Lecture 7, Slide 10

Step 1B: State transition diagramRESET1010RESETUnlock 0“0”Unlock 01“01”Unlock 00100“01011”Unlock 11“0101”Unlock 01“010”Unlock 006 states 3 bits6.111 Fall 2007Lecture 7, Slide 11

Step 2: Write Verilogmodule lock(clk,reset in,b0 in,b1 in,out);input clk,reset,b0 in,b1 in;output out;// synchronize push buttons, convert to pulses// implement state transition diagramreg [2:0] state,next state;always @ (*) begin// combinational logic!next state ?;endalways @ (posedge clk) state next state;// generate outputassign out ?;// debugging?endmodule6.111 Fall 2007Lecture 7, Slide 12

Step 2A: Synchronize buttons// button -- push button synchronizer and level-to-pulse converter// OUT goes high for one cycle of CLK whenever IN makes a// low-to-high transition.module button(clk,in,out);input clk;input in;output out;outinD Qr1D Qr2D Qr3clkreg r1,r2,r3;always @ (posedge clk)synchronizerstatebeginr1 in;// first reg in synchronizerr2 r1;// second reg in synchronizer, output is in sync!r3 r2;// remembers previous state of buttonend// rising edge old value is 0, new value is 1assign out r3 & r2;endmodule6.111 Fall 2007Lecture 7, Slide 13

Step 2B: state transition erparameterS RESET 0; // state assignmentsRESETS 0 1;1S 01 2;RESETS 010 3;Unlock 0S 0101 4;S 01011 5;1“01011 ”Unlock 1100“0”Unlock 01“01”Unlock 00001“0101 ”1“010”Unlock 0Unlock 0reg [2:0] state, next state;always @ (*) begin0// implement state transition diagramif (reset) next state S RESET;else case (state)S RESET: next state b0 ? S 0: b1 ? S RESET : state;S 0:next state b0 ? S 0: b1 ? S 01: state;S 01:next state b0 ? S 010 : b1 ? S RESET : state;S 010:next state b0 ? S 0: b1 ? S 0101 : state;S 0101: next state b0 ? S 010 : b1 ? S 01011 : state;S 01011: next state b0 ? S 0: b1 ? S RESET : state;default: next state S RESET; // handle unused statesendcaseendalways @ (posedge clk) state next state;6.111 Fall 2007Lecture 7, Slide 14

Step 2C: generate output// it’s a Moore machine!Output only depends on current stateassign out (state S 01011);Step 2D: debugging?// hmmm.What would be useful to know?Current state?assign hex display {1'b0,state[2:0]};6.111 Fall 2007Lecture 7, Slide 15

Step 2: final Verilog implementationmodule lock(clk,reset in,b0 in,b1 in,out, hex display);input clk,reset,b0 in,b1 in;output out; output[3:0] hex display;wire reset, b0, b1; // synchronize push buttons, convert to pulsesbutton b reset(clk,reset in,reset);button b 0(clk,b0 in,b0);button b 1(clk,b1 in,b1);parameter S RESET 0; parameter S 0 1; // state assignmentsparameter S 01 2; parameter S 010 3;parameter S 0101 4; parameter S 01011 5;reg [2:0] state,next state;always @ (*) begin// implement state transition diagramif (reset) next state S RESET;else case (state)S RESET: next state b0 ? S 0: b1 ? S RESET : state;S 0:next state b0 ? S 0: b1 ? S 01: state;S 01:next state b0 ? S 010 : b1 ? S RESET : state;S 010:next state b0 ? S 0: b1 ? S 0101 : state;S 0101: next state b0 ? S 010 : b1 ? S 01011 : state;S 01011: next state b0 ? S 0: b1 ? S RESET : state;default: next state S RESET;// handle unused statesendcaseendalways @ (posedge clk) state next state;assign out (state S 01011);// assign output: Moore machineassign hex display {1'b0,state};// debuggingendmodule6.111 Fall 2007Lecture 7, Slide 16

Where should CLK come from? Option 1: external crystal– Stable, known frequency, typically 50% duty cycle Option 2: internal signals– Option 2A: output of combinational logic No! If inputs to logic change, output may make severaltransitions before settling to final value several risingedges, not just one! Hard to design away output glitches – Option 2B: output of a register Okay, but timing of CLK2 won’t line up with CLK1D Q6.111 Fall 2007CLK1CLK2CLK1Lecture 7, Slide 17

Summary Modern digital system design:– Hardware description language Toolchain:– Design EntrySimulateSynthesis New Labkit:– Almost all functionalityis programmed in!– How to generate video?Synchronize systems?Create/Digitize Audio?Serial & communications?6.111 Fall 2007ImplementationDesign )– Black-box peripheralsFPGA / ASICrtlImplementation(map, place, route)*.bitProgramming(parallel cable)Lecture 7, Slide 18

Design of a Mealy Level-to-Pulse Since outputs are determined by state and inputs, Mealy FSMs may need fewer states than Moore FSM implementations S Comb. Logic CLK Flip-Flops Comb. n D Q Logic