An Overview Of Advanced Interconnect Solutions
An Overview of AdvancedInterconnect SolutionsProf. Krishna SaraswatDepartment of Electrical EngineeringStanford UniversityStanford, CA 94305araswattanford University1EE311/InterconnectOutline CurrentCu/low-k Paradigm: Challenges and Limitations Alternatives Circuit Architectural/Combination Solutions Technological Solutions– Air-gaps– 3-D technologies– Optical interconnects– Wireless Summaryaraswattanford University2EE311/Interconnect1
Interconnect Performance RequirementsTechnology Generation1.0 µm0.1 µmMOSFET Intrinsic Switching DelayInterconnect Response Time(Lint 1 mm)Clock FrequencySupply Current(Vdd 5.0, 1.0 V)Maximum Number of Wiring LevelsMaximum Total Wire Length per ChipChip Pad Count 10 ps 1 ps 1 ps 100ps 30 MHz 2.5 A 2-3.5 GHz 150 A3 100 m 2007-8 5000 m 2000, 4000araswattanford University3EE311/InterconnectCarbon Nanotubes: IntroductionBandstructureERolled up graphene sheetconductionEFvalencek xaraswatzig-zag tubechiral tubeθ 0º0º θ 30ºtanford University4k !yarmchair tubeθ 30ºEE311/Interconnect2
The one-dimensional subbandsMetallicSemiconductingEEEg 0.8/d (nm) eV)k k Chirality and diameter of the carbon nanotubes determine their properties Ideal carbon nanotubes don’t have scattering Ballistic transport Resistance of defect free nanotube-bundles, theoretically: h/(4e2n) Ballistic flow of electrons in metallic carbon nanotubes makes them potentialcandidates for nanoscale interconnectionsaraswattanford University5EE311/InterconnectKinetic Inductance for a 1-D System ofElectrons1000h2k 2! 2m1000 ! εFh2k 22m"!"k -40-100I 0 0k2!L40 -40-100 NI 20 .e.vFLk 40 In steady state equal number of electrons are moving in ve and -ve k direction Nanotube is a 1D system with limited density of states With potential applied the carriers have to move to higher energy statesresulting in increase in kinetic energy. Extra stored energy results in kinetic inductanceKinetic inductance of a carbon nanotube is 16nH/µm, more than 4 orders ofmagnitude larger than its magnetic counterpart in a normal metal. araswattanford University6EE311/Interconnect3
Alternatives for On-Chip Wires: Carbon NanotubesNaeemi, Meindl(IEDM 2004) Due to very large kinetic inductance, propagation speed in a carbon nanotubeabove a ground plane is more than 100 times slower than light in free space. Bundles of carbon nanotubes should be used for interconnect applications toavoid very slow signal propagation. Capacitance is similar to Cu-low-k. Will they have any power advantage overCu/low-k?araswattanford University7EE311/InterconnectCarbon Nanotubes with Finite ElectronMean Free Path Even initially perfect nanotubes become disordered once they arephysisorbed on a surface. Due to interference between incident and scattered electronwaves, nanotube resistance increases exponentially with length:R R0eL2 L0R0: Resistance of defect free nanotube-bundles, theoretically: h/(4e2n)L0: Electron mean free pathL: LengthNaeemi, Meindl (IEDM 2004)araswattanford University8EE311/Interconnect4
Nanotube-Bundles versus Cu Interconnects!2r L "Lcrit # 2 L0 0.9 1.15ln( int 0 ) %R0 '&22nmNode, year2016Naeemi, Meindl (IEDM 2004)As a rule of thumb, nanotube-bundles should never be used for lengthslarger than 10 times electron mean free path.araswatKey Challenge: Low thermal budget controlled growthtanford University9EE311/InterconnectOn-chip Network RoutersTileEast OutputTile OutputWest InputNorth OutputTile logic &Local WiringW. J. Dally et.al., DAC, 2001South Output(West input shown as an example)Partition of chip into tiles & network logic Modular machine– Lots of potential compute units, w/ memory– On-chip network routersaraswattanford University10EE311/Interconnect5
Alternate Solutions in Copper DomainNear Speed of light on-chip electrical interconnects(R. T. Chang et. al. 2002 Symposium on VLSI circuits)1 GHz pulse7.5 GHz carrier High frequencies in a wire (LC domain) travelclose to speed of light Modulate electrical signal to higher carrierfrequencies (baseband to RF) But loss is high at higher frequencies (2 losses:due to conductor resistance and dielectric loss) Requires good low-loss transmission lines Near speed of light delay (10 times faster repeaters) Power comparable to repeater (at least at this node) Possible Issues– Requires larger area (well designed wires)– Some overhead due to fancy modulator/detector– scalability: higher freq higher carrier freq. larger lossaraswattanford University11EE311/InterconnectInterconnect Hierarchy: Bird’s Eye ViewInbox: traditionally CopperOn-chipOut of Box: Optics strong-holdOverBackplaneDigital Systems: Short interconnectsNetworkY. Li et. al, Proceedings of the IEEE,vol. 88, no. 6, June 2000.araswattanford University12EE311/Interconnect6
What will be the energy cost, per bit processed?1. Logicenergy cost 40kT per bit processed2. Storageenergy cost 40kT per bit processed3. Communicationscurrently 100,000kT per bit processed ( 1fJ)Will this change in the future with scaling?There are many ways to do logic and memory.But there are not many ways to communicate:1. Electrons on a metallic interconnect2. Optical interconnectSource: Eli Yablonovitch, SRC Workshop, Asheville, 2005araswattanford University13EE311/InterconnectImpedance Matching CrisisWhat is the impedance of a wire?Cwire femto-FaradsZ wire 1 j" C wireThe natural capacitance of a nano-scale device is much smaller:Cnano 10-18 Farads!Z nano 1 j" C nano The natural voltage range for wired communication is rather low:The wire wants many electrons at few mVolt eachPhoto-Diodehν 1eV! The natural voltage range for the nano-device is the voltagerequired for switching the electron out of the potential well: 1Volt The nano-device wants one electron at 1 Volt An impedance matching device is needed at the Nano-scale.hνOptoelectronic devices may provide the best solutionSources: (1) David Miller, Optics Letters, 1989, (2) Eli Yablonovitch SRC Workshop, Asheville, 2005araswat14tanford UniversityEE311/Interconnect7
Can Optical Interconnects help?On-ChipOpticalInterconnects40Tb/sOptical I/O1024x OC-768100Tb/sOn-ChipBisection BWPMM64 Tiles64b Processor 4MB DRAMChip-to-chip Optical ng Signal wires Reduce delay Increase bandwidthincoming shortlaser pulse Clock distributionfiber Reduce jitter and skew I/O with very high bandwidth Reduce poweraraswattanford University15EE311/InterconnectOptical Vs. Electrical WiresLaser SourceReceiver SystemOptical InterconnectTransmitter SystemModulator OpticalSignal OutWaveguideOpticalsignal InFront-endand gain stagesElectricalsignal OutElectricalSignal InElectrical Driverlogic gatePhoto-detectorOptical Communication Systemtopt ttrans twg trecCMOS levelvoltage swingElectricalReceiverlogic gateElectrical componentsOptical componentsElectrical Interconnect with repeatersRepeaterR/nDriverReceiverC/nElectrical Communication Systemaraswattanford University16EE311/Interconnect8
Optical System DelayRPD: Receiver Power Dissipation; IOP:Incident Optical Power at the receiverCdet: Detector capacitance of the photodetector(1): RPD 1.8mW, IOP 75µW, Cdet 250fF(2): RPD 1.2mW, IOP 200µW, Cdet 250fF(3): RPD 1.7mW, IOP 240µW, Cdet 250fF(4): RPD 5.3mW, IOP 240 µW, Cdet 250fF Transmitter delay using bufferchain50nm NodeiondrCtio, 2)n (1(3)onditino(4)er C ditioneivnRec er CoeivReceiveRecTotal Optical SystemDelay ttrans twaveguide trec Waveguide delay: assumedsimplistic: 11.5 ps/mm Receiver Delay: differentconditionsidet wavegu Waveguide delay dominatesafter 15mmttranstrec(4)trec(3)trec(1, 2)araswattanford University17EE311/InterconnectGlobal Signaling Delay: Optical Vs. Electrical WiresopperρIdealCElectrical(Cu)Delay W/ORepeatersElectrical(Cu) Delay WithOptimized Repeaters50nm NodelCcactiopperρ Optical Interconnects arefaster than repeated wiresbeyond a length well withinchip sizeIOP: Incident Optical Power at the receiverPractical Cu ρ: ALD Barrier, Barrier Thickness 10nm,temperature 100 0C, Surface Scattering parameter (P) 0.5IdealρerppCoρPractical C However for Signaling bothdelay and power are importantaPrrpeopP 75µW8mW, IORPD 1. 1.8 mW is approximately powerdissipated by a repeated chipedge long wire0µWW, IOP 24RPD 5.3mTotal OpticalSystem Delay, Cdet 250fFCritical lengthabove which optical System isfaster than even the electrical (Cu) repeated wiresaraswattanford University18EE311/Interconnect9
Optical Receiver Power DissipationCfRfAdditional gain stagesfor CMOs level outputPhoto-detectorVoutCdetConstraints Bandwidth SNR Supply swingat outputFront-end width &feedback resistance# of gain stagesReceiver Power Dissipation (mW)A simple receiver analysis for studying scalingOptical power Short channel effects for transistorsincorporated Transistor specs from ITRS Receiver power dissipation (Static)Technology Node 100nmBit Rate 2 Gbits/secCdet 1pFCdet 0.75pFCdet 0.5pFCdet 0.25pFInput Optical Power (IOP) to the Receiver (mW)Lower detector capacitance and higher IOP for low receiver power dissipationKapur and Saraswat, IEEE IITC, June 2002araswattanford University19EE311/InterconnectDelay of a communication Link (ps)On Chip Optical Vs. Electrical Wires:Delay & Power Scaling Optical:ElectricalC det 250fF,IOP 240 mW Electrical: SA 0.2 Length (both electrical &optical) chip edge longKapur and Saraswat,IEEE IITC, June 200250nm node70nm100nmOptical Scaling: delay advantage increases for optics, power advantage diminishes Good for long global wires whose number is not large Even power advantage exists if switching activity (SA) is higher Power can be reduced with better detectorsaraswattanford University20EE311/Interconnect10
Off-Chip Interconnect RequirementsRequirements High Bandwidth or bit rate Low latency: some applications Acceptable data fidelity Low powerDifferent beast than on-chip interconnects Larger widths ( 100-200µm) and longer distances (1cm-1m) Better defined return paths (controlled L, R and C) Wires are mostly “low loss” LC No silicon no repeaters Equalizationaraswattanford University21EE311/InterconnectOff-Chip Electrical Vs. Optical Links Share many components withelectrical linksCoupling LossPhotodiodeMQWVbias,VswingCR, IL– Transmitter to drive the laser ormodulator– A CDR to recover timingOptical Transmission l# of stage Also have some new components– Laser/modulator, photo-diode– Need driver for the modulator/laser,TIA for photo-diode– Optical channel Connectors, optical wire (board,fiber, free space?)Ctransmitter PADBuffer chainCdetTIR# of stageAmplifierElectrical linksLength,attenuationPCB traceRT 2ZoRT 2ZoifirPCB traceReceiver -PKGM0.5pFif1/ 5RT !52ode0.7nHChip -l0.3pFVia0.7nH0.5pFPAReceiver0.3pFRT !52ir1/ 5DElectrical Linkaraswattanford UniversityCho, Kapur and Saraswat, IITC 2004, JLT 200422EE311/Interconnect11
Comparison Between Electrical and OpticalInterconnects for Off-Chip CommunicationsOptical Interconnect5Gb/sElectrical [Power Dissipation @Cdet 10fF] Beyond certain length optical I/O is more power efficient Critical length decreases at higher bit rate Beyond 32nm Technology node critical length 10cmCho, Kapur and Saraswat, IEEE IITC, June 2005araswattanford University23EE311/InterconnectPower Comparison:Technology Scaling Optical interconnects will becomemore and more favorable in thefuture by showing a rapidreduction in critical length withtechnology scalingC det 50fF25fF Importance of lower detectorcapacitance in facilitating theinsertion of optical interconnects10fF5fFCho, Kapur and Saraswat, IEEE IITC, June 2005araswattanford University24EE311/Interconnect12
Technology for Optical Interconnects onSilicon : Monolithic Integration of LasersGaAs/AlGaAs QW laser on Ge/GeSi/SiArrays of surface emitting lasersP -m etaAlGaA ls cladInGaAs/GaAs activeAlGaAs cladGe/SiGe/SisubstrateFitzgerald, MIT(Haney et al.) InGaAs/AlGaAs QW laser on Ge/SiGe/Si operates cw at λ 858nm Critical issues are power consumption, stability and life timearaswattanford University25EE311/InterconnectTechnology for Optical Interconnects onSilicon:: Optical Transmission MediaWaveguidesArrayed Waveguide GratingDirectional Coupler(Kimmerlingr, MIT)(Jalali, UCLA)araswattanford University26EE311/Interconnect13
Technology for Optical Interconnects on Si::Free Space TransmissionCritical issue is packaging technology(Jurgen Jahns, Fernuniversitätt Hagen, Germany)araswattanford University27EE311/InterconnectTechnology for Optical Interconnects on Si::Quantum Well Modulator(Miller, Harris, Stanford)Application of E-field changes optical transmissionthrough quantum well modulatorsaraswattanford University28EE311/Interconnect14
Flip-Chip Bonding of GaAs Modulatorsand Photodiodes to Silicon CMOS(Miller Group, Stanford)optical outputat 800 Mb/s Flip-chip bonding enables post-processing integration:– Mature CMOS process optimized optoelectronics– Dense 2D arrays bonded in parallel with high yieldaraswat– Low noise and high speeds due to reduced device capacitancetanford University29EE311/InterconnectGermanium – A Prospective MaterialSmall optical bandgap λ transparent to Si, no extracircuit noiseTelecomstandards Direct gap below 1.53µm Broadens λ spectrum for optoelectronic integration to enhanceCMOS functionalityGeGaAsSi Higher thermal leakageHigh carrier mobilities Short detector transit timeCompatible with Si IC Low processing temp(Stillman et al., IEEE TED, 31, p.1643, 1984)araswattanford University30EE311/Interconnect15
3D Integration of Ge Optoelectronic Devices on SiO2SiGepassivation MetalDielectricsc-Ge S/Dcrystallized-GeS/DILD2nd activeGe layerSi Devices with Metallization1st activeSi layerGe Photodetector Piecewisetechnologies readyfor the monolithicreceiver integrationin the near futureGe Transistor Employ recrystallization or layer transfer technique for Ge on Si Integration of optical receiver in the upper active (Ge) layer On-chip optical clock distribution in 3D-ICsSaraswat, Stanford Univ.araswattanford University31EE311/Interconnect3-D Integration: Motivation2D Area AVery Long Wire3DA/2A/22-D SystemNumber of InterconnectsShorter Wire(Log-Log Plot)2-D IC3-D ICWire-lengtharaswattanford University3-D System Integration of heterogeneous technologiespossible, e.g., memory & logic, optical I/O Reduce Chip footprint Replace long horizontal wires by shortvertical wires Interconnect length and therefore R, L, C – Delay reduction–Power reduction32EE311/Interconnect16
Importance of Form FactorSTAR TREK COMMUNICATORCell phoneGPS Hand-Held ReceiverDigital CameraMP3 playerPDAaraswattanford University33EE311/InterconnectWire-length Distribution of 3-D ICMicroprocessor Example93.6 million86.4 million50 nm91.673e-6 Ω-cm1E8ε r 2.5345 Single Layer1 453 22 LayersInterconnect Density21A significant fraction of horizontalwires replaced by vertical wiresaraswattanford UniversityInterconnect DensityNumber of Logic GatesNumber of Memory DevicesMinimum Feature SizeNumber of wiring levels,Metal Resistivity, CopperDielectric K, PolymerLogicMemoryLocalSemiglob 1101001000Interconnect Length, l (gate pitches)Souri, Banerjee, Mehrotra and Saraswat, ACM Design Automation Conf., June 2000.34EE311/Interconnect17
Delay of scaled 3D ICs with multiple Si layers Summary of delay results for ITRS technology nodes Moving repeaters to upper active layers reduces delay by 9% 3D (2 Si layers) shows delay reduction to 62% Increasing metal layers reduces delay further by 25%3D can alleviate interconnects limits101n /p Longest Interconnect DelayDelay Time (ns)2-D IC with repeaters100n /p GateRepeaters moved up3-D IC, constant metal layers3-D IC, 2X metal layers10-1Typical Gate DelayGate10-2n /p 6080n /p 100 120 140 160 180Technology Node (nm)Banerjee, Souri and Saraswat, Proc. IEEE, May 2001araswattanford University35EE311/InterconnectEffect of additional active layersNLogicNMemoryλMetal levelsρCuεr769X1066284X10650 nm91.67X10-6 Ω-cm1.5 Boundary condition: allfootprints increased to 2D Limited returns withincreased active layers dueto wire routing to highertiers 2 active layers show largestdelay improvementNormalized Interconnect DelayITRS 50 nm Technology Node10.90.80.70.60.50.40.30.21234No. of Active Layers5S. Souri, PhD Thesis, Stanford Univ., 2003araswattanford University36EE311/Interconnect18
Random vs. OptimizedRedistribution of Logic2DRandom redistribution“Optimized” redistribution Random redistribution: indiscriminate replacement of short/longwires with VILICs for generalized analysis Optimal redistribution: only critical paths replaced. Dependenton particular IC design Analysis so far conservative due to randomizing redistribution.With optimized redistribution gains would be higheraraswattanford University37EE311/InterconnectTechnology to Fabricate 3D ICs Bonding– Metal-metal– Dielectric glue Epitaxial growth Crystallization– Laser melting and crystallization– Seeded crystallization– Liquid phase crystallization Self assembled molecular devices– Si and Ge nanowires– Carbon nanotubes– Organic semiconductorsaraswattanford University38EE311/Interconnect19
Statistical Variations in Poly-TFT PropertiesSimulationsConventional Poly-TFTDeposited GateDielectricCrystallized usinglasers , RTA, or longfurnace annealsGrains inChannelGateGate OxideDrainChannelMobilityCumulative ProbabilitySmooth Interface(Crystallized a-Si)Grain size0.3-0.5 µmSourceSubstrate1.E-03ExperimentNumber of Grain Boundaries0 grain boundries1.E-04 As channel length grain size,statistical variation increases0, Ge-seeded1, unseeded12, unseeded 2 4, unseeded1.E-053ID (A/µm)1.E-06 Poly-Si TFTs not suitable for 3-D ICs. Grain boundaries need to be eliminated1.E-071.E-081.E-091.E-10VDS 2.0VW/L 0.3 µm/0.1 µm1.E-11Wang and Saraswat, IEEE Trans. Electron Dev., May 2000.araswattanford University1.E-12-2-101234VGS (V)39EE311/Interconnect3D Approaches: Epitaxial Lateral OvergrowthKey Challenges: High temperaturecompatible, low resistanceinterconnect technology Low temperature epitaxy( 400 oC)Source:G. Neudeck, Purdue Univ.araswattanford University40EE311/Interconnect20
3D Approaches: Cu Contact Wafer BondingWafer Bonding (MIT, IBM, and many more)Key Challenges: Precise alignment of wafers/diesaraswattanford University41EE311/Interconnect3D Approaches: Crystallization of α-SiFabricate devices at any metal level if thermal budget is lowSeed (Ni, Ge, etc)Gatea -Sin /p SiO2n /p Repeaters oroptical I/O devicesVILICM4SubstrateM3Locally induce nucleationM2M1Lateral crystallizationGaten /p n /p Grow single grain laterallyM2GateMemoryorAnalogM1Gate oxideSource Channel DrainGateSubstraten /p Vian /p T1LogicFabricate MOSFETaraswatT2Key Challenge: Low temperature defect free crystallizationtanford University42EE311/Interconnect21
Ni Seeded Lateral CrystallizationNMOS L 0.1µm, W 0.3 µmSiGe gateN N α-SisubstrateFabricate amorphous deviceId (A/µ m)SiO21.00E-03Vd 0.05 V1.00E-05Vd 2 V1.00E-071.00E-091.00E-11NiseedSiGe gate1.00E-13-2SiO2Crystallized Sisubstrateα-Si-10Vg (V)12 Low thermal budget (Tmax 500ºC) Devices on top of a metal line MOSFETs Optical detectorsUse seeding for simultaneouscrystallization and dopant activationJoshi & Saraswat, IEEE Trans. Electron Dev. 2003araswattanford University43EE311/Interconnect3D Image SensorFirst demo of 64x64 APS stacked on fully parallel ADC circuit4000 vertical interconnectsaraswattanford UniversitySource: Crais Casey, MIT Lincoln Laboratory44EE311/Interconnect22
Matrix Memory Array (8 geElementInput1Onwiring1layerSteeringElementOn wiring2wiring1layerlayerOnwiring2 Matrix memory is a 3D array of diode-antifuse cells. Diodes are inserted into the
ta nfo rdU ivesy 3 EE311/Interconnect araswat Interconnect Performance Requirements Technology Generation 1.0 µm 0.1 µm MOSFET Intrinsic Switching Delay 10 ps 1 ps Interconnect Response Time 1 ps 100ps (L int 1 mm) Clock Frequency 30 MHz 2-3.5 GHz Supply Current 2.5 A 150 A (V dd
Design Guide for High-density Interconnect Structures and Microvias IPC-2226: Sectional Design Standard for High-density Interconnect (HDI) Printed Boards IPC/JPCA-4104: Qualification and Performance Specification for Dielectric Materials for High-density Interconnect Structures (HDI) IPC-6016:
Cisco UCS 6454 Fabric Interconnect 8 Topology diagrams 15 Starting the X-Series configuration 16 Configure the first Fabric Interconnect for Cisco Intersight management. 16 Configure the second Fabric Interconnect for Intersight management 18 Claim the Fabric Interconnects in Cisco Intersight platform 19 Upgrade Fabric Interconnect firmware 22
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10 ex. 2" rmc 2 - 6pr #19 interconnect 1 11 ex. 2" pvc 1 - 6pr #19 interconnect 1 12 ex aerial 1 - 6pr #19 interconnect 1 13 2" pvc 2 1 14 2" pvc 2 1 15 2" pvc 2 1 16 3" pvc spare. construction notes. no r e v i s i o n date appd. city of tacoma.
Phono sockets. One end of each Naim interconnect cable is marked with a band to establish its correct orientation. The band denotes the end that connects to the signal source. Naim Hi-Line interconnect cables will provide the best results. Interconnect plugs and
2 ta nfo rdU ivesy 3 EE311/ Cu Interconnect araswat 1 1 A 1 C S1 1 A 1/S 1 SC S 0.5 0.5 1 1 A 1 C S1 1 0.5 C S1 0.5 0.5 A 1/S2 Interconnect Scaling Scenarios Scale Metal Pitch with Constant Height-R,C s andJ i cre
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