System-on-Chip Design With SystemC
System-on-Chip Designwith SystemCJoachim Gerlach gerlach@informatik.uni-tuebingen.de University of TübingenWilhelm-Schickard-InstitutDepartment of Computer Engineering
University ofTübingenDepartment ofComputerEngineeringContentsqBackground & Basicsm System-on-Chip Designm C/C Based System Designm The SystemC Approachm SystemC Licensing Modelm Open SystemC CommunityqIntroduction to SystemC 1.0m Modules & Hierarchiem Processesm Ports & Signalsm Data Types & Fixed Point Data TypesqDesign Example Am Simple 2-Process ScenarioBackground& BasicsSystemC 1.0DesignExample ADesignExample BDesignActivitiesToolSupportSystemC 1.1JoachimGerlachJoachim GerlachSystem-on-Chip Design with SystemC1
University ofTübingenContentsDepartment ofComputerEngineeringqDesign Example Bm JPEG Compression / Decompression StreamqDesign Activitiesm Modelingm Simulationm DebuggingqTool Supportm Synopsys: SystemC Compilerm CoWare: N2Cm C-Level Design: System Compilerm Frontier Design: AxRT BuilderqOutlook to SystemC 1.1Background& BasicsSystemC 1.0DesignExample ADesignExample BDesignActivitiesToolSupportSystemC 1.1JoachimGerlachJoachim GerlachSystem-on-Chip Design with SystemC2
SYSTEMCTMBackground & BasicsUniversity of TübingenWilhelm-Schickard-InstitutDepartment of Computer Engineering
University ofTübingenProductivity GapDepartment ofComputerEngineeringcomplexity[gates]Background& BasicsSystemC 1.0DesignExample ADesignExample entium IIPentium (0,35 µm)1M1M256K1K1K19704K8008486DX386DX64K16K10K/ M8080(source: ICE)19801990SystemC 1.1WolfgangRosenstiel(0,8 µm)productivitygap808819801990IP 0gates / day2000time(source: MEDEA Design Automation Roadmap 1999)Joachim GerlachSystem-on-Chip Design with SystemC4
University ofTübingenDepartment ofComputerEngineeringBackground& BasicsSystemC 1.0DesignExample ASystem Level DesignqSystem-on-Chips (SoC) designsqSoC designs containmMultiple design domains: hardware, software, analog, .mMultiple source components: DSPs, ASICs, IP-Cores, .mHard constraints: realtime, low power, .DesignExample BDesignActivitiesToolSupportSystemC 1.1WolfgangRosenstielJoachim GerlachSystem-on-Chip Design with SystemC5
University ofTübingenSystem Level Design FlowDepartment tionBackground& Basicsco-designarchitecturalvalidationSystemC 1.0DesignExample Bsoftwareimplementationsoftware architectureDesignActivitiesToolSupportSystemC 1.1WolfgangRosenstielJoachim apRTOSprocessor essorSystem-on-Chip Design with SystemChardware architecturealgorithmicmodelsDesignExample A6
University ofTübingenDepartment ofComputerEngineeringBenefits of a C/C Based Design FlowqBackground& BasicsSystemC 1.0DesignExample AqDesignExample BDesignActivitiesToolSupportqSystemC 1.1Productivity aspectmSpecification between architect and implementer is executablemHigh speed and high level simulation and prototypingmRefinement, no translation into hardware (no “semantic gap”)System level aspectmTomorrow’s systems designers will be designingmostly C/C software and less hardware !mCo-design, co-simulation, co-verification, co-debugging, .Re-usemSystemaspectArchitectSoCDesignMarketing& SalesOptimumC/C re-use support by object-oriented techniquesHDLWolfgangRosenstielmqEfficient testbench re-useSoftwareHardwareEspecially C/C is widespreadandcommonly used !Joachim GerlachDesignerDesignerSystem-on-Chip Design with SystemC7
University ofTübingenDepartment ofComputerEngineeringBackground& BasicsDrawbacks of a C/C Based Design FlowqC/C is not created to design hardware !qC/C does not supportmSystemC 1.0DesignExample ADesignExample BlmmSystemC 1.1WolfgangRosenstielHardware is inherently concurrent, operates in parallelReactivitylmClocks, time sequenced operationsConcurrencylmSignals, protocolsNotion of timelDesignActivitiesToolSupportHardware style communicationHardware is inherently reactive, responds to stimuli,interacts with its environment ( requires handling of exceptions)Hardware data typeslJoachim GerlachBit type, bit-vector type, multi-valued logic types,signed and unsigned integer types, fixed-point typesSystem-on-Chip Design with SystemC8
University ofTübingenHow to Get “Synthesizable C/C ” ?Department ofComputerEngineeringBackground& Basicsqsynthesizablesubset of Crestriction tosynthesizable subsetSystemC 1.0DesignExample ACStep-1:qDesignExample BStep-2:C extension pportmSystemC 1.1mWolfgangRosenstielqsynthesizablesubset of C hardware typecommunicationnew language constructs(HardwareC, C*)library based approach(SystemC, Cynlib)notionof timehardwaredata 1 and step-2 can be swapped !Joachim GerlachSystem-on-Chip Design with SystemC9
University ofTübingenDepartment ofComputerEngineeringWhy SystemC for System Design ?qThe GapmBackground& BasicsmSystemC 1.0DesignExample ADesignExample BDesignActivitiesToolSupportSystemC 1.1qTomorrow’s systems designers will be designingmostly software and little hardwareA software language is not capable of describingconcurrency, clocks, hardware data types, reactivityRequirementsmmmmAllow hardware/software co-design and co-verificationFast simulation for validation and optimizationSmooth path to hardware and softwareSupport of design and architectural re-useJoachimGerlachJoachim GerlachSystem-on-Chip Design with SystemC10
University ofTübingenDepartment ofComputerEngineeringWhat is SystemC ?qA library of C classesm Processes (for concurrency)m Clocks (for time)m Modules, ports, signals (for hierarchy)m Waiting, watching (for reactivity)m Hardware data typesqA modeling stylem . for modeling systems consisting of multipledesign domains, abstraction levels, architecturalcomponents, real-life constraintsqA light-weight simulation kernelm . for high-speed cycle-accurate simulationBackground& BasicsSystemC 1.0DesignExample ADesignExample BDesignActivitiesToolSupportSystemC 1.1JoachimGerlachJoachim GerlachSystem-on-Chip Design with SystemC11
University ofTübingenHow Does it Work ?Department ofComputerEngineeringSystemBackground& BasicsC/C TestbenchC/C SoftwareComponentSystemC 1.0DesignExample ADesignExample BModelingConstructsC/C vitiesToolSupportSystemCSystemC 1.1JoachimGerlachStandardC CompilerExecutable SimulatorJoachim GerlachSystem-on-Chip Design with SystemC12
University ofTübingenDepartment ofComputerEngineeringBenefits of a SystemC-Based Design FlowqClassical HDL based design methodologyBackground& BasicsSystemC 1.0DesignExample AsystemarchitectC/C 4. hand overspecificationdocumentDesignExample BDesignActivitiesToolSupportSystemC 1.11. conceptualize2. simulate in C/C 3. write specification3. document6. (re)implement in HDL7. (re)validate HDL7. implementationHDL8. synthesize from HDLhardwaredesignerWolfgangRosenstielJoachim GerlachSystem-on-Chip Design with SystemC13
University ofTübingenDepartment ofComputerEngineeringBenefits of a SystemC-Based Design FlowqC/C based design methodologyBackground& BasicsC/C SystemC 1.01. conceptualize2. simulate in C/C 3. write specification documentDesignExample ADesignExample BDesignActivitiessystemarchitectToolSupport4. hand over executable specification testbenches written specificationhardwaredesignerC/C 5. understand specification6. refine in C/C 7. validate re-using testbenches8. synthesize from C/C SystemC 1.1WolfgangRosenstielJoachim GerlachSystem-on-Chip Design with SystemC14
University ofTübingenDepartment ofComputerEngineeringThe SystemC ApproachqBackground& BasicsThe requirements.mFast system modeling containing multiple source componentsmModel once for multiple abstraction level, multiple users,multiple purposesSystemC 1.0DesignExample AqDesignExample BDesignActivitiesToolSupportSystemC 1.1The problem.mqNo common format for describing componentsThe approach.mPromote a standard C/C based modeling platform. to model and exchange system level components and IP. to build interoperable tools infrastructureWolfgangRosenstielJoachim GerlachSystem-on-Chip Design with SystemC15
University ofTübingenDepartment ofComputerEngineeringBackground& BasicsSystemC 1.0DesignExample AThe SystemC ApproachqWhy C/C based ?mSpecification between architect and implementer is executablemHigh simulation speed at higher level of abstractionmRefinement, no translation into HDL (no “semantic gap”)mEfficient testbench re-useDesignExample BC/C DesignActivitiesSystemArchitectToolSupportSystemC 1.1SoCDesignC/C WolfgangRosenstielHDLSoftwareDesignerJoachim GerlachMarketing& SalesHardwareDesignerSystem-on-Chip Design with SystemC16
University ofTübingenSystemC Modeling PlatformDepartment ofComputerEngineeringBackground& BasicsSystemC 1.0DesignExample ADesignExample BS Y S T E MCTMis. a methodology for modeling SoC designs consisting of. DSPs, ASICs, IP-Cores, Interfaces, . a C library extending C/C by concurrency, timing,. reactivity, communication, signal / data types, .DesignActivitiesToolSupport. a cycle-accurate high-speed simulationSystemC 1.1WolfgangRosenstielJoachim GerlachSystem-on-Chip Design with SystemC17
University ofTübingenSystemC Design MethodologyDepartment ofComputerEngineeringyour standardC/C developmentenvironmentheader filesSystemC 1.0linkerclass libraryandsimulation kerneldebugger.DesignExample BIP-CorecompilerlibrariesDesignExample ADesignActivities„make“ToolSupporteabl on “tuec icatixe„ ecifspSystemC 1.1DSPInterface.Background& BasicsASICsource filesfor system andtestbenchesa.outexecutable simulationWolfgangRosenstielJoachim GerlachSystem-on-Chip Design with SystemC18
University ofTübingenDepartment ofComputerEngineeringBackground& BasicsSystemC Key FeaturesqConcurrency(Sync. and async. processes)qNotion of time(Multiple clocks with arbitrary phase relation)qData types(Bit vectors, arbitrary precision integers, .)SystemC 1.0DesignExample ADesignExample Bv1.0: arbitrary precision fixed point data typesqCommunication(Signals, channels)v1.0: advanced communication protocolsqReactivity(Watching for events)DesignActivitiesqDebug support(Waveform tracing)ToolSupportqSimulation supportSystemC 1.1qSupport of multiple abstraction levels and iterative refinementqSupport of functional model creationq.WolfgangRosenstielJoachim GerlachSystem-on-Chip Design with SystemC19
University ofTübingenDepartment ofComputerEngineeringBackground& BasicsOpen Community LicensingqHow to get SystemC ?Steering GroupSystemC v0.9SystemC 1.0including:DesignExample AdownloadDesignExample B Modeling specification Source code(reference implementation) Reference stemC 1.1click-through web-basedlicense agreementUserWolfgangRosenstielJoachim GerlachSystem-on-Chip Design with SystemC20
University ofTübingenDepartment ofComputerEngineeringOpen SystemC Steering GroupqARMqCadenceBackground& BasicsqCoWareSystemC 1.0qEricssonDesignExample AqFujitsu MicroelectronicsqInfineon TechnologiesqLucent TechnologiesqMotorolaqNECqSony CorporationqSTMicroelectronicsqSynopsysqTexas InstrumentsDesignExample BDesignActivitiesToolSupportSystemC 1.1WolfgangRosenstielJoachim GerlachSystem-on-Chip Design with SystemC21
University ofTübingenDepartment ofComputerEngineeringBackground& BasicsSystemC 1.0DesignExample ADesignExample BDesignActivitiesToolSupportSystemC 1.1Community Charter MembersActelFujitsu MicroelectronicsSony CorporationAlcatelGenedaxStellar SemiconductorAltera CorporationIKOS SystemsSTMicroelectronicsAmerican Applied ResearchI-LogixSummit DesignAptixInfineon TechnologiesSun MicrosystemsArcadia Design SystemsIntegrated Silicon SystemsSynaptiCADARC CoresIntellectual PropertySynchronicityAristo TechnologyInternet CADSynopsysARMJTA ResearchTensilicaBillions of Operations Per SecondLogicVisionTexas InstrumentsCAE PlusLucent TechnologiesTransModelingChameleon SystemsMagma Design AutomationUltimaCo-Design AutomationMIPS TechnologiesVerplexCoWareMonterey Design SystemsViewlogicCSELTMotorolaVirtioDenaliRed HatVirtual Silicon TechnologiesEricssonSeva Technologies (Intrinsix)Willamette HDLFrequency TechnologySican MicroelectronicsWind River SystemsFrontier DesignSnaketechXilinxWolfgangRosenstielJoachim GerlachSystem-on-Chip Design with SystemC22
University ofTübingenDepartment ofComputerEngineeringOpen Community LicensingqCommunity membersmNo licensing fees, anybody / any company is free and welcometo join the communitySystemC 1.0mRight and responsability to contribute enhancementsDesignExample AmDesigners can create and share models with other companies,EDA vendors can build SystemC based toolsBackground& BasicsDesignExample BqDesignActivitiesToolSupportSystemC 1.1WolfgangRosenstielqSteering GroupmDrives convergence and interoperabilitymEnsures open evolution and structured innovationGoal:mMake SystemC a de-facto-standard for system-level designmProvide a foundation to build a market uponJoachim GerlachSystem-on-Chip Design with SystemC23
University ofTübingenDepartment ofComputerEngineeringSystemCqShort History of SystemCBackground& BasicsSystemC 1.0DesignExample AV0.9 launches9/27/1999SceneryV1.0 release3/28/2000DesignExample BDesignActivitiesfixed point datatypes1997 DAC PaperToolSupportSystemC 1.1HDL m GerlachSystem-on-Chip Design with SystemC24
University ofTübingenDepartment ofComputerEngineeringSystemCqEuropean SystemC Users GroupmBackground& BasicsSystemC 1.0DesignExample AmCommunication platform for SystemC userstake a look at:Information flow between SystemC users und Steering Groupwww-ti.informatik.uni-tuebingen.de/ systemcmAcceleration of SystemC evolution and standardizationmEvents:DesignExample BDesignActivitiesToolSupportFDL’20001st European SystemC Users Group Meeting3rd European SystemC Users Group MeetingSystemC Release 1.0SystemC 1.1WolfgangRosenstiel2nd European SystemC Users Group MeetingEuropean SystemC Users Group Conference(with DATE’2001)2000January 312000Joachim Gerlach2001March 28 June 30 September 4-8200020002000System-on-Chip Design with SystemCMarch 12-16200125
SYSTEMCTMSystemC 1.0University of TübingenWilhelm-Schickard-InstitutDepartment of Computer Engineering
University ofTübing
Joachim Gerlach System-on-Chip Design with SystemC University of Tübingen Department of Computer Engineering 1 q Background & Basics m System-on-Chip Design m C/C Based System Design m The SystemC Approach m SystemC Licensing Model m Open SystemC Community q Introduction to SystemC 1.0 m Modules & Hierarchie m Process
10.3.5 Connecting ADC and DAC IPs into a Cortex-M system 242 10.4 243Bring an SoC to life – Beetle test chip case study 10.4.1 Beetle test chip overview 243 10.4.2 Beetle test chip challenges 245 10.4.3 Beetle test chip system design 246 10.4.4 Implementation of the Beetle test chip 24
Nomenclature bch Chip width (mm), (in) bγ1 Insert/chip restricted contact length (mm), (in) Ch Cutting ratio (the ratio of the undeformed chip thickness to the chip thickness) d Depth of cut (mm), (in) d0 The standard critical depth of cut under pre-defined standard cutting condition (mm), (in) dmax Maximum depth of cut in extra region of chip-breaking chart (mm), (in)
The parallel chip breaker, that the figure N 1 shows an example, is mainly used in finishing operations. Figure N 1 - Parallel chip breaker Inclined chip breaker The angular type is suitable for most machining operations and is the most difficult to do. The chip is flexed towards the area of the workpiece where is broken without damaging .
NEW CHIP BREAKER FGS TYPE FGS type chip breaker The FGS chip breaker is a positive ground type insert. Its sharp cutting edge generates low cutting resistance while guarantee-ing high precision machining. The chip breaker minimizes heat when machining heat resistant super alloys and the small dot located in the corner is effective for chip control.
1.1 Chip breaker A chip breaker is the tool which has a groove or an obstacle placed on the incline face of the tool. A chip breaker can be used for increasing chip breakability which results in efficient chip control and improved productivity. It also decreases cutting resistance, and gives a better surface finish to the workpiece.
and processing unit in a single chip have been reported [7]-[13]. These architectures are proposed for a photo-image sensing chip. Fig. 1 shows the conventional photo-image-sensing chip architecture. In the architecture for a sensor-embedded chip, the sensor and processing unit are integrated on a single chip by placing them side by side, as .
provided with the Keiser Chip System. For operation of the Keiser Chip System, see the Keiser Chip System Operation Manual. The Keiser Chip System is designed to be an electronic replacement for a hand written exercise card by storing selected information about a user's recent workouts to be used in setting the exercise machine on the next visit.
Modern System-on-Chip Design on Arm David J. Greaves TEXTBOOK SoC Design. Modern System-on-Chip Design on Arm DAVID J. GREAVES. . 3.4 Network-on-Chip 113 3.4.1 NoCRoutingandSwitching 115 3.4.2 VirtualChannels 118 3.4.3 NoCDeadlocks 118 3.4.4 Credit-basedFlowControl 122 3.4.5 AMBA5CHI 124 vii.
