Lab 4c: Communications SPI Serial Protocols 1 Objectives 2 .
1300 Henley CourtPullman, WA 99163509.334.6306www.store.digilent.comLab 4c: Communications – SPI Serial ProtocolsRevised April 25, 2017This manual applies to Unit 4, Lab 4c.1Objectives1.2.3.2Learn how to configure an SPI channel on the PIC32MX370 processor.Learn the difference between software and hardware handshaking.Learn how to communicate with an SPI FLASH memory device.Basic Knowledge1.2.3.How to configure I/O pins on a Microchip PIC32 PPS microprocessor.How to configure the Analog Discovery 2 to display logic traces.How to implement code reuse that integrates previously developed processor code into new applicationprojects.3Equipment List3.1Hardware1.2.3.Basys MX3 trainer boardWorkstation computer running Windows 10 or higher, MAC OS, or Linux2 Standard USB A to micro-B cablesIn addition, we suggest the following instruments:4.3.2Analog Discovery 2SoftwareThe following programs must be installed on your development work station:1.2.3.4.5.Microchip MPLAB X v3.35 or higherPLIB Peripheral LibraryXC32 Cross CompilerWaveForms 2015 (if using the Analog Discovery 2)PuTTY Terminal EmulationUnit 4, Lab 4cCopyright Digilent, Inc. All rights reserved.Other product and company names mentioned may be trademarks of their respective owners.Page 1 of 19
Lab 4c: Communications – SPI Serial Protocols4Project Takeaways1.2.3.5Understanding of requirements and implementations of synchronous communications.Understanding of the SPI protocol.How to generate instruction sets for controlling SPI devices.Fundamental ConceptsSerial Peripheral Interface (SPI) is a master-slave interface bus commonly used to send data betweenmicrocontrollers and small peripherals such as analog-to-digital converters, instrumentation sensors, and solidstate memory devices. It uses a separate clock, send and receive data lines, and a device select signal. ThePIC32MX370 has built-in hardware circuits to support two SPI channels. Since SPI and I 2C have been used in similarapplications, there is frequently a comparison of the two protocols, such as presented in Reference 4.5.1Software HandshakingWe can see the application of hardware handshaking for synchronizing data transfers for both the asynchronousUART that used start and stop bits, and synchronous I 2C communications that uses the ACK bit. Softwarehandshaking involves exchanging data that indicates the status of slave devices. An example of softwarehandshaking with parallel I/O is polling the LCD busy flag. When using the UART, there is the XON/XOFFhandshaking that is used for information flow control.We will see that the flash memory device used on the Basys MX3 board requires command strings to place thedevice in different operating modes and to read device internal registers for determining status. Since SPI is asynchronous communications protocol, the clock signal manages the hardware element of the devicesynchronization.5.2SPI CommunicationsThe SPI serial protocol is capable of higher data rates than I2C because it can generally operate at higher clockrates, and is not limited to 8-bits per word. Although I2C requires only two wires (thus conserving processor pins),rather than four wires required by SPI, I2C has bandwidth overhead due to the time required for device selectionby sending the ID as a serial byte. Unlike I2C, SPI has no device acknowledge capability.SPI is a full-duplex synchronous serial communications bus protocol developed by Motorola and has become a defacto standard that has not been adopted by any national or international standards organizations. As with the I2Cprotocol, the SPI bus implements a master-slave communications scheme where the master device alone controlsthe data exchange with slave devices. The master device has exclusive control of the serial clock (SCK) signal that isused to clock the data to and from a slave device.SPI requires four wires for full-duplex operation and supports only one master but multiple slave devices. Themaster writes data to the slave using the Master Out Slave In (MOSI) line. The slave devices are able to send datato the master over the Master In Slave Out (MISO) line. Other than the clock signal, all handshaking is handled byan explicit slave select (SS) or chip select (CS) signal.Figures 5.1 and 5.2 illustrate the two common SPI bus connection configurations. Figure 5.1 shows that themultiple slave devices share SCK, MOSI, and MISO signals. For this connection configuration, the slave devices areCopyright Digilent, Inc. All rights reserved.Other product and company names mentioned may be trademarks of their respective owners.Page 2 of 19
Lab 4c: Communications – SPI Serial Protocolsexplicitly selected by multiple dedicated SS microprocessor outputs. This is the more common SPI connectionconfiguration.Figure 5.2 shows a daisy-chain configuration where slave devices share both the SCK and SS signals, and the MOSIand MISO signals are routed through a series of slave devices. Using this configuration, data intended for the lastdevice in the chain must be clocked through the preceding slave devices. Data that is to be read from the first slavedevice in the chain must also be clocked through the slave devices that follow it in the chain. This additional datatransfer time is the cost of conserving processor I/O pins used for enabling slave devices. Due to the excessive datatransfer time for systems with many slave devices, this configuration is seldom used.Figure 5.1. Parallel multiple slave SPI bus configuration withindividual device select signals.Figure 5.2. Daisy chain multiple slave SPI bus configuration with acommon device select signal.When the microprocessor is connected to a slave device that has both input and output capability using SPI, asdata is clocked out of the master, data is also clocked in from the slave device. This results in efficient datatransfers for some slave devices. The loosely defined SPI interface requires careful consideration of the slave clockdata timing, as well as using a microprocessor that can be configured to support various timing requirements.Figure 5.3 shows the clock-data timing for the four SPI operating modes. The clock polarity (CPOL) controls the idlelevel of the SCK output from the master. If CPOL is high, then the idle level of SCK is high. The clock phase (CPHA)specifies when the data is to be changed or written to MOSI by the master and to MISO by the slave device. Forexample, when CPHA is low, the data signal (MISO for master and MOSI for the slave) is sampled by the receivingdevice when SCK makes a transition from the idle level to the active level.Figure 5.3. SPI timing modes.Copyright Digilent, Inc. All rights reserved.Other product and company names mentioned may be trademarks of their respective owners.Page 3 of 19
Lab 4c: Communications – SPI Serial ProtocolsFigure 5.4 shows the PIC32 settings for clock edge (CKE) and clock polarity (CKP). Table 5.1 provides the correlationbetween the conventional definitions of SPI mode CPHA and CPOL to those CKE and CKP settings. (Note: There isan apparent error in the Microchip table shown in Fig. 5.4. Both CKE and CKP should be equal to 1 for the fourthcase of the SCK timing diagrams.) It is important to match the master processor operation to what the slave deviceis expecting. For some designs, it is possible for different slave devices to expect the master to operate in modesthat are not the same. The PIC32 operating modes can be changed during program execution, but the modesshould not be changed when the processor is actively clocking data on the SPI bus.Table 5.1. SPI SCK operational modes.SPI ModeActive Level0 (or 0,0)1 (or 0,1)2 (or 1,0)3 (or 1,1)HighHighLowLowSampleTransitionIdle to ActiveActive to IdleIdle to ActiveActive to IdleCPOLCPHAPIC32 CKPPIC32 CKE0011010100111010Copyright Digilent, Inc. All rights reserved.Other product and company names mentioned may be trademarks of their respective owners.Page 4 of 19
Lab 4c: Communications – SPI Serial ProtocolsFigure 5.4. PIC32 SPI control setting to specify the sample timing (Reproduced from Microchip PIC32 Family Reference Guide Section 23, Fig. 237).SPI master-slave communications can be operated in either simplex or full-duplex modes. Simplex communicationsoccur when the slave device can only send or receive data. Regardless of which device, master or slave, is sendingthe data, the master always provides the SCK signal. Although the phase and sample timing can differ betweendevices using SPI, the data is always active high (a high level represents a logical 1.)Copyright Digilent, Inc. All rights reserved.Other product and company names mentioned may be trademarks of their respective owners.Page 5 of 19
Lab 4c: Communications – SPI Serial ProtocolsData is sent and received by transferring the most significant bit (MSB) on the first clock pulse. We will define atransfer transaction as the exchange of data while the SS signal is continuously asserted in the active state (usuallya low level.) For a specific transaction, if multiple bytes are to be transferred, the byte counter in the slave device isreset when the SS signal is asserted. There is no start and stop sequence or byte acknowledge like that used withI2C. Data can be transferred as 8-, 16-, or 32-bit words. There is no limit to how much data can be transferred in asingle transaction.A data bit is shifted into the receiving device at the same time as the data bit is shifted out. Hence, once a word ofdata has been sent, the device has also received the next word. The SPI uses SCK clock edges to implement eachbit transfer. At one SCK edge, each data sends a bit of data on the send line. The opposite clock edge a half of SCKclock cycle later, a data bit on the receive line is clocked into the receiving device. The specific clock edges arespecified by the SPI mode of operation. The SCK signal can be asymmetrical as long as the period of the high or lowstate is greater than the inverse of two times the maximum data rate.6Problem StatementYou are to develop a software system that allows the PIC32MX370 to write an arbitrary number of 8-bit bytes toan arbitrary address location in the SPI flash memory device. You must be able to read back this stored data anddetermine if the data read matches the data written.7Background Information7.1PIC32MX370 SPI I/OFigure 7.1 shows the signal connections to the S25FL132K flash memory IC. Table 7.1 lists the PIC32MX370processor pins that these signals are connected to. The PIC32 processor pin for the SPI CE signal is configured as adigital output pin, as shown in Listing B.1. To implement the wiring configuration shown in Fig. 7.1, processor I/Opins PORT F:2 and PORTF:7 are mapped to SPI1T and SPI1R respectively using the first two statements in Listing B.2in Appendix B. The PIC32MX370 PORTF:6 has a fixed assignment to SCK1.Figure 7.1. SPI flash memory IC schematic diagram.Copyright Digilent, Inc. All rights reserved.Other product and company names mentioned may be trademarks of their respective owners.Page 6 of 19
Lab 4c: Communications – SPI Serial ProtocolsTable 7.1. SPI Flash Memory to PIC32MX370 connection table.7.2FunctionFlash Memory PinPIC32MX370 PinChip EnableSPI CE – 1PORT F Pin 8Serial ClockSPI SCK – 6PORT F Pin 6 – SCK1Flash Serial InputSPI SI – 5PORT F Pin 2 – SPI1R (MISO)Flash Serial OutputSPI SO – 2PORT F Pin 7 – SPI1T (MOSI)Interface with SPI Flash MemoryUsing the SPI initialization shown in Listing B.2, the PIC32 processor is configured for SPI Mode 0 operation. Figure7.2 shows that the bit output is held constant when the clock pulse makes a positive transition. Figure 7.2 alsoshows that the bit rate is 1 MHz.Figure 7.2. SPI Bit timing for Mode 0 configuration.As Fig. A.2 shows, the same SPIxSR serial shift buffer is used for input and output, thus requiring the common SCKxclock signal. Hence, when a byte of data is shifted out of the SDOx pin, data is also being shifted into the SPIxSRfrom the SDIx pin. In other words, to receive SPI serial data, you must send SPI serial data.Listing B.3 shows the function that can be used to send, receive, or exchange a byte of data using SPIcommunications. In most cases, when the SPI master is sending header data to the slave, the master SPI ignoresthe data received on the SDIx pin. Similarly, as the master continues to send non-consequential data during a SPIslave read operation, the slave SPI discards the data sent to it. The SPI master clock must be generated for bothsending and receiving.7.2.1 SPI Flash Memory SoftwareWe will use the S25FL132K SPI FLASH 132 MB memory device that is populated on the Basys MX3 processor boardto demonstrate SPI device communications. The characteristics of this FLASH device are not representative of allcontrol protocol used by SPI silicon devices. The FLASH memory device has command and status/configurationregisters that can be accessed independently of the memory data.Each device transaction is started with a command from the PIC32 processor. The command set of the S25FL132KFlash Memory is fully controlled through the SPI bus. Commands are initiated with the falling edge of Chip Select(CS#). The first byte of data clocked into the SI input provides the instruction code. Data on the SI input is sampledon the rising edge of clock with most significant bit (MSB) first.Commands vary in length from a single byte to several bytes. Each command begins with an instruction code andmay be followed by address bytes, a mode byte, read latency (dummy/don’t care) cycles, or data bytes.Copyright Digilent, Inc. All rights reserved.Other product and company names mentioned may be trademarks of their respective owners.Page 7 of 19
Lab 4c: Communications – SPI Serial ProtocolsCommands are completed with the rising edge of edge CS#. Clock relative sequence diagrams for each commandare included in the command descriptions. All read commands can be completed after any data bit. However, allcommands that Write, Program, or Erase must complete on a byte boundary (CS# driven high after a full 8 bitshave been clocked) otherwise the command will be ignored. This feature further protects the device frominadvertent writes. Additionally, while the memory is being programmed or erased, all commands except for ReadStatus Register and Suspend commands will be ignored until the program or erase cycle has completed. When theStatus Register is being written, all commands except for Read Status Register will be ignored until the StatusRegister write operation has completed.Since the data sheet for this Flash memory device is quite daunting, excerpts from that manufacturers data sheetsare shown in Table 7.2 through 7.5 with the commands highlighted that can be used to implement basic FLASHmemory management.The highlighted commands in Table 7.2 allow for reading basic device identification parameters. Each command issent to the device followed by zero to five read bytes. It is recommended that the “Release Power down/DeviceID” command be sent as part of a Flash initialization process. Figure 7.3 shows the screen capture for the SPItransaction of this command. For the S25FL132K Flash part, the device ID is 21 or 0x15 as demonstrated in Fig. 7.3.Table 7.2. Command Set (ID and Security Commands)1Command NameDeep Power-downRelease PowerDown / Device IDManufacturer /Device ID (2)JEDEC IDRead SFDP Register/ Read Unique IDNumberRead SecurityRegisters (3)Erase SecurityRegisters (3)Program SecurityRegisters (3)1BYTE 1(Instruction)B9hBYTE 2BYTE 3BYTE 4BYTE 5BYTE 6ABhDummyDummyDummyDevice ID (1)90hDummyDummy00hManufacturerDevice ummy(D7-D0, )48hA23-A16A15-A8A7-A0Dummy(D7-D0, )44hA23-A16A15-A8A7-A042hA23-A16A15-A8A7-A0D7-D0, S25FL132K and S25FL164K Data Sheet, http://www.mouser.com/ds/2/380/S25FL132K 164K 00-268210.pdfCopyright Digilent, Inc. All rights reserved.Other product and company names mentioned may be trademarks of their respective owners.Page 8 of 19
Lab 4c: Communications – SPI Serial ProtocolsFigure 7.3. Release Power Down/Read Device ID SPI transaction.The flash memory status register, SR0, has two volatile bits, bits 0 and 1, that indicate the current operationalstatus of the memory chip. When WEL (bit 1) is set high, the device can be written to erase or program. The PageProgram command (0x02) allows from one byte to 256 bytes (a page) of data to be programmed at previouslyerased (0xFF) memory locations. A Write Enable command must be executed before the device will accept thePage Program Command (Status Register bit WEL 1). The command is initiated by driving the CS# pin low thenshifting the instruction code “02h,” followed by a 24-bit address (A23-A0) and at least one data byte, into the SIpin. The CS# pin must be held low for the entire length of the command while data is being sent to the device.Refer to section 8 of the Flash Memory data sheet (Reference 5) for additional information.Table 7.3. Command set (Configuration, Status, Erase, Program Commands) 2CommandNameRead StatusRegister - 1Read StatusRegister - 2Read StatusRegister - 3Write EnableWriteDisableWrite StatusRegistersSet Burstwith WrapSet Block /PointerProtection(S25FL132K /S25FL164K)PageProgram2BYTE 1(Instruction)BYTE 205hSR1[7:0] (2)(4)35hSR2[7:0] (2)(4)33hSR3[7:0] (2)BYTE 3BYTE 4BYTE 5BYTE 23-A16A15-A10, x,xxxh02hA23-A16A15-A8A7-A0SR3[7:0] (3)D7-D0S25FL116K, S25FL132K, S25FL164K, ht Digilent, Inc. All rights reserved.Other product and company names mentioned may be trademarks of their respective owners.Page 9 of 19
Lab 4c: Communications – SPI Serial ProtocolsSector Erase(4 kB)Block Erase(64 kB)Chip EraseErase /ProgramSuspendErase 8A7-A0C7h / 60h75h7AhTable 7.4. Status Register 0 bit otect 06SEC5TB432BP2BP1BP0Block ProtectBits1WELWrite EnableLatchVolatile, Readonly00BUSTEmbeddedOperationStatusVolatile, Readonly0BitsSector / BlockProtectTop / BottomProtectTypeDefaultState0Non-volatileand Volatileversions00000Description0 WP# input has no effect of PowerSupply Lock Down mode1 WP# input can protect the StatusRegister or OTP Lock Down.0 BP2-BP0 protect 64 kB blocks1 BP2-BP0 protect 4 kB sectors0 BP2-BP0 protect from the Top down1 BP2-BP0 protect from the Bottom up000b No protection0 Not Write Enabled, no embeddedoperation can start1 Write Enabled, embedded operationcan start0 Not Bust, no embedded operation inprogress1 Busy, embedded operation in progressAny number of bytes can be read from the flash device starting at any address. As Table 7.5 illustrates, a readcommand (0x03) initializes the starting address. The read operation is terminated whenever the CS# pin is assertedhigh.Table 7.5. Command Set (Read Commands).CommandNameBYTE 1(Instruction)BYTE 2BYTE 3BYTE 4Read Data03hA23-A16A15-A8A7-A0Fast ReadFast Read DualOutputFast Read QuadOutput0BhA23-A16A15-A8A7-A0(D7-D0, -A0DummyCopyright Digilent, Inc. All rights reserved.Other product and company names mentioned may be trademarks of their respective owners.BYTE 5BYTE 6(D7-D0, )(D7-D0, )(1)(D7-D0, )(3)Page 10 of 19
Lab 4c: Communications – SPI Serial ProtocolsFast Read DualI/OFast Read QuadI/OContinuous ReadMode Reset (6)BBhA23-A8 (2)EBhA23-A0, M7M0 (4)FFhFFhA7-A0, M7M0 (2)(x, x, x, x,D7-D0, ) (5)(D7-D0, )(1)(D7-D0, )(3)Figure 7.4. SPI Flash Read Byte command and three-byte address followed by reading data 'A', 'B', 'C', etc.8Lab 4c8.1Requirements1.2.3.The PIC32MX370 UART channel 4 must operate at 38400 BAUD with no parity.Two buffers must be created of size 1024 bytes.Generate a 550-byte data set using the following code:#define nBytes 550for(i 0; i nBytes; i ){wrBuffer[i] (BYTE) ('A' i);}4.5.6.7.// Initialize array for FLASH writeWhenever the push button, BTN
2. Understanding of the SPI protocol. 3. How to generate instruction sets for controlling SPI devices. 5 Fundamental Concepts Serial Peripheral Interface (SPI) is a master-slave interface bus commonly used to send data between microcontrollers and small peripherals such as analog-
The XM25QH32B of non-volatile flash memory device supports the standard Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (quad I/O or QIO) serial protocols. This multiple width interface is called SPI Multi-I/O or MIO.
The objective of this lecture is to learn about Serial Peripheral Interface (SPI) and micro SD memory cards. 2. SPI Introduction Serial Peripheral Interface (SPI) communication was used to connect devices such as printers, cameras, scanners, etc. to a desktop computer; but it has largely been replaced by USB. SPI is still utilized as aFile Size: 741KB
C8051F700 Serial Peripheral Interface (SPI) Overview. 2 . C8051F700 device features SPI operation overview SPI module overview Where to learn more. 3 Introducing The C8051F700 New patented capacitive touch sense True capacitance-to-digital converter Robust and responsive . SPI USB Configurati
The support and marketing staff of Ricoh Sales companies, including Ricoh family group . B264 Aficio 3035 SP/SPF/Spi/G 8035 SP/SPF/Spi/G DSm735 SP/SPF/Spi/G LD235 B265 Aficio 3045 SP/SPF/Spi/G 8045 SP/SPF/Spi/G DSm745 SP/SPF/Spi/G LD245 B276 Aficio MP 1600 9016 DSm716 LD316 B277 Aficio MP 2000 9021d DSm721d LD320 .
This manual describes the installation and operation of the SYSMAC CS/CJ-series CS1W-SCB@1-V1 Serial Communications Boards and CS1W-SCU@1-V1, CJ1W-SCU@1-V1, and CJ1W-SCU@2 Serial Communications Units. It includes the sections described on the next page. The Serial Communications Boards are classified as Inner Boards and the Serial Communications
MPC5121e Serial Peripheral Interface (SPI), Rev. 0 Description of the SPI module 2 Freescale Semiconductor diodes (LCD), analog-to-digital converter subsystems, etc. The SPI is a very simple synchronous serial data, master/slave protocol based on four lines:
SPI NAND Flash supports Quad SPI operation when using the x4 and Quad IO commands. These commands allow data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become bidirectional I/O pins: SIO0 a
Introduction to Literature, Criticism and Theory provides a completely fresh and original introduction to literary studies. Bennett and Royle approach their subject by way of literary works themselves (a poem by Emily Dickinson, a passage from Shakespeare, a novel by Salman Rushdie), rather than by way of abstract theoretical ideas and isms. In 32 short chapters they focus on a range of .
