C8051F700 Serial Peripheral Interface (SPI) Overview
C8051F700 Serial Peripheral Interface(SPI) Overview
Agenda C8051F700 block diagram C8051F700 device features SPI operation overview SPI module overview Where to learn more2
Introducing The C8051F700 New patented capacitive touch sense True capacitance-to-digital converter Robust and responsive Easy to use High performance MCU 25 MHz 8051 CPUBest in class ADC16 kB flash32 B data-EEPROM 54 multi-function GPIO 3User configured as digital or analogDigital crossbar assigns pinsUp to 32 capacitive touch sense inputsAvailable in TQFP64, TQFP48, andQFN48 (7x7 mm) packages
C8051F700 Product Family 322515kB322516kB-Part GQSerial rt I/OPins54UART, I2C, SPI432%CapTouchSenseY51254UART, I2C, SPI432%Y-51254UART, I2C, 51254UART, I2C, SPI432%Y-1QFP64C8051F704-GQ2515kB3251239UART, I2C, T, I2C, T, I2C, SPI432%Y-1QFP48C8051F705-GM2515kB3251239UART, I2C, SPI432%Y-1QFN48C8051F706-GQ2516kB-51239UART, I2C, , I2C, , I2C, SPI432%Y-1QFP48C8051F707-GM2516kB-51239UART, I2C, SPI432%Y-1QFN48C8051F708-GQ258kB3251254UART, I2C, SPI432%Y10-BitC8051F709-GQ258kB3251254UART, I2C, 1254UART, I2C, SPI432%Y10-BitC8051F711-GQ258kB-51254UART, I2C, SPI432%Y-C8051F712-GQ258kB3251239UART, I2C, SPI432%Y10-BitYC8051F712-GM258kB3251239UART, I2C, SPI432%Y10-BitYC8051F713-GQ258kB3251239UART, I2C, SPI432%Y-1QFP48C8051F713-GM258kB3251239UART, I2C, kB-51239UART, I2C, SPI432%Y10-BitYY1QFP48C8051F714-GM258kB-51239UART, I2C, SPI432%Y10-BitYY1QFN48C8051F715-GQ258kB-51239UART, I2C, SPI432%Y-1QFP48C8051F715-GM258kB-51239UART, I2C, SPI432%Y-1QFN48 24 unique part numbers 41Choice of flash sizeCan select EEPROM (in larger flash size, EEPROM is traded for 1 kB flash)ADC or no-ADCCapacitive touch sense option
Serial Peripheral Interface (SPI)
SPI Overview Serial Peripheral Interface (SPI) Master/Slave operationFull duplex or single wire operationProgrammable transmit bit ratesDouble veMOSID7D7D0D0
Synchronous Serial Communication Serial communication implies sending data bit by bit over a single wire Synchronous serial requires the clock signal to be transmitted from the sourcealong with the data Data rate for the link must be the same for the transmitter and the receiverSynchronous SerialData InD0D1D2D3D4D5D6D7Data OutD0D1D2D3D4D5D6D7CLKLatch data on rising edges7Output data on falling edges
SPI Configurations Multi-master Single master with single slave Single master with several slavesMulti-masterSingle master/multipleslaves8Single master/single slave
SPI Interface Application Example Need a solution that provides the capability to download the FPGA configurationfile MCU provides the bridge between a host application that has the configuration MCU can retrieve configuration file from on board serial flash MCU can provide additional functionality to the FPGA after configuration USB 2 UART FPGAConfigurationinterfaceNSSMCULogicExample SPI Application – FPGA configuration interface9
Silicon Labs Enhanced SPI Module Full duplex synchronous serialcommunications Master or slave operation Supports multiple masters or slave ona single SPI bus 3 or 4 wire operation Up to 12.5 Mbps operation in mastermode 2.5 Mbps operation in slave mode 6.25 Mbps operation in half duplexmode Programmable clock phase andpolarity settings10
SPI Programming Steps Step 1: Set port pins to digital inputs and push-pull outputs using theport I/O registers Step 2: Enable the SPI module in the crossbar using the XBAR register Step 3: Set the master or slave operating mode of the SPI peripheralusing the SPI0CFG register as well as the clock phase and polarity Step 4: Select the SPI interface as 3 or 4 wire slave or master andenable the SPI peripheral Step 5: Set the SPI clock speed using the SPI0CKR register Step 6: Enable the interrupts11
Digital I/O Pins All port pins can be used for digital I/O Port pin configured as digital using PxMDIN register bits set to a ‘1’ The output mode is selected to be push-pull using the PxMDOUT bits set to a ‘1’12PxMDINPxMDOUTPxDescription100Open drain low101Open drain high/digital Input110Push Pull: pin driven Low111Push Pull: pin driven High
Crossbar Pin Assignment Using Config WizardEnable crossbar (XBAR1)Enable SPI0 to thecrossbar (XBAR0)Generated Code SPI0 has the second highest crossbar priority and is assigned to P0.0through P0.3 when enabled XBARE: enable the crossbar13
SPI Programming Steps Step 1: Set port pins to digital inputs and push-pull outputs using theport I/O registers Step 2: Enable the SPI module in the crossbar using the XBAR register Step 3: Set the master or slave operating mode of the SPI peripheralusing the SPI0CFG register as well as the clock phase and polarity. Step 4: Select the SPI interface as 3 or 4 wire slave or master andenable the SPI peripheral Step 5: Set the SPI clock speed using the SPI0CKR register Step 6: Enable the interrupts14
Clock Polarity and Phase Four configurations of clock polarity and phase controlled by the SPI0CFGregister Clock phase determines the clock edge used to latch the data Clock polarity selects between an active high or active low clock Master and slave devices must be configured to use the same clock polarity andphase settingsClock polarity15Clock phase
Slave Mode Clock Polarity and Phase Slave mode with CKPHA 0Clock phase Slave mode with CKPHA 116
SPI0 Configuration: SPI0CFG RegisterBits7NameFunctionSPIBSYSPI BusyThis bit is set to logic 1 when a SPI transfer is in progress (master or slave mode)6MSTENMaster Mode Enable0: Disable master mode. Operate in slave mode1: Enable master mode. Operate as a master5CKPHASPI0 Clock Phase0: Data centered on first edge of SCK period1: Data centered on second edge of SCK period4CKPOLSPI0 Clock Polarity0: SCK line low in idle state1: SCK line high in idle state3SLVSELSlave Selected FlagThis bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected slave.It is cleared to logic 0 when NSS is high (slave not selected). This bit does not indicate theinstantaneous value at the NSS pin, but rather a de-glitched version of the pin input.2NSSINNSS Instantaneous Pin InputThis bit mimics the instantaneous value that is present on the NSS port pin at the time thatthe register is read. This input is not de-glitched.1SRMTShift Register Empty (valid in slave mode only)This bit will be set to logic 1 when all data has been transferred in/out of the shift register,and there is no new information available to read from the transmit buffer or write to thereceive buffer. It returns to logic 0 when a data byte is transferred to the shift register fromthe transmit buffer or by a transition on SCK. SRMT 1 when in Master Mode.017RXBMTReceive Buffer Empty (valid in slave mode only)This bit will be set to logic 1 when the receive buffer has been read and contains no newinformation. If there is new information available in the receive buffer that has not beenread, this bit will return to logic 0. RXBMT 1 when in Master Mode.
SPI0 Control: SPI0CN RegisterBits7NameFunctionSPIFSPI0 Interrupt FlagThis bit is set to logic 1 by hardware at the end of a data transfer6WCOLWrite Collision FlagThis bit is set to logic 1 if a write to SPI0DAT is attempted when TXBMT is 0. When thisoccurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be written.5MODFMode Fault FlagThis bit is set to logic 1 by hardware when a master mode collision is detected (NSS is low,MSTEN 1, and NSSMD[1:0] 01)4RXOVRNReceive Overrun Flag (valid in slave mode only)This bit is set to logic 1 by hardware when the receive buffer still holds unread data from aprevious transfer and the last bit of the current transfer is shifted into the SPI0 shiftregister.3:2NSSMD[1:0]Slave Select ModeSelects between the following NSS operation modes:00: 3-Wire Slave or 3-Wire Master Mode. NSS signal is not routed to a port pin.01: 4-Wire Slave or Multi-Master Mode (Default). NSS is an input to the device1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the device andwill assume the value of NSSMD01TXBMTTransmit Buffer EmptyThis bit will be set to logic 0 when new data has been written to the transmit buffer. Whendata in the transmit buffer is transferred to the SPI shift register, this bit will be set to logic1, indicating that it is safe to write a new byte to the transmit buffer.0SPIENSPI0 Enable0: SPI disabled1: SPI enabled18
SPI Programming Steps Step 1: Set port pins to digital inputs and push-pull outputs using theport I/O registers Step 2: Enable the SPI module in the crossbar using the XBAR register Step 3: Set the master or slave operating mode of the SPI peripheralusing the SPI0CFG register as well as the clock phase and polarity Step 4: Select the SPI interface as 3 or 4 wire slave or master andenable the SPI peripheral Step 5: Set the SPI clock speed using the SPI0CKR register Step 6: Enable the interrupts19
Clock Rate Settings Master mode clock setting derived from the system clock (SYSCLK)f SCK SYSCLK2 x SPI 0CKR[7 : 0] 1 orSPI 0CKR[7 : 0] SYSCLK 12 f SCK Example: Desired SPI rate is 250 KHz System clock 24.5 MHzSPI 0CKR 24500000 12 x 250000SPI 0CKR 4820
SPI0 Code: I/O and SPI0 Configuration Step 1: Set port pins to digitalinputs and push-pull outputs usingthe port I/O registers Step 2: Enable the SPI module inthe crossbar using the XBARregister Step 3: Set the master or slaveoperating mode of the SPIperipheral using the SPI0CFGregister as well as the clock pahseand polarity Step 4: Select the SPI interface as 3 or 4 wire slave or master and enable the SPIperipheral Step 5: Set the SPI clock speed using the SPI0CKR register Step 6: Enable the interrupts21
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C8051F700 Serial Peripheral Interface (SPI) Overview. 2 . C8051F700 device features SPI operation overview SPI module overview Where to learn more. 3 Introducing The C8051F700 New patented capacitive touch sense True capacitance-to-digital converter Robust and responsive . SPI USB Configurati
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