MPC5121e Serial Peripheral Interface (SPI)
Freescale SemiconductorApplication NoteDocument Number: AN3904Rev. 0, 08/2009MPC5121e Serial PeripheralInterface (SPI)by: Pavel Bohá čikRožnov Czech System CenterCzech Republic1IntroductionThe purpose of this application note is to describe theserial peripheral interface bus controller (SPI)implemented on Freescale’s MPC5121e microcontroller.It describes how to configure and use the programmableserial controller (PSC) and PSC centralized FIFOcontroller (FIFOC) in all supported SPI modes.1.1123ObjectiveThe objective of this application note is to describe thenecessary steps needed to initialize and configure PSC inthe SPI mode at all supported modes.1.2Contents4Definition of the SPIThe Serial Peripheral Interface (SPI) protocol isasynchronous serial data standard, primarily used toallow a microprocessor to communicate with othermicroprocessors or ICs such as memories, liquid crystal Freescale Semiconductor, Inc., 2009. All rights reserved.5Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Definition of the SPI. . . . . . . . . . . . . . . . . . . . . . . . . 1Description of the SPI module . . . . . . . . . . . . . . . . . . . . . 22.1 SPI module in MPC5121e . . . . . . . . . . . . . . . . . . . . 22.2 Serial peripheral interface register list . . . . . . . . . . . 32.3 Signal description and connection scheme . . . . . . . 6Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73.1 PIN muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73.2 IPS bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83.3 MCLK frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . 83.4 Data polling, interrupts, and DMA . . . . . . . . . . . . . . 93.5 PSC and FIFOC initialization. . . . . . . . . . . . . . . . . 103.6 Interrupt initialization . . . . . . . . . . . . . . . . . . . . . . . 153.7 Direct memory access . . . . . . . . . . . . . . . . . . . . . . 17Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194.1 SPI configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 194.2 Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214.3 Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244.4 Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264.5 DMA mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Description of the SPI modulediodes (LCD), analog-to-digital converter subsystems, etc.The SPI is a very simple synchronous serial data, master/slave protocol based on four lines: Clock line (SCLK) Serial output (MOSI) Serial input (MISO) Slave select (SS)Every SPI system consists of one master and one or more slaves, where a master initiates thecommunication by asserting the SS line. When a slave device is selected, the master starts clocking out thedata through the MOSI line to the selected slave device. The master sends and receives one bit for everyclock edge. One byte can be exchanged in eight clock cycles. The master finishes communication byde-asserting the SS line.The SPI is a primitive protocol without an acknowledgement mechanism for checking received or sentdata. For safe communication, a flow control has to be implemented in the communications protocol on sa higher level.2Description of the SPI module2.1SPI module in MPC5121eThe MPC5121e PSC module in SPI mode is capable of master and slave mode as well. The MPC5121ehas a centralized FIFO controller that contains data to be transmitted plus the received data for all twelvePSC modules. FIFO is divided into twenty-four slices. For each PSC module, one Tx and one Rx FIFOspace is available. The size of each memory slice is fully user-programmable, depending on the free FIFOspace. The FIFO slice is able to allocate maximum available memory but the user has to prevent overlayof the individual slices in the memory. The available memory space for all slices together is 32b 1024(4 KB).MPC5121e Serial Peripheral Interface (SPI), Rev. 02Freescale Semiconductor
Description of the SPI rnal Memory — 4 KBPSC0 Tx FIFO gicPSC0 Rx FIFO slicePSC1 Tx FIFO slicePSC1 Rx FIFO gicPSC9 Tx FIFO slicePSC9 Rx FIFO sliceCoreConfigurationregisterIPB interfaceDMA2engineProgrammableTx/Rx clockgenerationSCLKSSMOSIMISOExternalclock sourcePSC 0.11Internal clock sourceInterface control logicFIFOCIPS busFigure 1. MPC5121e PSC and FIFOC module system interconnectionThe PSC requests new data if the Tx shift register is empty or writes Rx data to FIFOC if the Rx shiftregister is full. This communication is independent of external interrupt or request signals. To make surethe transfer is successful and avoid an overrun/underrun event, both transceiver and receiver must bealways enabled and the core/DMA must make sure that the data slices or Tx or Rx shift registers neverbecome full/empty.2.2Serial peripheral interface register listThe PSC and FIFOC available in the MPC5121e use these registers for self-configuration and forcommunication with the connected device. The register address is calculated as the base address for therelevant PSC plus the offset value. Table 1 shows the register list related to the PSC and Table 2 shows theregister list related to the FIFOC.For further information and detail on these registers see these chapters in Freescale documentMPC5121ERM, MPC5121e Microcontroller Reference Manual: Chapter 30, “Programmable Serial Controller” Chapter 31, “PSC Centralized FIFO Controller”MPC5121e Serial Peripheral Interface (SPI), Rev. 0Freescale Semiconductor3
Description of the SPI moduleTable 1. Register list — PSCDressRegister NameDescriptionBase Address 00Mode Register 1 (MR1)Controls configurationBase Address 00Mode Register 2 (MR2)Controls configurationBase Address 04Status Register (SR)Status of PSCBase Address 04Clock Select Register (CSR)DefaultBase Address 08Command Register (CR)Provides commands to the PSCBase Address 0CRx Buffer Register (RB)Reads data directly from the Rx shift registerBase Address 0CTx Buffer Register (TB)Writes data directly from the Tx shift registerBase Address 10Input Port Change Register (IPCR)DefaultBase Address 10Auxiliary Control Register (ACR)DefaultBase Address 14Interrupt Status Register (ISR)Status for all potential interrupt sourcesBase Address 14Interrupt Mask Register (IMR)Selects corresponding bits in the ISR thatcause an interruptBase Address 18Counter Timer Upper Register (CTUR) Together with CTLR affects delay after transferBase Address 1CCounter Timer Lower Register (CTLR) Together with CTUR affects delay aftertransferBase Address 20Codec Clock Register (CCR)Define DSCKLL delay and SPI baud rateBase Address 24AC97 Slots Register (AC97Slots)DefaultBase Address 28AC97 Command Register (AC97CMD) DefaultBase Address 2CAC97 Status Data Register(AC97Data)DefaultBase Address 30ReservedDefaultBase Address 34Input Port Register (IP)DefaultBase Address 38Output Port 1 Bit Set (OP1)DefaultBase Address 3COutput Port 0 Bit Set (OP0)DefaultBase Address 40Serial Interface Control Register(SICR)Sets the main operation modeMPC5121e Serial Peripheral Interface (SPI), Rev. 04Freescale Semiconductor
Description of the SPI moduleTable 2. Register list — FIFOCAddressRegister Name11 8BaseAddress 0x0n(n PSCnumber)Description7 00x80Command register for PSCn Tx slice —PSCn Tx CMDProvides commands to the FIFOC0x84Alarm level for PSCn Tx slice —PSCn Tx ALARMDefines alarm level0x88Status register for PSCn Tx slice —PSCn Tx SRShows internal status of the FIFO slice0x8CInterrupt status register for PSCn Tx slice — Status of all potential interruptsPSCn Tx ISR0x90Interrupt mask register for PSCn Tx slice — Selects corresponding bits in the ISR thatPSCn Tx IMRcause an interrupt0x94FIFO count for PSCn Tx slice —PSCn Tx COUNTNumber of bytes in the FIFO0x98FIFO pointer for PSCn Tx slice —PSCn Tx POINTERReads or modifies pointer in the FIFOslice0x9CFIFO size register for PSCn Tx slice —PSCn Tx SIZESets start address and size of the FIFOslice0xBCFIFO data register for PSCn Tx slice —PSCn Tx DATAFIFO data register0xC0Command register for PSCn Rx slice —PSCn Rx CMDProvides commands to the FIFOC0xC4Alarm level for PSCn Rx slice —PSCn Rx ALARMDefines alarm level0xC8Status register for PSCn Rx slice —PSCn Rx STATShows internal status of the FIFO slice0xCCInterrupt status register for PSCn Rx slice — Status of all potential interruptsPSCn Rx INTSTAT0xD0Interrupt mask register for PSCn Rx slice — Selects corresponding bits in the ISR thatPSCn Rx INTMASKcause an interrupt0xD4FIFO count for PSCn Rx slice —PSCn Rx COUNTNumber of bytes in the FIFO0xD8FIFO pointer for PSCn Rx slice —PSCn Rx POINTERReads or modifies pointer in the FIFOslice0xDCFIFO size register for PSCn Rx slice —PSCn Rx SIZESets start address and size of the FIFOslice0xFCFIFO data register for PSCn Rx slice —PSCn Rx DATAFIFO data registerBase Address 0xF00 FIFO commandDefaultBase Address 0xF04 FIFO interrupt statusShows all PSCs with currently pendinginterruptsMPC5121e Serial Peripheral Interface (SPI), Rev. 0Freescale Semiconductor5
Description of the SPI moduleTable 2. Register list — FIFOC (continued)AddressRegister Name11 8Description7 0Base Address 0xF08 FIFO DMA requestShows all PSCs with currently pendingrequestsBase Address 0xF0C FIFO AXE requestDefaultBase Address 0xF10 FIFO debugDefault2.3Signal description and connection schemeThe serial peripheral interface bus has four external lines, described in Table 3. Figure 2 shows how theslave device is connected to the master in the single master, single slave SPI implementation. Figure 3shows single master, multiple slave SPI implementations. Multiple slave SPI implementation is notsupported by the MPC5121e without additional external hardware.Table 3. Signal descriptionSignalDescriptionSCLKSerial clock signal with direction from master to slave device.MOSI/SIMOMaster-out/slave-in signal for data transmission from master to slave in 8-bit, 12-bit, 16-bit,20-bit, 24-bit, or 32-bit width (output from master).MISO/SOMIMaster-in/slave-out signal for data transmission from slave to master in 8-bit, 12-bit, 16-bit,20-bit, 24-bit, or 32-bit width (output from slave).SSSlave select signal, initiated by master to select slave device.SCLKMOSIMasterMISOSlaveSSFigure 2. Single master, single slave SPI implementationMPC5121e Serial Peripheral Interface (SPI), Rev. 06Freescale Semiconductor
ve 1SSSS2SS3SCLKMOSIMISOSlave 2SSSCLKMOSIMISOSlave 3SSFigure 3. Multiple slave SPI implementations3InitializationTo assure proper PSC-SPI module functionality, each module must be initialized before usage. Wheninitializing the PSC-SPI module, the user must obey these instructions.3.1PIN muxingExternal signals of the MPC5121e are grouped (for a pinout diagram showing pin numbers and a listingof all the electrical and mechanical specifications, refer to Freescale document MPC5121e, MPC5121eData Sheet, at www.freescale.com). Any functionality which is not the primary function is multiplexed.For more detail see Freescale document MPC5121ERM, MPC5121e Microcontroller Reference Manual,chapter 3, “Signal Descriptions.”When the user wishes to use MPC5121e and its PSCn pins, it is necessary to set up I/O control registers.The I/O control block controls the functional muxing and configuration of the pads. Configurableparameters include slew rate, Schmitt-trigger input, internal pulldown/pullup, and PCI hold timing.For proper initialization it is necessary to set up I/O control GP and PAD registers.For further information on how to set up these registers see these chapters in Freescale documentMPC5121ERM, MPC5121e Microcontroller Reference Manual: Chapter 3, “Signal Descriptions” Chapter 22, “IO Control”MPC5121e Serial Peripheral Interface (SPI), Rev. 0Freescale Semiconductor7
Initialization3.2IPS busWhen setting up a system with the MPC5121e, proper clocking must be assured. One of the importantclock sources is the IPS bus clock (IPS CLKFrequency). The IPS bus clock is used as a source for the clockgeneration unit CSR and CT registers. This clock can be as high as 83 MHz.3.3MCLK frequencyEach PSC can select from multiple clock sources. A single clock input is provided that allows thePSC MCLK IN to be used as a master clock reference by all PSCs. The MCLK frequency source is themain clock source which is used as the peripheral clock source. Figure 4 shows the circuit which isreplicated for each PSC individually.Many peripheral clocks may be disabled to reduce power consumption in the system clock control register(SCCR1, SCCR2). If the user wishes to operate PSC in the SPI mode, the user must enable clocks for therelated PSC and FIFOC in the SCCR1 register.When PSC and FIFOC clocks are enabled, it is necessary to set up the PSCn clock control (PnCCR)register, which controls: PSCn MCLK divider ratio (PSCn MCLK DIV) — the divider determines the FMCLK Outfrequency, which is used for example for calculating the SPI clock (SCLK) frequency. This valuecan only be changed when the value of MCLK EN 0. Two examples of the FMCLK Out arementioned in Equation 1 and Equation 4. PSCn MCLK divider enable (MCLK0 EN) — enable/disable PSCn divider PSCn MCLK divider source (PSCn MCLK 0 SRC) — define MCLK divider source (SYS CLK,REF CLK, PSC MCLK IN, SPDIF TxCLK) PSCn MCLK source (PSCn MCLK 1 SRC) — define MCLK source (MCLK DIV,SPDIF RxCLK)PnCCR register sets all parameters shown in Figure 4.MCLK ENSYS CLKMCLK DIVREF CLKClockgatePSC MCLK INMCLK DIVSPDIF RXCLKSPDIF TXCLKPSC MCLK OUTMCLK 1 SRCMCLK 0 SRCFigure 4. PSC (MCLK) clock generationEquation 1 and Equation 2 show the calculation of a 1 MHz SCLK frequency derived from the SYS CLKfrequency.MPC5121e Serial Peripheral Interface (SPI), Rev. 08Freescale Semiconductor
Initialization400 MHzSYS CLKPSC MCLK OUT -------------------------------------- ----------------------- 66.67 MHz IPS CLK (83 MHz)5 1MCLK DIV 1Eqn. 1PSC MCLK OUT 66.67 MHzSCLK Frequency --------------------------------------------- --------------------------- 0.995 MHzBCLK DIV 166 1Eqn. 2CAUTIONIPS frequency must be greater than or equal to PSC MCLK OUTfrequency.The maximum SCLK frequency for SYS CLK input frequency can be easily calculated as 20 MHz — seeEquation 3 and Equation 4.SYS CLK400MHzPSC MCLK OUT -------------------------------------- --------------------- 80MHz IPS CLK ( 83MHz )MCLK DIV 14 1PSC MCLK OUT80MHzSCLK Frequency --------------------------------------------- ------------------ 20MHzBCLK DIV 13 1Eqn. 3Eqn. 4NOTEThe PSC:CCR register contains BCLKDiv (bit clock divider) information.Note that BCLKDiv bytes in CCR register are swapped.NOTEMinimum BCLKDiv for SPI mode equals 3.3.4Data polling, interrupts, and DMAThe user can chose how to get the data from the memory to the FIFOC slice or how to put data in thememory from the FIFOC slice. The user can also choose between active polling, interrupts, and DMA. Themain differences, advantages, and disadvantages are: Active polling mode — core periodically checks status of Tx and Rx FIFO slices and writes datato Tx FIFO slice or reads data from Rx FIFO slice.Disadvantages — core loading, FIFO slice status does not show the actual status of the serial shiftregisters due to a small delay (a few processor ticks). It can happen that data is received in the Rxshift register and Rx FIFO slice shows as empty. This can cause small difficulties at the end of thecommunication. Interrupt mode — lower core loading compared to active polling mode. The core is not used forperiodical status checks of the Tx and Rx FIFO slices, but it is used for handling interrupt events(sending and receiving data). The number of interrupts depends on the user application. Usage ofFIFOC alarm level interrupts can decrease the number of requested interrupts. DMA mode — the lowest core loading compared with active polling or interrupt mode. DMA isused for transfer data (array) from memory to the FIFO slice. The DMA engine takes care of theFIFOC status as well. The core is used to start Rx and Tx DMA tasks and to handle interruptssignaling the end of transfer.MPC5121e Serial Peripheral Interface (SPI), Rev. 0Freescale Semiconductor9
InitializationDisadvantages — end of frame mode is not supported in DMA mode. The last data packet has tobe sent using polling or interrupt mode. All data has to be pre-prepared in the array/buffer beforethe DMA transfer starts.The following sections show how to initialize each one of these modes.3.5PSC and FIFOC initializationThe MPC5121e has a centralized FIFO controller that contains data to be transmitted plus received datafor all twelve PSC modules. The FIFO is divided into twenty-four slices. For each PSC module, one Txand one Rx FIFO space is available. The size of each memory slice is fully user-programmable, dependingon the free FIFO space. The FIFO slice is able to allocate maximum available memory but the user has toprevent overlay of the individual slices in the memory. The available memory space for all slices togetheris 32b 1024 (4 KB).If the user wishes to transfer data with the use of the SPI, then the programmable serial controller must beinitialized in SPI mode and the FIFOC must be initialized as well.3.5.1PSC initializationSeveral steps are necessary for proper initialization of the PSC module in the SPI mode. These steps haveto be done in the proper sequence as shown in Figure 5 (master) and Figure 6 (slave).1. Disable receiver and transmitter — disable the Tx and Rx part in the PSC-CMD configurationregister, if the PSC was enabled earlier.2. Set the main operation mode — set the main operation mode in the Serial Interface ControlRegister (SICR). For details see Table 4.3. Define the delay before SCLK (DSCKLL) (not required for slave mode) — when the PSC is in SPImode (SICR[SPI] 1), the FrameSyncDiv divider is used to determine the length of time the PSCdelays after SS goes low/active before the first SCKL transition of the serial transfer. The delaybefore SCKL depends on the connected slave device. The delay before SCKL (DSCKLL) can forexample be set to 0.5 μs. Equation 5 determines the actual delay before SCKL and an example ofthe calculation as well.32 1FrameSyncDiv 1DSCKL Delay ------------------------------------------------- ------------------------6- 0.5 μ sMCLK Frequency66.6 10Eqn. 54. Define the divider for the bit clock generation (not required for slave mode) — in SPI master mode,the bit clock frequency BCLK (SCKL) is generated by dividing the MCLK frequency. In additionto the BCLK generation, the DSCLK delay and the DTL delay must be defined. SCKL is generatedinternally by dividing the MCLK frequency, as determined by Equation 6. This equation containsthe example for SCKLFrequency 1 MHz.6MCLK Frequency66.6 10SCK Frequency ------------------------------------- ------------------------- 0.99MHz66 1BCLKDiv 1Eqn. 6MPC5121e Serial Peripheral Interface (SPI), Rev. 010Freescale Semiconductor
InitializationNOTEPSC:CCR register contains BCLKDiv (bit clock divider) information. Notethat BCLKDiv bytes in the CCR register are swapped.5. Set delay after transfer (not required for slave mode) — the delay between consecutive transfers iscreated by dividing the IPS CLK clock frequency. The delay after transfer is usually set to 2 μs.Equation 7 determines the actual delay after transfer.CT 23132 2DTL ------------------------------------------- --------------------------------------
MPC5121e Serial Peripheral Interface (SPI), Rev. 0 Description of the SPI module 2 Freescale Semiconductor diodes (LCD), analog-to-digital converter subsystems, etc. The SPI is a very simple synchronous serial data, master/slave protocol based on four lines:
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