Fall 2008 EE 410/510: Microfabrication And Semiconductor .

Fall 2008 EE 410/510:Microfabrication and Semiconductor ProcessesM W 12:45 PM – 2:20 PMEB 239 Engineering Bldg.Instructor: John D. Williams, Ph.D.Assistant Professor of Electrical and Computer EngineeringAssociate Director of the Nano and Micro Devices CenterUniversity of Alabama in Huntsville406 Optics BuildingHuntsville, AL 35899Phone: (256) 824-2898Fax: (256) 824-2898email: williams@eng.uah.eduTables and Charts taken from Cambell, Science and Engineering of Microelectronic Fabrication, Oxford 2001Implantation images taken from Axcelis Corporation.

Ion ImplantationAxcelis Technologies, Inc.Penn State Graphical Description of Ion implant/Online chapter of ion implantation process ger/node20.htmlIon Implantation .edu/cleanroom/rangestraggle.phtmlFreeware for 1-D implant ndex.html

Arc Chamber–Ion source: Arc Chamber Feed gas of implant species using mass flow controllers–– BF3, AsH3, PH3 for SiSiH4 and H2 for GaAsSolid sources can be heated to vapor form and controlled via a shutter if neededMolecules flow past a hot charged filament in a magnetic field to produce ionization.Positive ions are accelerated and exit the chamber through a slit, resulting in an ion beam a fewmm by 1 cm accross

Ion Separation Ions are separated by atomic massusing a large magnetic fieldThe field bends the ion beam by anangle φ which does NOT have to be 90oIn fact, it is possible to conceive of animplanter with multiple exit slits allowingfor mass production of devicesimplanted with different atomic massesVextFrom extractiongridMv 2 qvBrBxv rφr LM1M2D D2E2 qVext MMMv 1M 2 VextqB Bq1 δMr2 ML 1cosφsinφ r

Beam Steering After separationIons are accelerated by RF bias fieldsMagnetic lenses can be used to focusthe beamElectronic biasing plates are used tosteer and scan the beam over a limitedrangeBeam exits through a window andimplants high energy ions ontosubstrateSubstrate can also be scanned acrossthe beam as needed

Ion Penetration Where Se and Sn are the energylosses due to electronic and nuclearstopping potentialsElectronic stopping potential due to scatteringof ions from electron within the latticedEZi Z t ( M i M t )Se 32/32/3dx eM i M t Zi Z t3/ 2()Nuclear stopping potential due toscattering from nuclei in the latticeSno 2.8 10 15eV / cm2 (Z Zi2/ 3 Zt)2 / 3 3/ 2Zi Zt MiZ1/ 3 Mi MtEE energy of the implanted ions (eV)Z charge number of protons in the atomM atomic massi incident iont target material

Implantation Range Penetration is estimated using rangeand standard deviation equationsRp00dEdERp dx dE/ dx Eo Sn SeEo02 MM ΔRp Rp i t 3 Mi Mt Impurity concentration as a functionof depth isφ ( x R ) /(2ΔRN(x) e2πΔRp2P2p )

Implantation Range

Implantation Range

Channeling Effects Channeling is a lack of scattering dueto geometrical orientation of the targetmaterial with respect to the incidentbeamOccurs when ion velocity is parallel toa major crystal orientationOnce in a channel, the ion willcontinue in that direction making manyglancing internal collisions that areearly elastic until coming to rest or dechannels due to a crystal defect orimpurityEffect is characterized by a criticalangleΨ 9.73oZi ZtEo d

Implantation ApplicationsMedium Dose ApplicationsHigh Dose ApplicationsBuried channel doping0.5 keV to 750 keV35-65 nm ULSI0.2 keV to 80 keVhttp://www.axcelis.com/

Implantation ApplicationsHigh Energy Applications10 keV to 4 MeVChannel Engineering andTransistor isolationhttp://www.axcelis.com/

Quantum Computing with SingleAtom Implantation Single atom ionimplantation can beused to producequantum computersDoping of one atomscreates a singleelectron that exist ineither one or twodifferent quantumstates (double well)The quantuminformation packet iscalled a (q-bit)Surface electrodes Sand B control the stateSingle electrontransistors (SETs)detect charge transferbetween the two donorsMicroelectronic Engineering Volumes 78-79,March 2005, Pages 279-286

Buried Dielectrics SOI wafers formed by Ionimplantation of O2 into Siliconfollowed by annealing150 – 300 keV O does to about2*1018cm-2Very long implantation timeOften done on axis to takeadvantage of channeling effectsGenerates a nearly amorphouslayer of 30% Si / 60% O2To reduce damage, wafers mustbe heated to at least 400oC duringimplantAnneals are performed at 13001400oC for several hours underan deposited oxide capImplanters designed for SIMOXoperate at 100mA with metalliccontamination held below 1011cm-2and pinhole density less than0.2cm2. Thickness uniformity isapprox. 50 Ang over 6 inH.W. Lam, “SIMOX SOI fo Integrated Circuit Fabrication,” IEEE Circuits and Devices 3:6 (1987).

Rapid Thermal Annealing Method for annealing materials attemperatures up to 1200oC for very shortperiods of timeTypical ramp rates are 30 secProcess times range from 2-600 secAdvantages– Extremely fast technique– Single wafer processing produces bestuniformity– Minimizes redistribution of dopants– Cold walls allow multiple processes tooccur without contamination– Photochemistry can be exploitedDisadvantages– Absolute temperatures are almost neverknown– Nonthermal-equilibrium process makesmodeling and predicting difficult– Uniform heating is more critical thantraditional thermal processing Ramp rates Internal stresses

Rapid Thermal Annealing Types of RTP– Adiabatic: excimer laser heats surface– Thermal Flux: rastered electron beam– Isothermal: Optical illuminationMeasurement Devices– Pyrometry: measures thermal light intensity– Acoustic: measures velocity of sound in the chamber as a linear function of temperature– Thermocouples imbedded in SiC, Si, or Graphite susceptor plate

Feed gas of implant species using mass flow controllers – BF 3, AsH 3, PH 3 for Si – SiH 4 and H 2 for GaAs Solid sources can be heated to vapor form and controlled via a shutter if needed Molecules flow past a hot ch