CMOS Image Sensors With Self-Power Generation Capability
PAPER IDENTIFICATION NUMBER - 19011CMOS Image Sensors withSelf-Power Generation CapabilityAlexander Fish, Shy Hamami and Orly Yadid-Pecht, Senior Member, IEEEAbstract— Considerations for CMOS image sensors with selfpower generation capability design are presented. Design ofCMOS imagers, utilizing Self-Powered Sensors (SPS) is a newapproach for ultra low-power CMOS Active Pixel Sensors (APS)implementations. The SPS architecture allows generation ofelectric power by employing a light sensitive device, located onthe same silicon die with an APS and thus reduces powerdissipation from the conventional power supply. This makesimage sensors using the SPS architecture very useful inapplications where ultra low-power is the main demand. Adetailed analysis of the SPS structure is carried out, with respectto power dissipation requirements, sensor area and powergeneration efficiency, showing advantages and drawbacks of theproposed concept.An illustrative example of CMOS imager with Self-Powergeneration capability in 0.18μm standard CMOS technology isdiscussed. Measurements from a test chip, implemented in0.18μm CMOS process, are presented.Index Terms—Active Pixel Sensor (APS), Self-Powered Sensor(SPS), Power Generated Photo Diode (PGPd), low-power sensor.I. INTRODUCTIONCMOS image sensors are very attractive in the field ofportable battery-operated devices. CMOS imagers offersignificant advantages in terms of low-cost, low-power, lowvoltage and monolithic integration. Current state of the art CMOSimagers allow integration of all functions required for timing,exposure control, color processing, image enhancement, imagecompression and ADC on the same die, while dissipating onlytens of mW of power. It is expected that the next generation ofimage sensors will consume less than 1mW to support the demandfor continuous power reduction in mobile devices [1]-[3]. Thistarget is usually achieved by technology scaling and aggressivesupply voltage reduction. However, low-voltage power supplyhas an enormous impact on the imager performance, mainly dueto dynamic range and signal-to-noise ratio reduction.A comprehensive study on low-power low-voltage CMOSimage sensors has been performed in the last years [1]-[14]. Anumber of methodologies were presented to reduce imager powerManuscript received Mar 9, 2004.A. Fish is with the VLSI Systems Center, POB 653, Beer-Sheva 84105,Israel (e-mail: afish@ee.bgu.ac.il).V. Milrud is with the VLSI Systems Center, POB 653, Beer-Sheva 84105,Israel (e-mail: milrud@ee.bgu.ac.il).O. Yadid-Pecht is with VLSI Systems Center, POB 653, Beer-Sheva84105, Israel (phone: 972-8646-1512; fax: 972-8647-7620; e-mail:oyp@ee.bgu.ac.il) and with Dept of Electrical and Computer Engineering,University of Calgary, Alberta, Canada T2N1N4.dissipation while still achieving good image quality. In 2000 anCMOS Active Pixel Sensor (APS), fabricated in 0.35μm CMOStechnology and operating at a supply voltage of only 1.2 V hasbeen demonstrated by Cho [3]. In this work the bootstrappingtechnique was used to increase the dynamic range of the sensor.Another approach to low-voltage APS design was presented in[4],[5], where a PMOS is used as the reset transistor inside thepixel to eliminate threshold voltage drop. Low-power 1V voltagesupply complementary APS architecture that removes thethreshold voltage influence on the available output swing waspresented by Xu in 2002 [12]. An advanced APS imager usinglow-power sensor design methodology was presented in 2002[13]. In [14] an ultra-low power wide dynamic range snapshotimager with dual voltage supplies was presented. Current modepixel architectures were also used to reduce power dissipation[15].This paper presents considerations for CMOS image sensorswith self-power generation capability design, providing boththeoretical analysis and measurements from a test chip. Design ofCMOS imagers, utilizing Self-Powered Sensors (SPS) is a newapproach for ultra low-power CMOS Active Pixel Sensors (APS)implementations [16]. The SPS concept is based on the sensorself-power generation using an additional photo sense element,located on the same silicon die with APS. The SPS pixelarchitecture allows employing the energy of incident light toproduce power for the APS reset operation and in-pixel amplifier,hence reducing the sensor power dissipation from the regularpower supply. One of the well known methods, having a similarconcept of power production is a solar cell. However, theadvantage of the proposed SPS technique over solar cells is that itcan be easily integrated with a CMOS imager in a standardfabrication process.Section II describes the SPS architecture and explains itsprinciples of operation. A detailed analysis with reference topower dissipation requirements, sensor area and power generationefficiency is presented in Section III. Section IV shows anillustrative example of an SPS structure in 0.18um standardCMOS technology. Test chip design and measurements from theprototype, fabricated in a standard 0.18μm CMOS technology aredescribed in Section V. Conclusion and future research areoutlined in Section VI.II. SPS CONCEPT, ARCHITECTURE AND PRINCIPLE OFOPERATIONA. SPS conceptFig.1 shows an example of a possible implementation of thebasic SPS structure in conjunction with a 3-T photodiode CMOSAPS employing a PMOS reset transistor [4],[5]. This structureimplements the basic APS elements and Power Generation
PAPER IDENTIFICATION NUMBER - 1901Photodiodes (PGPd), used for self-power generation. ThesePGPds are inverse-biased using a conventional power supply(VDD). According to this proposed design, the VDD' line iscommon to all pixels and is connected to the PGPd elements,which can be located inside each pixel or alternatively, in thesensor periphery. The SPS operates as follows: under illuminationconditions, the voltage at node VDD' is increased to VDD by thephotocurrent which discharges the PGPd space-chargecapacitance. This photo-electric process is comparable to theregular photodiode (Pd) operation, where the voltage across thejunction decays proportionally to the illumination level. Note, thePGPd is connected in an open-circuit configuration, as long as thereset and the RS transistors are off, which is similar to the Pdintegration mode. The photo-electric charge, induced by PGPdelement is used for Pd reset during the reset stage and for readoutoperation, as will be described in sub-section B.Fig. 2 depicts a possible SPS implementation in a standard nwell CMOS process. The PGPd element is formed by the p Nwell junction, while the Pd is implemented by the n -Psubjunction.Generated power supply - VDD’To other pixelsResetSF2Figure 3. SPS general architecture.From a power dissipation point of view, the SPS operation,with reference to Fig. 3 and Fig. 4, can be divided into two mainphases, (a) Enable transistor is on and (b) Enable transistor is off("power-off" phase). The first phase (Treadout in Fig. 4) consists ofthe Pd reset stage, the reset value readout stage (SHR) and thephoto-generated signal readout stage (SHS). During this stage, thecircuit is powered by the PGPd elements. However, the phase (b)can be considered as non-power consumer phase, where the PGPdelement can be charged by the photo-electric charge in opencircuit configuration.RSPGPdPdVDDCol BusFigure 1. Possible implementation of SPS.Figure 4. SPS timing waveformFigure 2. Possible SPS implementation in a standard N-wellCMOS process.As previously noted, the PGPd elements can be located insideeach pixel (as shown in Fig. 2), which has an advantage ofrobustness in scene contrast because it is able to receive sceneilluminance averagely by the overall focal plane. However, thisapproach degrades the sensor fill factor and spatial resolution.Thus, locating PGPd elements in the array periphery can bepreferred in some cases.B. SPS architecture and principle of operationFig. 3 shows the general architecture of the proposed SPSstructure, operating in the rolling shutter readout mode [17]. Thestructure consists of (a) a single SPS pixel, as presented in Fig. 1,(b) VLN transistor, which acts as a current source, (c) Enabletransistor for leakage current reduction due to the stack effect[18], (d) two analog switches for signal and reset signalsselection, (e) two capacitors for reset and signal voltage storage,CR and CS, respectively.In the rolling readout technique the Correlated DoubleSampling (CDS) circuit is usually used to reduce the FixedPattern Noise (FPN) by subtracting the signal pixel value from thereset value of the next frame. Because CDS is not truly correlatedwithout frame memory, the read noise is limited not only by thereset noise on the photodiode, but also by the voltage variationson the PGPd elements (VDD'). The VDD' variations are due tocharge pumping during Treadout phase and illumination leveldeviations between two sequential readouts. The above flaws canbe overcome by the use of truly CDS, which requires 4-Ttransistors APS architecture [17],[19].As mentioned above, the VDD' voltage depends on illuminationlevels. Thus, the SPS reliability can be undermined in lowillumination levels. To overcome this possible problem, a backupcircuit should be used. Fig. 5 shows a possible implementation ofsuch a type of a circuit.The backup circuit operates as follows: before each Treadoutphase, the comparator samples the VDD' voltage and compares itwith appropriate reference voltage Vref. In case where the VDD' Vref, meaning that PGPd element voltage did not recover duringthe "power-off" phase, the PMOS transistor is on and VDD' node
PAPER IDENTIFICATION NUMBER - 19013where Tframe is the frame time and Nrow is the number of rows inthe APS array.For proper SPS operation, ΔQTOT, required during the Treadoutphase, should be smaller than Qgen. Equating (4) and (6) leads tothe expression for PGPd required area, A:A ΔQVLN ΔQC(7)q Φ η (T frame / N row Treadout )The drop in the VDD' during the Treadout phase is given by:Figure 5. Possible implementation of a backup circuit.Vdrop is charged to VDD. The Vref voltage is defined as Vref VDD- ΔVmax,where ΔVmax is the maximum allowed voltage drop in powersupply, which ensures a proper operation of APS. A brief ΔVmaxdetermination is discussed in the next Section. Note, thecomparator used in this backup circuit should be power efficientand is activated only for very small periods of time employing theenable input.A. APS Power Dissipation PatternAPS power dissipation during the Treadout phase can be dividedinto the following components: (a) the power dissipated by theVLN transistor, (b) the power dissipated to charge the storagecapacitors CS and CR and (c) the power dissipated through resetoperation of the pixel photodiode. Equations (1) - (3) describe thecharge pumping of components (a) to (c), respectively.ΔQVLN Treadout N col I LN(1)ΔQC ( CS CR ) Vswing N col(2)ΔQreset C pd Vswing N col(3)where Ncol is the number of pixels in the row, ILN is the currentflowing through the VLN transistor, Vswing is the maximum swingvalue on the CS and CR capacitor, Cpd is the pixel photodiodecapacitance. The predominant power consumers are the currentsource ILN and the CS and CR capacitors charging, while the ΔQresetcomponent can be neglected, resulting in:(4)where ΔQTOT is the total charge dissipated during the Treadoutphase.B. PGPd power generation efficiencyPower generation efficiency of SPS structure is defined by thephoto-electric conversion efficiency of the PGPd element. Thephotocurrent, produced in PGPd may be considered as a currentsource and is given as follows:I ph q Φ η A(5)where q is the electron charge, Φ is the photon flux, η is thequantum efficiency and A is the photosensitive area.The total photo-electric charge, generated in the PGPd elementcan be approximated as:Qgen I ph Tgen I ph (T frame / N row Treadout )(8)A C j (VDD ')where Cj(VDD') is the space-charge capacitance of the PGPdelements and in case of abrupt junction is defined as:C j (VDD ') qε sNAND2 (Vbi [VDD ' VDD ]) N A N D(9)where εs is the permittivity of silicon, Vbi is the built-in voltage,ND and ND are the acceptors and donors concentrations,respectively.III. SPS ANALYSIS AND CONSTRAINTSΔQTOT ΔQVLN ΔQCΔQVLN ΔQC(6)Assuming the equality in (7), the equation (8) is reduced to:Vdrop q Φ η (T frame / N row Treadout )(10)C j (VDD ') J ph(Tframe/ N row Treadout )C j (VDD ')where Jph is the photocurrent density.As mentioned in Section II (see Fig. 2), the PGPd element isformed by the p -Nwell junction. In a standard CMOS process,this structure provides relatively high depletion capacitance due tothe high ND concentration, resulting in smaller Vdrop. Note, thatthere is no straightforward relation between Vdrop and ΔVmax.While Vdrop is defined by (8), ΔVmax is determined by theacceptable output swing of the APS.IV. ILLUSTRATIVE EXAMPLE IN 0.18µM PROCESSAn illustrative example of the SPS structure in 0.18μm process isdepicted herein, based on the analysis presented in the previousSection. The QCIF APS array (176x120) operating at 30 framesper second at 1.8V is assumed. The parameter values listed in thissub-section are typical to 0.18μm process and will be utilized toillustrate the relevant expressions.The total charge ΔQTOT dissipated during the Treadout phase isobtained using (4) and is given by:ΔQtot ΔQC ΔQVLN 96 p Col 23 p Col 120 p Col (11)assuming Treadout 250nsec, ILN 0.75uA, where CS CR 0.4pFand Vswing 1V.The photocurrent density is calculated using (5):J ph q Φ η 2 μ A / cm2 (12)
PAPER IDENTIFICATION NUMBER - 1901where η 0.3 for typical p /n-well junction and Φ 4x1013[ph/cm2sec]. Note, room light flux and clear sky flux correspondto Φ 4x1012 and Φ 4x1015, respectively.The required area of the PGPd element according to (7) is:A ΔQVLN ΔQCq Φ η (T frame / N row Treadout ) 0.35 cm2 (13)According to (8) and (9) the Vdrop voltage is:Vdrop J ph(T/ N row Treadout ) 7.9m V (14)C j (VDD ')where Cj 43n [F/cm2] and Vbi 0.9V were obtained usingNA 2x1018 [cm-3] and ND 2x1016 [cm-3] which are typical valuesfor 0.18μm process (the reversed voltage was neglected). Note,the edge capacitance of the PGPd element can be neglectible,relatively to A·Cj.According to (13) the active area required for a properoperation of the whole QCIF SPS structure and the readoutcircuitry at the given illumination level and without need in aconventional power supply is 0.35 cm2. As mentioned in [16], thiscan be significantly reduced in applications, where small regionsof interests are processed. In these applications the required areaof the PGPd element is reduced by factor of M, showed in thefollowing expression:frameM N row N colX Y(15)4PGPd elements, the 'PGPd reset' transistor is implemented using anumber of transistors, connected in parallel, to allow fast reset ofPGPd element. The voltage value on the PGPd elements isbuffered using four simple source follower amplifiers. That is, thesignal value on the PGPd element is represented by two outputvoltages: Vout1 and Vout2. While the output swing of Vout1 is limitedto the range of approximately 0.7V to 1.8V, the voltage value ofVout2 is varying between 0V to 1V. These two output chains allowthe representation of the full swing of the output voltage. Thereason to use these two source amplifiers instead of one rail-torail amplifier was due to their simplicity and thus risk of faultreduction. The first two amplifiers (employing Vbias1 and Vbias2)have very low input capacitances to reduce the influence of thetest circuitry on the SPS operation. The other two buffers(employing Vbias3 and Vbias4) are sized to drive the off-chip loads.Fig. 8 shows the measurements of PGPd elements charge atlow illumination conditions. In this test, all pixels weredisconnected from the VDD' line. As can be seen, after the PGPdelements are reset to ground (the reset operation is performedevery 30msec), all PGPd elements are situated in the open circuitsconfiguration and linearly charged. As expected, the PGPdvoltage value is increased from 0V to 1.8V in 30msec (can beobserved in Fig. 8 by the combination of Vout1 and Vout2.),providing charge for SPS self-power capability. The same testwas also applied at different illumination levels (e.g. room light,clear sky and laser beam) and as expected, the time required tocharge the PGPd elements to VDD was decreased linearly with theincreasing of illumination level.where X and Y are the number of rows and columns in the regionof interest, respectively. For example, for the region of 10x15 therequired area is only 0.24mm2.V. TEST CHIP MEASUREMENTSA test chip, consisting of 7x7 SPS array, was implemented in astandard TSMC 0.18µm CMOS technology. Figure 6 shows thelayout of 14μmx14μm single SPS pixel with an in-pixel PGPd.The pixel employs a standard n /p-sub photodiode, as a sensingelement, similarly to the pixel shown in Fig. 1. The sizes of thephotodiode and each PGPd element are approximately 14 µm2and 60 µm2, respectively.Figure 6. Layout of a single SPS pixelA variety of tests were carried out to prove the SPS concept. Theelectrical scheme of the fabricated circuit, including additionalelements for testing is shown Fig. 7. This figure shows the pixels1, k and 7 (out of 7) of a single row. As mentioned before, allPGPd elements are connected to the power generated VDD' line.The 'Reset' and 'RS' lines are common for each row. The PGPdelements can be reset to ground using the 'PGPd reset' line viaNMOS transistor. Because of relatively large capacitance of allFigure 8. Measurement of the PGPd elements charging at lowillumination conditions.An additional test, examining SPS operation, is presented in Fig.9. In this test two phases can be clearly distinguished, i.e. T1 andT2. During the first phase (T1), both PGPd and photodiodes aredisconnected each from other (all Reset transistors from Fig. 7 areoff) and exposed to incident illumination. During T1, the PGPdelements are charged to VDD (Vout1 in Fig. 9) and on the otherhand, the voltage value of the APS photodiodes is zero. From thebeginning of the T2, the SPS array is situated in dark conditionsand the Reset transistors turn on in the rolling shutter fashion[17]. As can be observed, the voltage on the PGPd elements isdeclined according to charge sharing between the PGPd overallcapacitance and the total capacitance of the APS i row (includingthe photodiodes capacitance and the parasitics associated withthat node). The total voltage drop in the PGPd elements is 450mV(out of 1.8V) which is approximately the relation between theAPS photodiodes and PGPd capacitances.
PAPER IDENTIFICATION NUMBER - 19015Figure 7. The electrical scheme of the fabricated circuit, including additional elements for testing.[5][6][7][8]Figure 9. Measurement of the charge sharing between the PGPdoverall capacitance and the total capacitance of the APS i-th rowVI. CONCLUSIONS AND FURTHER RESEARCHConsiderations for CMOS image sensors with self-powergeneration capability design were presented. A detailedquantitative and qualitative discussion was carried outsuccessfully demonstrated, that the proposed SPS architectureallows generation of electric power for the whole APS array andsignal readout circuitry operation. This makes image sensorsusing the SPS architecture very useful in applications where ultralow-power is the main demand. A test chip, consisting of 7x7 SPSarray, was designed in a standard TSMC 0.18µm CMOS and themeasurements results support the SPS concept and the theoreticalanalysis.Further work should be concentrated on the improving of thePGPd elements efficiency in order to reduce the demand for diearea. In addition, large APS array with full self-power generationcapability will be designed.REFERENCES[1][2][3][4]C. Xu, W. Zhang, W. Ki and M. Chan, "A 1.0-V VDD CMOS ActivePixel Sensor With Complementary Pixel Architecture and PulsewidthModulatio
CMOS imagers, utilizing Self-Powered Sensors (SPS) is a new approach for ultra low-power CMOS Active Pixel Sensors (APS) implementations. The SPS architecture allows generation of electric power by employing a light sensitive device, located on the same silicon die with an APS and thus redu
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image sensors first appeared in the late 1960s,'3 most of todays CMOS image sensors are based on work done starting around the early 1980's. Until the early 1990s PPS was the CMOS image sensor technology of choice.'4'8 The feature sizes of the available CMOS technologies were too large to accomodate more than a
CMOS APS: The CMOS pixel sensors use a photogate or photodiode to capture the photon flux and convert it into corresponding electrical charge. The main photodiode type MOS pixel sensors which use the photon flux integration mode can be divided into 2 basic approaches, i.e. of passivepixels (PPS) and active pi
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