Digital Filter Design Using FPGA - IJEIT
ISSN: 2277-3754ISO 9001:2008 CertifiedInternational Journal of Engineering and Innovative Technology (IJEIT)Volume 5, Issue 4, October 2015Digital Filter Design Using FPGASuvadip Roy, L. Srivani, D. Thirugnana MurthyAtomic Energy Regulatory Board, Indira Gandhi Centre for Atomic ResearchAbstract - Nowadays Digital Filters are replacing AnalogFilters which are used widely in front end Electronics toremove the unwanted component from the signal and increasethe signal to noise ratio. Their widespread popularity isbasically because of a set of programmed coefficients derivedfrom the analog filter specifications which can in wholecontrol the filter operation and unlike analog filters the valueof bulky capacitors and inductors do not affect the filteroperability. Initially digital filters were implemented on PDSPand ASIC. But due to the comparatively lower cost andcustomized design possibilities, FPGA based system havegained much popularity.Moreover most of the FPGAsarereprogrammable hence by programming different filtercoefficients the type of filter implemented can be changed asrequired.This work consists of designing a digital filter fromthe analog filter specifications and implementing the digitalfilter on a FPGA development board.Index Terms –Finite Impulse Response (FIR), InfiniteImpulse Response (IIR), Field Programmable Gate Arrays(FPGA), Multiply and Accumulate (MAC)I. INTRODUCTIONNowadays we live in the digital world where DigitalSignal Processing is used widely in several spheres anddomains. Filtering of unwanted signals from the desiredsignals have been used since time immemorial andnowadays filtering in the digital domain is used widelywhich has got several advantages over filtering in theanalog domain like increased accuracy, requirement oflower filter order and availability of various digital filtertypes and configurations to fit for a specific use.Moreover in case of analog filters with increase in theorder of the filter the number of filter componentsincreases which increases it‟s complexity. Anotherdisadvantage of analog Filters for which digital filterscame in the limelight is that the cut off frequency dependson the values of the filter components like resistor andcapacitor values, any change in component values whichis technically referred to as drift of components due totime or physical parameters like temperature, changes thecut off frequency of the filter. These problems areovercome in digital filters whose characteristics dependson the filter coefficients which once programmed for aspecific filter order and type do not change withtime.Moreover digital filters are advantageous over theanalog counterpart in the sense that they have faster rolloff, less transition width and less overshoot in case oftime domain operations [1]. For all these, digital filterscome handy in several real time applications like in frontend of Data Acquisition systems, Image processingapplications where it can be used to recover a blurredimage, in real time audio recording applications as well asin biomedical engineering fields like ECG signalDOI:10.17605/OSF.IO/48HYMprocessing where problems like baseline wander andremoval of 50 Hz power supply noise can be handled wellwith these filters.Moreover analog filters experienceripples in pass band and stop band whereas responses ofdigital filters is much flatter compared to analog filters. Inthe nuclear domain also digital filters are being usednowadays in front end electronics.Implementation of thefilter hardware using programmable Digital SignalProcessors(PDSP) or by using Application SpecificIntegrated Circuits (ASIC) [2] have become increasinglypopular. But due to lower cost and versatility of FieldProgrammable Gate Array (FPGA) technology, it ismostly preferred over ASIC / PDSP technology for filterimplementation and also because of its higher packagedensity and availability of Multiply and Accumulate(MAC) units which are the basic building blocks ofdigital filter hardware. Sometimes FPGA‟s with availableDSP resources are preferred for ease of filterimplementation. This paper contains an overview ofdigital filters and its types, basic design flow fordesigning digital filters, design and hardwareimplementation of a Moving Average Filter on aActel‟sPROSAIC3 FPGA development board and itsverification.II. DIGITAL FILTER BASICSDigital Filters are mainly classified into two types:i.Finite Impulse Response or Non recursive Filtersii.Infinite Impulse Response or Recursive FiltersFinite Impulse Response (FIR) Filters are those whoseoutput depends on present and past input only. They donot contain any feedback from output. The basicmathematical equation governing the output of such afilter is :y[n] b(0)*x[n] b(1)*x[n-1] .b(N)*x[n-N](1)Fig.(1) - Architecture of FIR filtersFig. 1 shows a basic Transversal realization of a FIRfilter [3]. Other form includes Cascade and Latticestructure realizations. The order of a filter depends on thenumber of delay lines present in the filter architecture.Again b[0],b[1] b[N] are called the Filter kernel or theFilter coefficients. Some varieties of the FIR filtersinclude Windowed Sinc, Moving average etc. Output ofRecursive or Infinite Impulse Response (IIR) FiltersPage 78
ISSN: 2277-3754ISO 9001:2008 CertifiedInternational Journal of Engineering and Innovative Technology (IJEIT)Volume 5, Issue 4, October 2015depends on present input, past inputs as well as pastIII. BASIC DESIGN FLOWFor designing any digital filter, a sequence of steps asoutputs. So these filters have feedback from the output.mentioned in Fig.3 is required:FORM FILTERSPECIFICATIONSDERIVE FILTERCOEFFICIENTSFig.(2) - Architecture of IIR filtersHere the filter consists of two set of coefficients thenumerator and denominator coefficients called therecursion coefficients. Fig.2 shows Direct-Form – Irealization of the filter [3]. Other forms include DirectForm-II, Lattice and Lattice Ladder structure. The basicequation governing the output of such a filter is:y[n] 1/a(0) * {b(0)*x[n] b(1)*x[n-1] .b(P)*x[n-P] – a(1)* y[n-1] -a(2)*y[n-2] - .a[Q]*y[nQ] }(2)Where P is the order of the Feed forward Network and Qis the order of the Feedback network The basic propertyof these Filters is that their impulse response last tillinfinite time but generally it can be truncated after somecoefficients as the other coefficients seldom have majorcontribution. Butterworth, Chebyshev Type –I & II andElliptic filters are a few examples. The basic Filteringoperation is called „Convolution‟. The time domainoutput depends on the convolution results of the inputwith the Filter coefficients.y[n] x[n] * h[n](3)Where h[n] is the impulse response of the filter popularlycalled the filter coefficients in case of FIR filters. It canbe seen from the basic filtering architecture that the basicoperation consists of multiplication and addition whichare the two major mathematical operations and are wellperformed by the Multiply & Accumulate units (MAC)[4].Table (I) – Selection Criteria for Digital FiltersTYPE OF FILTERCRITERIONSELECTION1.FIRStable response,linear phase2.IIRFaster processing, economical.ButterwrothFlat response,a.FORHigher transition width, higherorder.b.ChebyshevExhibit ripples,fasteroff,lower order.DOI:10.17605/OSF.IO/48HYMrollCHECK MODELUSINGMATHEMATICALSOFTWAREDEVELOP FILTERHARDWARE USINGVHDLTESTING &VERIFICATIONFig. (3) - Basic Design FlowA. Forming the Filter SpecificationsThe first step consists of forming the digital filterspecifications from the analog filter specifications likeselecting the sampling rate, the type of filter and the orderof the filter. Whether a FIR or IIR filter is requireddepends on the specific area where the filter needs to beapplied like if linear phase response is required then aFIR filter should be the ideal choice or else if speed ofoperation is the factor an IIR filter may be preferred.Moreover the specific category of filter whether aButterworth or a Chebyshev filter would be requireddepends on the kind of response needed. Like ifequiripple response is required then a higher orderButterworth is the ideal requirement. Whereas if the mainrequirement is to minimize the filter order then aChebyshev or an Elliptic filter which may exhibit ripplesin the pass band and in the stop band may solve thepurpose [5]. The type of filter suitable for specificpurpose is covered in Table. I. Once the Type and theorder of the filter as well as it‟s cut off frequency isformulated then the next step becomes finding the filtercoefficients specific to the filter to be designed.Page 79
ISSN: 2277-3754ISO 9001:2008 CertifiedInternational Journal of Engineering and Innovative Technology (IJEIT)Volume 5, Issue 4, October 2015g. Shift the input signal one step to the left of eachB. Deriving Filter Coefficients& Checking responsecell of array at each clock instant.using Mathematical SoftwareOne way of finding the filter coefficients is to deriveh. Convert the result from integer to logic vector.them from the „Z‟ domain transfer function. The generali. Give real time output to the output port.equation is as :The above algorithm gives the basic steps for writinga0 a1z-1 a2z-2 . anz-nthe VHDL code. In step (e) truncation is required becauseH(z) DL only allows multiplication of integers and division1 b1z-1 b2z-2 bnz-n(4)by any integer in the power of 2 because in generaldivision means left shift of bits. [7] Once the code isWhere a0, a1 are the numerator coefficients and b0,ready, simulation has to be performed using the testb1 are the denominator coefficients. For a FIR filterbench by giving specific input combinations anddenominator is 1.checking the Pre Synthesis, Post Synthesis and PostAnother way of finding the coefficient is by use ofLayout Simulation results using the same test bench. Ifsoftwaretoolsforfastercalculations.Severalthe results are as predictedit proves that the logic havemathematical software‟s are available which can directlybeen implemented correctly. The next step in that case isfind out the filter coefficients given the correspondingto create the programming file and burn it into the FPGAfilter specifications. The response of filter with theand check the results else reprogramming has to bederived coefficients to test inputs by simulation can alsoattempted. [8]be found out to establish the filtering capability.D. Testing & VerificationMoreover verificationof unwanted frequency componentsremoved while filtering can also be performedbyDesign Entrycomparing the frequency spectrum of the input and theUsing VHDLoutput. The basic algorithm is as follows:a. Give the input specifications.Behavioralb. Derive the filter coefficients.Simulationc. Give a test signal in time domain to the filterhaving the coefficients as found in the abovestepSynthesisd. Observe the response in time domain for theSame Testfilter to the test input.e. Observe the frequency spectrum of the input andPost-SynthesisBenchfiltered signal to check for any unwantedSimulationcomponent.[6]C.Designing Filter Hardware using VHDLThe design entry and simulations are carried out usingActel'sLibero IDE and the experiments are performedusing the FPGA development board.The entire project iscreated using Actel‟sLibero IDE as the FPGA used forprogramming is an Actel designed PROSAIC3 FPGA.The basic algorithm implemented using HDL for FIRfilters is as follows:a. Declare an array of Integers to store Inputsample values.b. Declare the required library functions.c. Declare the filter entity consisting of Input portsfor input signal and clock signal and output portfor output filtered signal.d. In the filter architecture convert the input datafrom logic vector to integer for calculationflexibility.e. Truncate the Floating point filters coefficientsinto fixed point like if coefficient is 0.129 then itshould be like 129/1024 so accuracy ofcoefficients is around 97%.f. Implement convolution operation by repeatedmultiplication and addition at each clock‟s risingedge.DOI:10.17605/OSF.IO/48HYMPlace & RoutePost LayoutSimulationFPGAVerificationFig. (4)- VLSI Design FlowFig. (4) Shows the VLSI design flow model in whichthe steps including Synthesis of the VHDL code into Gatelevel net list, Placing and routing the gates to produce thedevice programmable bit steam was done in the previousstep, the next step included generating the programmingbit file and burning it on to the FPGA. For testing astudent development kit was used and verified that thehardware was functioning properly by giving properdigitalized test inputs and checking the output pattern.Ideal testing platform would be to inject an analog signalwith noise riding on it, digitalizing the signal with ananalog to digital converter (ADC), filtering the sequencePage 80
ISSN: 2277-3754ISO 9001:2008 CertifiedInternational Journal of Engineering and Innovative Technology (IJEIT)Volume 5, Issue 4, October 2015by passing it through the filter hardware implemented onThe Seven point moving average filter with the abovethe FPGA, sending back the filtered signal to a digital tofilter coefficients was designed using HDL and a testanalog converter (DAC) for reconstruction and thenbench was written to verify the design during Behavioralcomparing the initial input and the filtered output but inSimulation, Post-synthesis Simulation & Post-layoutthis case as the FPGA kit did not have an inbuilt ADC,simulation. Finally the generated bit stream afterso the input had to be digitalized and the digitalizedsuccessful Post Layout simulation step was programmedsamples were stored in specific location in the FPGAinto the PROSAIC3 FPGA (Device- M1A3P1000 ,which would be fetched by the filter at appropriate clockPackage – 484 FBGA) using a JTAG interface . Responseedges and filtering operation would be implemented onof the filter was checked and found to be appropriate.the samples.IV. DESIGN OF A MOVING AVERAGE FILTEROut of the several filters designed by the generalizedsteps mentioned above one unique time domain filter thatwas designed was a Moving Average filter which is usedto filter out the time domain disturbances sitting on thesignal. It is a FIR filter and a 6th order Moving Averagefilter was designed. The Input output relationship is givenby:y[n] {x[n] x[n-1] x[n-2] x[n-3] x[n-4] x[n-5] x[n-6]}/7So the filter impulse response is given by:h[n] {0.142,0.142,0.142,0.142,0.142,0.142,0.142}The response of the filter to test inputs were seen byusing a mathematical software by generating noisysimulated inputs and checking the output after passingthrough the filter with the above coefficients. Fig. (5)shows the simulated input waveform, whereas Fig. (6)gives the output after filtering during lockDIVM(FilterMMHCHCKFig. (7) –Block Diagram of FPGA Internal ConfigurationFig. (7) gives the internal modules designed within theFPGA hardware. The actual hardware implemented in theFPGA was divided into five modules namely the clockdivider, Address increamenter, Filter module, MemoryUnit and the Checker module. The clock divider modulewas used to convert the reference frequency available inthe board into a lower frequency required for operationand to synchronize the operation of the other modules. Asno inbuilt ADC module was present on board, samples ofthe input signal was stored in the Memory unit in from of8 bit samples in 32 memory location. The Addressincreamenter was used as a 5 bit counter to fetch onesample at a time from a particular memory location andgive it to the Filter module. The output obtained from theFilter module was checked in the checker module wherethe bit steam corresponding to the envisaged output wasstored. If the output of the Filter and the checker modulematched then it would light up a LED interfaced to theFPGA.-1-1.5020406080Time100120140160Fig. (5) –Noisy Input to the 20Fig. (6) –Filtered OutputDOI:10.17605/OSF.IO/48HYM140160V. RESULTS & DISCUSSIONSDigital Filters were designed by defining the filterspecifications in the analog domain, transforming theanalog filter specification into digital filter specification,defining the order of the filter, the sampling rate and typeof filter to be used like a FIR or an IIR filter dependingon the specifications like pass band ripple, linear phaserequirement etc. The coefficients were derived for thefilter based on the specifications and response checkswere done using mathematical software with the samefilter coefficients derived earlier to check the output forthe filter designed from the given specifications. VHDLwas used in the design entry stage to implement the filterhardware. Test bench written in VHDL was used to checkthe correctness of hardware implementation as a part ofbehavioral simulation (after design entry), post-synthesisPage 81LED
ISSN: 2277-3754ISO 9001:2008 CertifiedInternational Journal of Engineering and Innovative Technology (IJEIT)Volume 5, Issue 4, October 2015[7] “Digital Signal Processing Using Field Programmable Gatesimulation (after the code is converted to a gate level netArrays”, Uwe-Meyer-Baese, Springer publication.list using a synthesizer) and post-layout simulation (afterplacement & routing). For all the three phases of[8] Sara Grassi, Alexandre Heubi, Micheal Ansorge, Faustosimulation, the same test bench was used.Actel‟sPellandini.”Study of a VLSI implementation of a noisereduction algorithm for Digital hearing aid”, EUSIPCO,PROSAIC3 FPGA kit was programmed with the1994, pp-1661-1664.generated bit stream using a JTAG interface and testinputs in real time were given and filtering capabilities of[9] E.C Tan. “Variablelowpass wave-digital filters”,Electronics letters, vol.18 No.8, pp.324-326.the designed filter hardware was checked and found to beappropriate.[10] S.S Ahuja&.S.C Dutta Roy. “Variable Digital Filters”,VI. CONCLUSIONFilters such as seven point moving average filter fortime domain filtering or waveform shaping, frequencyselective filters like low pass, high pass filters wereimplemented and checked.A tunable Low pass FIR filterwas also designed which can be tuned in the frequencyrange from 1Khz to 15Khz according to the user selectinputs [9-10]. Moreover an IIR Butterworth 6th orderNotch filter was designed to suppress power supplyinterference. An all pass filter in form of a Hilberttransformer which would cause a phase change of 90degree to all frequency components was implemented.This work concludes that in future digital filters can beimplemented in flexible FPGA based architecture wherethe coefficients can be programmed and changed whenrequired to implement filters of specific requirement.Concepts of tunable filters based on user selection canalso be implemented using such flexible architecture.IEEE trans. Circuits.Systms, vol-CAS- 27, N.O-9, pp.836838.AUTHORS PROFILEShri Suvadip Roy is an Electronics Engineer from 56 thBatch of BARC Training School. He has done his ring. Currently he is working as a NuclearRegulator in Atomic Energy RegulatoryBoard and isassociated with review of Instrumentation & ControlAspects of Nuclear Power Plants. His Area of Interest includes DigitalElectronic Systems, Digital Signal Processing, NeutronicInstrumentaion,Modern Control Theory & Use of Programmable Logic Devices (FPGA &CPLD) in Safety Critical Applications in Nuclear Power Plants.VII. FUTURE ENHANCEMENTTime domain Filters to deal with salt and pepper noiseand shot noise which are seen in daily life and will behelpful in front end signal processing to be attempted andimplemented in real time signal processing applications.VIII. ACKNOWLEDGEMENTI sincerely acknowledge the opportunity given to meby BARC Training School (IGCAR campus), AERB&Director, EIRSG, IGCAR for carrying out the work.REFERENCES[1] Vijender Saini, Balwinder Singh & Rekha Devi, “Areaoptimization of FIR filter and its implementation inFPGA”, International Journal of Recent Trends inEngineering, Vol 1, No. 4, pp. 55-58, May 2009[2] Kowalski J.E. &Berner, J.B, “ Digital Filter ASIC ForNASA deep space radio science receiver” ASICconference & Exhibit, pp.39 – 42, 18-22 Sep 1995, Austin,TX.[3] “Digital Signal Processing”, Ramesh Babu, 4th edition.[4] A.Heubi, M.Ansorge, F.Pellandini. “Low powerArchitecture for Digital Signal Processing”, GRETSI,1993, 3661-3664.[5] “The Scientists & Engineers guide to Digital Signalprocessing”, Steven.W.Smith.[6] www.mathworks.comDOI:10.17605/OSF.IO/48HYMPage 82
using the FPGA development board.The entire project is created using Actel‟sLibero IDE as the FPGA used for programming is an Actel designed PROSAIC3 FPGA. The basic algorithm implemented using HDL for FIR filters is as follows:- a. Decl
Step 1: Replace ASIC RAMs to FPGA RAMs (using CORE Gen. tool) Step 2: ASIC PLLs to FPGA DCM & PLLs (using architecture wizard), also use BUFG/IBUFG for global routing. Step 3: Convert SERDES (Using Chipsync wizard) Step 4: Convert DSP resources to FPGA DSP resources (using FPGA Core gen.)
In this thesis, FPGA-based simulation and implementation of direct torque control (DTC) of induction motors are studied. DTC is simulated on an FPGA as well as a personal computer. Results prove the FPGA-based simulation to be 12 times faster. Also an experimental setup of DTC is implemented using both FPGA and dSPACE. The FPGA-based design .
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Filter Gallery dialog box A. Preview B. Filter category C. Thumbnail of selected filter D. Show/Hide filter thumbnails E. Filters pop‑up menu F. Options for selected filter G. List of filter effects to apply or arrange H. Filter effect selected but not applied I. Filter effects applied cumulatively but not selected J. Hidden filter effect Display the Filter Gallery
I am FPGA novice and want to try classical FPGA design tutorials. I bought perfect modern FPGA board ZYBO (ZYnq BOard) based on Xilinx Z-7010 from Digilent but latest tools from Xilinx VIVADO 2015.2 more focused on AP SoC programming while I want to just pure FPGA de
3 FPGA, ASIC, and SoC Development Projects 67% of ASIC/FPGA projects are behind schedule 75% of ASIC projects require a silicon re-spin Over 50% of project time is spent on verification Statistics from 2018 Mentor Graphics / Wilson Research survey, averaged over FPGA/ASIC 84% of FPGA projects have non-trivial bugs escape into production
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