FPGA Technology And Industry Experience - Enclustra
FPGA Technology and Industry Experience Guest Lecture at HSLU, Horw (Lucerne) May 24 2012 Oliver Bründler, FPGA Design Center, Enclustra GmbH Silvio Ziegler, FPGA Design Center, Enclustra GmbH
Content Enclustra GmbH Real-World FPGA Application Company Profile FPGA Basics Software Defined Radio Example Project FPGA Architecture FPGA Design Flow Motion Control Conclusions Field Update The Case for FPGAs FPGA vs. ASIC Outsourcing FPGA vs. DSP Skills How to Stand Out Enclustra GmbH -2- 18.05.2012
Content Enclustra GmbH Real-World FPGA Application Company Profile FPGA Basics Software Defined Radio Example Project FPGA Architecture FPGA Design Flow Motion Control Conclusions Field Update The Case for FPGAs FPGA vs. ASIC Outsourcing FPGA vs. DSP Skills How to Stand Out Enclustra GmbH -3- 18.05.2012
Enclustra GmbH – Company Profile Quick Facts FPGA Solution Center FPGA Modules Founded in 2004 Mars, Mercury and Saturn Located at Technopark Zurich IP Cores Currently 8 employees TFT Display Controller Vendor-Independent Universal Drive Controller FPGA Design Center Etc. FPGA-Related Design Services Firmware (VHDL/Verilog) Hardware (incl. analog and digital interfaces) Embedded Software (for FPGA soft processors) Enclustra GmbH -4- 18.05.2012
Content Enclustra GmbH Real-World FPGA Application Company Profile FPGA Basics Software Defined Radio Example Project FPGA Architecture FPGA Design Flow Motion Control Conclusions Field Update The Case for FPGAs FPGA vs. ASIC Outsourcing FPGA vs. DSP Skills How to Stand Out Enclustra GmbH -5- 18.05.2012
FPGA Basics – FPGA Architecture The Big Picture Field Programmable Gate Array Regular array of configurable logic blocks I/O Many Flip-Flops available I/O S I/O S I/O S S I/O Logic Block I/O Configurable I/O blocks Logic Block I/O Dedicated clock management blocks S Configuration data stored in distributed SRAM cells I/O S S RAM Block S Logic Block S DSP Block DSP blocks DSP Block RAM Block I/O Embedded RAM blocks S Logic Block I/O S S I/O Logic Block S I/O Logic Block I/O S I/O -6- DSP Block RAM Block I/O I/O Enclustra GmbH I/O S I/O S I/O I/O 18.05.2012
FPGA Basics – FPGA Architecture DSP Blocks DSP blocks are used to implement fixed-point arithmetic operations Typically 18 x 18 bit multiplier 48 48 bit adder/accumulator DSP Block Pre-adder for symmetric FIR filters MULT Dynamic configuration via OPMODE A C Highly pipelined (configurable) B x Up to 600 MHz clock frequency Support for carry and adder chains ACCU ADD OPMODE 4 . 4000 per FPGA Pre-Adder Multiplier Post Adder / Accumulator Up to 2400 GMAC/s per FPGA!!! Enclustra GmbH -7- 18.05.2012
FPGA Basics – FPGA Architecture Time Division Multiplexing (TDM) Register replication 50 MHz State registers: Yes Pipeline registers: No x BRAM/SRL can be used Advantages Power Area 200 MHz Less hard macros Disadvantages x Longest path Debugging Enclustra GmbH -8- 18.05.2012
FPGA Basics – FPGA Design Flow Floorplanning Floorplanning Required for highest performance Grouping of components which belong together Keep floorplan in mind while designing Pipelining for long connections Placement of specific resources «Holes» due to hard macros Directions of carry chains Enclustra GmbH -9- 18.05.2012
Content Enclustra GmbH Real-World FPGA Application Company Profile FPGA Basics Software Defined Radio Example Project FPGA Architecture FPGA Design Flow Motion Control Conclusions Field Update The Case for FPGAs FPGA vs. ASIC Outsourcing FPGA vs. DSP Skills How to Stand Out Enclustra GmbH - 10 - 18.05.2012
The Case for FPGAs – FPGA vs. ASIC FPGAs can‘t beat ASICs when it comes to Parameter FPGA ASIC Low power Clock frequency ü Ultra small form factor Power consumption ü Ultra high design security Form factor ü Ultra high volume Design security ü ASICs need volume to overcome the NRE penalty NRE increase with each process shrink FPGA logic gets cheaper with each process shrink Reconfiguration ü Redesign risk (weighted) ü NRE ü Time to market ü Total Cost FPGA vs. ASIC The break-even is moving towards higher volumes with each process shrink Total Cost FPGA Remote update and faster time to market become more and more important Trend ASIC FPGAs gain ground in the ASIC domain FPGAs are often used for ASIC prototyping Enclustra GmbH ASIC NRE FPGA Domain ASIC Domain Volume - 11 - 18.05.2012
The Case for FPGAs – FPGA vs. DSP DSPs are widely used in low-cost, lowpower and low- to mid- performance systems Parameter DSPs suffer from their serial instruction stream when it comes to more complex systems running at high sample rates FPGA System performance ü Multi-channel architecture ü Many operations per sample ü DSP Many conditional operations ü FPGAs can provide a performance boost of 10.1000 compared to DSPs for such applications (e.g. software defined radio). Floating point ü Absolute power consumption ü FPGAs even excel when compared in MAC/ and MAC/W. Performance FPGA vs. DSP Operations per Sample Hard-macro CPU cores in the FPGAs take over traditional DSP tasks (e.g. complex protocol stacks), enabling single-chip high-performance signal processing systems Enclustra GmbH - 12 - FPGA Domain DSP Domain Trend Sample Rate 18.05.2012
Content Enclustra GmbH Real-World FPGA Application Company Profile FPGA Basics Software Defined Radio Example Project FPGA Architecture FPGA Design Flow Motion Control Conclusions Field Update The Case for FPGAs FPGA vs. ASIC Outsourcing FPGA vs. DSP Skills How to Stand Out Enclustra GmbH - 13 - 18.05.2012
Real-World Application – Software Defined Radio Software defined radio RF Frontend Most of the signal processing of a RF receiver/transmitter is done in „software“ FPGA ADC Interface Real-world application 1 Stream Real-Valued 2.4 GHz RF receiver Parallel baseband-processing of all 40 channels with a time division multiplexed datapath architecture Demodulators (FSK, PSK) 40 x 2 Msps Channel Filter Bank 40 Channels Complex 40 x 2 Msps Demodulator 40 Channels 40 x 1 MSps Packet Engine Spartan-3A DSP low-cost FPGA 126 multipliers running at 240 MHz clock frequency 30 giga multiplications per second Ported to Spartan-6 LX TDM / Floorplanning Enclustra GmbH 40 Channels Complex Register Bank Down conversion to 40 channels at 2 Msps each Channel filters 240 Msps Down Converter 240 Msps sampling rate SPI Local Interface Host PC - 14 - 18.05.2012
Content Enclustra GmbH Real-World FPGA Application Company Profile FPGA Basics Software Defined Radio Example Project FPGA Architecture FPGA Design Flow Motion Control Conclusions Field Update The Case for FPGAs FPGA vs. ASIC Outsourcing FPGA vs. DSP Skills How to Stand Out Enclustra GmbH - 15 - 18.05.2012
Example Project – Motion Control Specification Technical requirements: General information: Motion control platform for next-generation products Motion control module Up to 4 DC or 2 stepper motors Up to 2 BLDC motors in a later stage CAN interface High-volume ( 10‘000 units/year) Commercial requirements: Manufacturing costs X Trajectory planner/integrator 1.5 KHz position/velocity control Available no later than day Y 10.100 KHz current control Engineering costs are secondary 4 integrated FET H-bridges Credit-card size Enclustra GmbH - 16 - 18.05.2012
Example Project – Motion Control Project Setup General project setup: Team setup at the customer: The customer is responsible for hardware design, production and embedded software 1 project manager 2 embedded software engineers Enclustra is responsible for FPGA firmware and FPGA-related system design issues Team setup at Enclustra: 2 hardware engineers and The strategic procurement department 1 project manager and 1 FPGA firmware engineer The upper management 1 hardware consultant and Many potential users of the motion control module Enclustra GmbH - 17 - 18.05.2012
Example Project – Motion Control Project Schedule (Basic Functions) System Design Hardware Support Hardware Design / Schematics / Layout Hardware Production FPGA Firmware Embedded Software Bring-Up, Integration & Test - 18 - an ce Ac ce pt Cu st om er La yo ut Fr ee ze Sc he m at ics De sig n Sy st em Ki ck -O f Enclustra GmbH Fr ee Fi ze rs tP ro to ty pe s 3rd Party Fr ee ze Enclustra f Customer 18.05.2012
Example Project – Motion Control System Design (1) Altera Cyclone III FPGA SPI Master Register Bank DC Motor Controller Nios II CPU with FPU CAN IP Core Shared Memory Nios II DSP with FPU Stepper Motor Controller Communication, configuration, trajectory planning, I/O handling Enclustra GmbH Trajectory integration, position and velocity controllers - 19 - Current sensing and current controllers, commutation, PWM generation 18.05.2012
Example Project – Motion Control First Prototypes! Bring-Up Position 1.200 Power, clocks, FPGA configuration Position [rot] Nios II booting and JTAG communication 1.000 0.800 DesPos 0.600 ActPos 0.400 0.200 First tests on hardware 0.000 1 6 11 16 21 26 31 36 41 46 51 56 61 66 71 76 81 86 91 96 101 106 111 116 121 126 131 136 141 146 151 156 161 166 171 176 181 Tim e [m s] The first logged move! ActVel 16.000 14.000 Velocity [rot/s] 12.000 10.000 8.000 ActVel 6.000 4.000 2.000 0.000 1 6 11 16 21 26 31 36 41 46 51 56 61 66 71 76 81 86 91 96 101 106 111 116 121 126 131 136 141 146 151 156 161 166 171 176 181 Tim e [m s] Acceleration 500.000 400.000 Acceleration [rot/s 2] 300.000 200.000 100.000 0.000 -100.000 ActAcc 1 6 11 16 21 26 31 36 41 46 51 56 61 66 71 76 81 86 91 96 101 106 111 116 121 126 131 136 141 146 151 156 161 166 171 176 181 -200.000 -300.000 -400.000 -500.000 Tim e [m s] Enclustra GmbH - 20 - 18.05.2012
Example Project – Motion Control FPGA Resources over Time FPGA Resources over Time FPGA Resources FPGA Resource Limit New Features More New Features BLDC Motor (FOC) Basic Functions Enclustra GmbH Small Improvements Time - 21 - 18.05.2012
Content Enclustra GmbH Real-World FPGA Application Company Profile FPGA Basics Software Defined Radio Example Project FPGA Architecture FPGA Design Flow Motion Control Conclusions Field Update The Case for FPGAs FPGA vs. ASIC Outsourcing FPGA vs. DSP Skills How to Stand Out Enclustra GmbH - 22 - 18.05.2012
Conclusions – Field Update FPGAs allow fast market entry thanks to their field update capability This often leads to the fallacy that FPGA development does not require thorough verification („we can fix an error after it occurs“) This might be partly true for non security relevant applications running in static ambient conditions FPGA development actually IS done like this a lot more than one might think This often wrongs FPGA technology in the user‘s minds, because there WILL be errors in this case The development of a reliable FPGA system does not get by without thorough verification! Verification may include behavioral simulation and tests running on the hardware Enclustra GmbH - 23 - 18.05.2012
Conclusions – Outsourcing Make or buy – the case for outsourcing FPGA development Successful and efficient FPGA design requires in-depth knowledge of Basic digital and analog circuit design, chip design, VLSI HDL (VHDL/Verilog/etc.), FPGA architecture and tools High-speed hardware design Deployed algorithms, I/O standards, protocols, etc. Many companies have extensive knowledge in their application area, but do not have the required expertise for successfully employing FPGA technology Building up FPGA know-how is a lengthy and expensive process Collaboration between application specialists and FPGA technology experts shows great promise for successful product development Enclustra GmbH - 24 - 18.05.2012
Conclusions – Skills FPGA jobs in engineering services - what skills do we expect? Technical skills Basic digital and analog circuit design, chip design, VLSI (very important) HDL (VHDL, Verilog, etc.) Basic understanding of FPGA architecture and tools Basic understanding of DSP and SoPC Soft skills Keen perception also for complex structures Good communication with customers and colleagues Ability to work in a team Flexibility for changing tasks quickly Enclustra GmbH - 25 - 18.05.2012
Conclusions – How to Stand Out How can an FPGA engineering company stand out from the crowd? Focus on FPGA technology (don‘t be a „general merchandise store“) Key application domains (e.g. DSP, SoPC, etc.) Provide solutions, not only engineering resources FPGA modules as HW platform IP cores for complex building blocks Custom design for custom functionality System integration Not only make the customer happy, but also make him successful What the customer initially wants is most often not what he really needs Enclustra GmbH - 26 - 18.05.2012
Questions? Oliver Bründler Enclustra GmbH bruendler@enclustra.com Fon 41 43 343 39 40 Silvio Ziegler Enclustra GmbH ziegler@enclustra.com Fon 41 43 343 39 46 Slides in PDF format: http://www.enclustra.com/de/company/publications/ Enclustra GmbH - 27 - 18.05.2012
FPGA ASIC Trend ASIC NRE Parameter FPGA ASIC Clock frequency Power consumption Form factor Reconfiguration Design security Redesign risk (weighted) Time to market NRE Total Cost FPGA vs. ASIC ü ü ü ü ü ü ü ü FPGA Domain ASIC Domain - 11 - 18.05.2012 The Case for FPGAs - FPGA vs. ASIC FPGAs can't beat ASICs when it comes to Low power
In this thesis, FPGA-based simulation and implementation of direct torque control (DTC) of induction motors are studied. DTC is simulated on an FPGA as well as a personal computer. Results prove the FPGA-based simulation to be 12 times faster. Also an experimental setup of DTC is implemented using both FPGA and dSPACE. The FPGA-based design .
Step 1: Replace ASIC RAMs to FPGA RAMs (using CORE Gen. tool) Step 2: ASIC PLLs to FPGA DCM & PLLs (using architecture wizard), also use BUFG/IBUFG for global routing. Step 3: Convert SERDES (Using Chipsync wizard) Step 4: Convert DSP resources to FPGA DSP resources (using FPGA Core gen.)
The LabVIEW implementation of the control system consisted of two main parts; (i) host PC virtual instrument (VI) and (ii) FPGA VI. A host PC VI was deve loped to model the PID control transfer function and inter act with the FPGA based RIO hardware. The FPGA VI was programmed in LabVIEW and synthesized to ru n on the FPGA.
5.2 Inspection of Structural Adder Using Schematic and fpga editor 5.2.1 Schematics and FPGA layout Now let’s take a look at how the Verilog you wrote mapped to the primitive components on the FPGA. Three levels
3 FPGA, ASIC, and SoC Development Projects 67% of ASIC/FPGA projects are behind schedule 75% of ASIC projects require a silicon re-spin Over 50% of project time is spent on verification Statistics from 2018 Mentor Graphics / Wilson Research survey, averaged over FPGA/ASIC 84% of FPGA projects have non-trivial bugs escape into production
FPGA, ASIC, and SoC Development Projects 67% of ASIC/FPGA projects are behind schedule 75% of ASIC projects require a silicon re-spin Over 50% of project time is spent on verification Statistics from 2018 Mentor Graphics / Wilson Research survey, averaged over FPGA/ASIC 84% of FPGA projects have non-trivial bugs escape into production
FPGA Resource Small FPGA Large FPGA Logic PLBs per FPGA 256 25,920 LUTs and flip -flops per PLB 1 8 System-on-Chip Test ArchitecturesEE141 Ch. 12 - FPGA Testing - P. 15 15 Routing Wire segments per PLB 45 406 PIPs per PLB 139 3,462 Specialized Cores Bits per memory core 128 36,864 Memory cores per FP
Archaeological Investigations and Recording 1994-2011 by David James Etheridge with scientific analysis by Dr David Dungworth Avon Archaeological Unit Limited Avondale Business Centre, Woodland Way, Kingswood, Bristol, BS15 1AW Bristol 2012 Illustration taken from the ‘Annales des Mines” Vol 10, dated 1825 . William Champion’s Warmley Brass and Zinc works, Warmley, South Gloucestershire .
