UltraScale Architecture And Product Data Sheet: Overview .
UltraScale Architecture andProduct Data Sheet: OverviewDS890 (v4.0) March 16, 2021Product SpecificationGeneral DescriptionXilinx UltraScale architecture comprises high-performance FPGA, MPSoC, and RFSoC families that address a vast spectrum ofsystem requirements with a focus on lowering total power consumption through numerous innovative technologicaladvancements.Artix UltraScale FPGAs: Highest serial bandwidth and signal compute density in a cost-optimized device for criticalnetworking applications, vision and video processing, and secured connectivity.Kintex UltraScale FPGAs: High-performance FPGAs with a focus on price/performance, using both monolithic andnext-generation stacked silicon interconnect (SSI) technology. High DSP and block RAM-to-logic ratios and next-generationtransceivers, combined with low-cost packaging, enable an optimum blend of capability and cost.Kintex UltraScale FPGAs: Increased performance and on-chip UltraRAM memory to reduce BOM cost. The ideal mix ofhigh-performance peripherals and cost-effective system implementation. Kintex UltraScale FPGAs have numerous poweroptions that deliver the optimal balance between the required system performance and the smallest power envelope.Virtex UltraScale FPGAs: High-capacity, high-performance FPGAs enabled using both monolithic and next-generation SSItechnology. Virtex UltraScale devices achieve the highest system capacity, bandwidth, and performance to address key market andapplication requirements through integration of various system-level functions.Virtex UltraScale FPGAs: The highest transceiver bandwidth, highest DSP count, and highest on-chip and in-package memoryavailable in the UltraScale architecture. Virtex UltraScale FPGAs also provide numerous power options that deliver the optimalbalance between the required system performance and the smallest power envelope.Zynq UltraScale MPSoCs: Combine the Arm v8-based Cortex -A53 high-performance energy-efficient 64-bit applicationprocessor with the Arm Cortex-R5F real-time processor and the UltraScale architecture to create the industry's firstprogrammable MPSoCs. Provide unprecedented power savings, heterogeneous processing, and programmable acceleration.Zynq UltraScale RFSoCs: Combine RF data converter subsystem and forward error correction with industry-leadingprogrammable logic and heterogeneous processing capability. Integrated RF-ADCs, RF-DACs, and soft decision FECs (SD-FEC)provide the key subsystems for multiband, multi-mode cellular radios and cable infrastructure.Family ComparisonsTable 1: Device ResourcesArtixUltraScale FPGAKintexUltraScaleFPGAKintexUltraScale FPGAVirtexUltraScaleFPGAVirtexUltraScale FPGAMPSoC Processing SystemZynqUltraScale MPSoCZynqUltraScale RFSoC RF-ADC/DAC SD-FEC System Logic Cells (K)Block Memory 090–3600–3613.5–45.00–81UltraRAM (Mb)0–16HBM DRAM (GB)DSP ,8801,320–12,288216–3,5281,872–4,272DSP Performance ��16Max. Transceiver Speed (Gb/s)16.316.332.7530.558.032.7532.75Max. Serial BW (bidir) (Gb/s)3932,0863,2685,6168,3843,2681,048Memory Interface Perf 2–408I/O Pins Copyright 2013–2021 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Spartan, UltraScale, Versal, Virtex, Vivado, Zynq, and other designated brands included hereinare trademarks of Xilinx in the United States and other countries. AMBA, AMBA Designer, Arm, Arm1176JZ-S, CoreSight, Cortex, and PrimeCell are trademarks of Arm inthe EU and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.DS890 (v4.0) March 16, 2021Product Specificationwww.xilinx.com1
UltraScale Architecture and Product Data Sheet: OverviewSummary of FeaturesRF Data Converter Subsystem OverviewMost Zynq UltraScale RFSoCs include an RF data converter subsystem, which contains multiple radiofrequency analog to digital converters (RF-ADCs) and multiple radio frequency digital to analogconverters (RF-DACs). The high-precision, high-speed, power efficient RF-ADCs and RF-DACs can beindividually configured for real data or in most cases can be configured in pairs for real and imaginary I/Qdata. See RF-ADCs and RF-DACs sections.Soft Decision Forward Error Correction (SD-FEC) OverviewSome Zynq UltraScale RFSoCs include highly flexible soft decision FEC blocks for decoding and encodingdata as a means to control errors in data transmission over unreliable or noisy communication channels.The SD-FEC blocks support low-density parity check (LDPC) decode/encode and Turbo decode for use in5G wireless, backhaul, DOCSIS, and LTE applications.Processing System OverviewZynq UltraScale MPSoCs and RFSoCs feature dual and quad core variants of the Arm Cortex-A53 (APU)with dual-core Arm Cortex-R5F (RPU) processing system (PS). Some devices also include a dedicated ArmMali -400 MP2 graphics processing unit (GPU). See Table 2.Table 2: Zynq UltraScale MPSoC and RFSoC Device FeaturesMPSoCRFSoCCG DevicesEG DevicesEV DevicesDR DevicesAPUDual-core Arm Cortex-A53Quad-core Arm Cortex-A53Quad-core Arm Cortex-A53Quad-core Arm Cortex-A53RPUDual-core Arm Cortex-R5FDual-core Arm Cortex-R5FDual-core Arm Cortex-R5FDual-core Arm H.264/H.265–To support the processors' functionality, a number of peripherals with dedicated functions are included inthe PS. For interfacing to external memories for data or configuration storage, the PS includes amulti-protocol dynamic memory controller, a DMA controller, a NAND controller, an SD/eMMC controllerand a Quad SPI controller. In addition to interfacing to external memories, the APU also includes a Level-1(L1) and Level-2 (L2) cache hierarchy; the RPU includes an L1 cache and Tightly Coupled memorysubsystem. Each has access to a 256KB on-chip memory.For high-speed interfacing, the PS includes 4 channels of transmit (TX) and receive (RX) pairs oftransceivers, called PS-GTR transceivers, supporting data rates of up to 6.0Gb/s. These transceivers caninterface to the high-speed peripheral blocks that support PCIe at 5.0GT/s (Gen 2) as a root complex orEndpoint in x1, x2, or x4 configurations; Serial-ATA (SATA) at 1.5Gb/s, 3.0Gb/s, or 6.0Gb/s data rates; andup to two lanes of Display Port at 1.62Gb/s, 2.7Gb/s, or 5.4Gb/s data rates. The PS-GTR transceivers canalso interface to components over USB 3.0 and Serial Gigabit Media Independent Interface (SGMII).DS890 (v4.0) March 16, 2021Product Specificationwww.xilinx.com2
UltraScale Architecture and Product Data Sheet: OverviewFor general connectivity, the PS includes: a pair of USB 2.0 controllers, which can be configured as host,device, or On-The-Go (OTG); an I2C controller; a UART; and a CAN2.0B controller that conforms toISO11898-1. There are also four triple speed Ethernet MACs and 128 bits of GPIO, of which 78 bits areavailable through the MIO and 96 through the EMIO.High-bandwidth connectivity based on the Arm AMBA AXI4 protocol connects the processing units withthe peripherals and provides interface between the PS and the programmable logic (PL).For additional information, go to: DS891, Zynq UltraScale MPSoC Overview.I/O, Transceiver, PCIe, 100G Ethernet, and 150G InterlakenData is transported on and off chip through a combination of the high-performance parallel SelectIO interface and high-speed serial transceiver connectivity. I/O blocks provide support for cutting-edgememory interface and network protocols through flexible I/O standard and voltage support. The serialtransceivers in the UltraScale architecture-based devices transfer data up to 58.0Gb/s, enabling 25G backplane designs with dramatically lower power per bit than previous generation transceivers. Alltransceivers, except the PS-GTR, support the required data rates for 8.0GT/s (Gen3), and 16.0GT/s (Gen4)for PCIe. The integrated blocks for PCIe can be configured for Endpoint or Root Port, supporting a varietyof link widths and speeds depending on the targeted device speed grade and package. Integrated blocksfor 150Gb/s Interlaken and 100Gb/s Ethernet (100G MAC/PCS) extend the capabilities of UltraScaledevices, enabling simple, reliable support for Nx100G switch and bridge applications. Virtex UltraScale HBM devices include Cache Coherent Interconnect for Accelerators (CCIX) ports for coherently sharing datawith different processors.Clocks and Memory InterfacesUltraScale devices contain powerful clock management circuitry, including clock synthesis, buffering, androuting components that together provide a highly capable framework to meet design requirements. Theclock network allows for extremely flexible distribution of clocks to minimize the skew, powerconsumption, and delay associated with clock signals. The clock management technology is tightlyintegrated with dedicated memory interface circuitry to enable support for high-performance externalmemories, including DDR4. In addition to parallel memory interfaces, UltraScale devices support serialmemories, such as hybrid memory cube (HMC).Routing, SSI, Logic, Storage, and Signal ProcessingConfigurable Logic Blocks (CLBs) containing 6-input look-up tables (LUTs) and flip-flops, DSP slices with27x18 multipliers, 36Kb block RAMs with built-in FIFO and ECC support, and 4Kx72 UltraRAM blocks (inUltraScale devices) are all connected with an abundance of high-performance, low-latency interconnect.In addition to logical functions, the CLB provides shift register, multiplexer, and carry logic functionality aswell as the ability to configure the LUTs as distributed memory to complement the highly capable andconfigurable block RAMs. The DSP slice, with its 96-bit-wide XOR functionality, 27-bit pre-adder, and30-bit A input, performs numerous independent functions including multiply accumulate, multiply add,and pattern detect. In addition to the device interconnect, in devices using SSI technology, signals cancross between super-logic regions (SLRs) using dedicated, low-latency interface tiles. These combinedrouting resources enable easy support for next-generation bus data widths. Virtex UltraScale HBMdevices include up to 16GB of high bandwidth memory.DS890 (v4.0) March 16, 2021Product Specificationwww.xilinx.com3
UltraScale Architecture and Product Data Sheet: OverviewConfiguration, Encryption, and System MonitoringThe configuration and encryption block performs numerous device-level functions critical to thesuccessful operation of the FPGA, MPSoC, or RFSoC. This high-performance configuration block enablesdevice configuration from external media through various protocols, including PCIe, often with norequirement to use multi-function I/O pins during configuration. The configuration block also provides256-bit AES-GCM decryption capability at the same performance as unencrypted configuration.Additional features include SEU detection and correction, partial reconfiguration support, andbattery-backed RAM or eFUSE technology for AES key storage to provide additional security. The SystemMonitor enables the monitoring of the physical environment via on-chip temperature and supply sensorsand can also monitor up to 17 external analog inputs. With Zynq UltraScale MPSoCs and RFSoCs, thedevice is booted via the Configuration and Security Unit (CSU), which supports secure boot via the 256-bitAES-GCM and SHA/384 blocks. The cryptographic engines in the CSU can be used after boot for userencryption.Migrating DevicesUltraScale and UltraScale families provide footprint compatibility to enable users to migrate designsfrom one device or family to another. Any two packages with the same footprint identifier code arefootprint compatible. For example, Kintex UltraScale devices in the A1156 packages are footprintcompatible with Kintex UltraScale devices in the A1156 packages. Likewise, Virtex UltraScale devices inthe B2104 packages are compatible with Virtex UltraScale devices and Kintex UltraScale devices in theB2104 packages. All valid device/package combinations are provided in the Device-Package Combinationsand Maximum I/Os tables in this document. Refer to UG583, UltraScale Architecture PCB Design User Guidefor more detail on migrating between UltraScale and UltraScale devices and packages.DS890 (v4.0) March 16, 2021Product Specificationwww.xilinx.com4
UltraScale Architecture and Product Data Sheet: OverviewArtix UltraScale FPGA Feature SummaryTable 3: Artix UltraScale FPGA Feature SummaryAU10PAU15PAU20PAU25PSystem Logic Cells96,250170,100238,437308,437CLB Flip-Flops88,000155,520218,000282,000CLB LUTs44,00077,760109,000141,000Max. Distributed RAM (Mb)1.02.53.24.7Block RAM Blocks100144200300Block RAM (Mb)3.55.17.010.5UltraRAM Blocks––––UltraRAM (Mb)––––CMTs (1 MMCM and 2 PLLs)3334Max. HPI/O(1)156156156208Max. HDI/O(2)727272964005769001,2001111GTH Transceiver 16.375Gb/s(3)1212––GTY Transceivers 16.375Gb/s(3)––1212Transceiver Fractional PLLs––66PCIE4 (PCIe Gen3 x16)––11PCIE4C(PCIe Gen3 x16 / Gen4 x8 / CCIX)(4)11––DSP SlicesSystem MonitorNotes:1.2.3.4.HP High-performance I/O with support for I/O voltage from 1.0V to 1.8V.HD High-density I/O with support for I/O voltage from 1.2V to 3.3V.GTH and GTY transceiver line rates are package limited: SFVB784, SBVB484, and UBVA368 to 12.5Gb/s. See Table 8. 12.5Gb/soperation in UBVA368 package is pending characterization.This block operates in compatibility mode for 16.0GT/s (Gen4) operation. Go to PG213, UltraScale Devices IntegratedBlock for PCI Express Product Guide, for details on compatibility mode.Artix UltraScale Device-Package Combinations and Maximum I/OsTable 4: Artix UltraScale Device-Package Combinations and Maximum I/OsPackage(1)(2)(3)Package Dimensions(mm)AU10PAU15PAU20PAU25PHD I/O, HP I/O, GTH, GTYUBVA36811.5x9.524, 104, 8, 024, 104, 8, 0SBVB48419x1948, 156, 12, 048, 156, 12, 0SFVB78423x23FFVB67627x2772, 156, 12, 072, 156, 12, 072, 156, 0, 1296, 208, 0, 1272, 156, 0, 1272, 208, 0, 12Notes:1. Go to Ordering Information for package designation details.2. FF packages have 1.0mm ball pitch. SB/SF packages have 0.8mm ball pitch. UB packages have 0.5mm ball pitch.3. Packages with the same last letter and number sequence, e.g., B676, are footprint compatible with all other UltraScalearchitecture-based devices with the same sequence. The footprint compatible devices within this family are outlined. See theUltraScale Architecture Product Selection Guide for details on inter-family migration.DS890 (v4.0) March 16, 2021Product Specificationwww.xilinx.com5
UltraScale Architecture and Product Data Sheet: OverviewKintex UltraScale FPGA Feature SummaryTable 5: Kintex UltraScale FPGA Feature m Logic 01,451,100CLB ,2001,326,720CLB 360Maximum Distributed RAM (Mb)4.15.97.09.113.44.718.3Block RAM Blocks3605406001,0801,6201,6802,160Block RAM 048566464208416416520572650676CMTs (1 MMCM, 2 PLLs)I/O DLLsMaximum HPI/Os(2)Maximum ,1007685,520System Monitor1111212PCIe Gen3 x81233446DSP Slices150G Interlaken0000020100G Ethernet0000020121620325632640000032000000160GTH 16.3Gb/s Transceivers(4)GTY 16.3Gb/sTransceivers(5)Transceiver Fractional PLLsNotes:1.2.3.4.5.Certain advanced configuration features are not supported in the KU025. Refer to the Configuring FPGAs section for details.HP High-performance I/O with support for I/O voltage from 1.0V to 1.8V.HR High-range I/O with support for I/O voltage from 1.2V to 3.3V.GTH transceivers in SF/FB packages support data rates up to 12.5Gb/s. See Table 6.GTY transceivers in Kintex UltraScale devices support data rates up to 16.3Gb/s. See Table 6.DS890 (v4.0) March 16, 2021Product Specificationwww.xilinx.com6
UltraScale Architecture and Product Data Sheet: OverviewKintex UltraScale Device-Package Combinations and Maximum I/OsTable 6: Kintex UltraScale Device-Package Combinations and Maximum I/OsKU025KU035KU040KU060KU085KU095KU115HR, HPGTHHR, HPGTHHR, HPGTHHR, HPGTHHR, HPGTHHR, HPGTH, GTY(4)HR, HPGTH23x23104, 3648104, 3648FBVA676(5)27x27104, 20816104, 20816FBVA900(5)31x31104, 36416104, 36416FFVA115635x35104, 41616104, s(mm)SFVA784(5)104, 20812104, 4162852, 46820, 8104, 52032104, 52048104, 5204852, 46820, 20104, 2346452, 65032, 16104, 57244104, 59852156, 67652104, 52056104, 62464156, 6765252, 65032, 32104, 59864Notes:1. Go to Ordering Information for package designation details.2. FB/FF/FL packages have 1.0mm ball pitch. SF packages have 0.8mm ball pitch.3. Packages with the same last letter and number sequence, e.g., A2104, are footprint compatible with all other UltraScalearchitecture-based devices with the same sequence. The footprint compatible devices within this family are outlined. See theUltraScale Architecture Product Selection Guide for details on inter-family migration.4. GTY transceivers in Kintex UltraScale devices support data rates up to 16.3Gb/s.5. GTH transceivers in SF/FB packages support data rates up to 12.5Gb/s.DS890 (v4.0) March 16, 2021Product Specificationwww.xilinx.com7
UltraScale Architecture and Product Data Sheet: OverviewKintex UltraScale FPGA Feature SummaryTable 7: Kintex UltraScale FPGA Feature SummaryKU3PKU5PKU9PKU11PKU13PKU15PKU19PSystem Logic ,842,750CLB ,4401,684,800CLB 400Max. Distributed RAM (Mb)4.76.18.89.111.39.811.6Block RAM Blocks3604809126007449841,728Block RAM (Mb)12.716.932.121.126.234.660.8UltraRAM raRAM (Mb)CMTs (1 MMCM and 2 PLLs)44484119Max. HPI/O(1)208208208416208572468Max. HDI/O(2)96969696969672DSP Slices1,3681,8242,5202,9283,5281,9681,080System Monitor1111111GTH Transceiver 16.3Gb/s00283228440161602003232Transceiver Fractional PLLs881426143816PCIE4 (PCIe Gen3 x16)1104050PCIE4C (PCIe Gen3 x16 / Gen4x8 / CCIX)(4)0000003150G Interlaken0001040100G Ethernet w/RS-FEC0102041GTY Transceivers 32.75Gb/s(3)Notes:1.2.3.4.HP High-performance I/O with support for I/O voltage from 1.0V to 1.8V.HD High-density I/O with support for I/O voltage from 1.2V to 3.3V.GTY transceiver line rates are package limited: SFVB784 to 12.5Gb/s; FFVA676, FFVD900, and FFVA1156 to 16.3Gb/s. SeeTable 8.This block operates in compatibility mode for 16.0GT/s (Gen4) operation. Go to PG213, UltraScale Devices IntegratedBlock for PCI Express Product Guide, for details on compatibility mode.DS890 (v4.0) March 16, 2021Product Specificationwww.xilinx.com8
UltraScale Architecture and Product Data Sheet: OverviewKintex UltraScale Device-Package Combinations and Maximum I/OsTable 8: Kintex UltraScale Device-Package Combinations and Maximum U9PKU11PKU13PKU15PKU19PHD, HPGTH, GTYHD, HPGTH, GTYHD, HPGTH, GTYHD, HPGTH, GTYHD, HPGTH, GTYHD, HPGTH, GTYHD, HPGTH, GTYSFVB784(3)23x2396, 2080, 1696, 2080, 16FFVA676(3)27x2748, 2080, 1648, 2080, 16FFVB67627x2772, 2080, 1672, 2080, 16FFVD900(3)31x3196, 2080, 1696, 2080, 16FFVE90031x31FFVA1156(3)35x3548, 41620, 848, 46820, 8FFVE151740x4096, 41632, 2096, 41632, 24FFVA176042.5x42.596, 41644, 32FFVE176042.5x42.596, 57232, 24FFVJ176042.5x42.572, 4680, 32FFVB210447.5x47.572, 4680, 3296, 31216, 096, 20828, 096, 20828, 0Notes:1.2.3.4.Go to Ordering Information for package designation details.FF packages have 1.0mm ball pitch. SF packages have 0.8mm ball pitch.GTY transceiver line rates are package limited: SFVB784 to 12.5Gb/s; FFVA676, FFVD900, and FFVA1156 to 16.3Gb/s.Packages with the same last letter and number sequence, e.g., A676, are footprint compatible with all other UltraScalearchitecture-based devices with the same sequence. The footprint compatible devices within this family are outlined. Seethe UltraScale Architecture Product Selection Guide for details on inter-family migration.DS890 (v4.0) March 16, 2021Product Specificationwww.xilinx.com9
UltraScale Architecture and Product Data Sheet: OverviewVirtex UltraScale FPGA Feature SummaryTable 9: Virtex UltraScale FPGA Feature SummaryVU065VU080VU095VU125VU160VU190VU440System Logic 9,9005,540,850CLB 02,148,4805,065,920CLB mum Distributed RAM (Mb)Block RAM BlocksBlock RAM (Mb)CMT (1 MMCM, 2 PLLs)10161620283030I/O DLLs40646480120120120Maximum HP I/Os(1)4687807807806506501,404Maximum HR I/Os(2)525252104525252DSP Slices6006727681,2001,5601,8002,880System Monitor1112333PCIe Gen3 x82444466150G Interlaken3666890100G Ethernet3446993GTH 16.3Gb/s Transceivers20323240526048GTY 30.5Gb/s Transceivers2032324052600Transceiver Fractional PLLs1016162026300Notes:1. HP High-performance I/O with support for I/O voltage from 1.0V to 1.8V.2. HR High-range I/O with support for I/O voltage from 1.2V to 3.3V.DS890 (v4.0) March 16, 2021Product Specificationwww.xilinx.com10
UltraScale Architecture and Product Data Sheet: OverviewVirtex UltraScale Device-Package Combinations and Maximum I/OsTable 10: Virtex UltraScale Device-Package Combinations and Maximum VU190VU440Package(1)(2)(3)HR, HPGTH, GTYHR, HPGTH, GTYHR, HPGTH, GTYHR, HPGTH, GTYHR, HPGTH, GTYHR, HPGTH, GTYHR, HPGTH, GTYFFVC151740x4052, 46820, 2052, 46820, 2052, 46820, 20FFVD151740x4052, 28632, 3252, 28632, FLVB210447.5x47.5FLGB210447.5x47.552, 65040, 3652, 65040, 7.552, 36452, 5252, 36452, 52FLGB237750x50FLGA257752.5x52.5FLGA289255x5552, 28640, 3252, 65032, 1652, 65032, 1652, 65036, 1652, 78028, 2452, 78028, 2452, 78028, 2452, 65032, 3252, 65032, 3252, 65040, 3652, 36432, 3252, 36440, 4052, 124836, 00, 44860, 6052, 140448, 0Notes:1.2.3.Go to Ordering Information for package designation details.All packages have 1.0mm ball pitch.Packages with the same last letter and number sequence, e.g., A2104, are footprint compatible with all other UltraScalearchitecture-based devices with the same sequence. The footprint compatible devices within this family are outlined. See theUltraScale Architecture Product Selection Guide for details on inter-family migration.DS890 (v4.0) March 16, 2021Product Specificationwww.xilinx.com11
UltraScale Architecture and Product Data Sheet: OverviewVirtex UltraScale FPGA Feature SummaryTable 11: Virtex UltraScale FPGA Feature 0,0008,937,6002,252,2502,835,0003,780,000CLB B 004,085,7601,029,6001,296,0001,728,000Max. Distributed RAM (Mb)12.018.324.136.136.248.358.414.236.248.3Block RAM ,688Block RAM AM Blocks3204706409609601,2803203529601,280UltraRAM 0––––––––––System Logic CellsHBM DRAM (GB)CMTs (1 MMCM and 2 PLLs)10202030121640111616Max. HP I/O(1)5208328328326248321,976572676676Max. HD ,8401,3209,21612,288DSP SlicesSystem Monitor12233441444080801209612880343232GTM Transceivers 58.0Gb/s000000044848100G / 50G KP4 FEC00000002/424/4824/48GTY Transceivers 32.75Gb/s(3)Transceiver Fractional PLLs20404060486440204040PCIE4 (PCIe Gen3 x16)2446340011PCIE4C (PCIe Gen3 x16 / Gen4 x8 /CCIX)(4)0000008400150G Interlaken3469680088100G Ethernet w/RS-FEC3469912021515Notes:1. HP High-performance I/O with support for I/O voltage from 1.0V to 1.8V.2. HD High-density I/O with support for I/O voltage from 1.2V to 3.3V.3. GTY transceivers in the FLGF1924 package support data rates up to 16.3Gb/s. See Table 12.4.This block operates in compatibility mode for 16.0GT/s (Gen4) operation. Go to PG213, UltraScale Devices Integrated Block for PCI Express Product Guide, fordetails on compatibility mode.DS890 (v4.0) March 16, 2021Product Specificationwww.xilinx.com12
UltraScale Architecture and Product Data Sheet: OverviewVirtex UltraScale Device-Package Combinations and Maximum I/OsTable 12: Virtex UltraScale Device-Package Combinations and Maximum )VU3PVU5PVU7PVU9PVU11PVU13PVU19PVU23PVU27PVU29PHP, GTYHP, GTYHP, GTYHP, GTYHP, GTYHP, GTYHP, HD, GTYHP, HD, GTY, GTMHP, GTY, GTMHP, GTY, GTM676, 16, 30676, 16, 30448, 32, 48448, 32, 48364, 0, 34(7), 4520, 40572, 72, 34, 445x45624, 64FLVA210447.5x47.5832, 52832, 5FSGA257752.5x52.5FSVA382465x651976, 96, 48FSVB382465x651664, 96, 80832, 52832, 52702, 76702, 76702, 76572, 76702, 76416, 80416, 80416, 104416, 96416, 104676, 76572, 76448, 120448, 96676, 76448, 128448, 128Notes:1. Go to Ordering Information for package designation details.2. All packages have 1.0mm ball pitch.3. Packages with the same last letter and number sequence, e.g., A2104, are footprint compatible with all other UltraScale architecture-based devices with the same sequence.The footprint compatible devices within this family are outlined. See the UltraScale Architecture Product Selection Guide for details on inter-family migration.4. Consult UG583, UltraScale Architecture PCB Design User Guide for specific migration details.5. GTY transceivers in the FLGF1924 package support data rates up to 16.3Gb/s.6. These 52.5x52.5mm overhang packages have the same PCB ball footprint as the corresponding 47.5x47.5mm packages (i.e., the same last letter and number sequence) andare footprint compatible.7. GTYs in quads 224-230 and 232 are limited to 16Gb/s.DS890 (v4.0) March 16, 2021Product Specificationwww.xilinx.com13
UltraScale Architecture and Product Data Sheet: OverviewTable 13: Virtex UltraScale HBM FPGA Feature SummaryVU31PVU33PVU35PVU37PVU45PVU47PVU57PSystem Logic 1,8002,851,800CLB 02,607,3602,607,360CLB 1,303,680Max. Distributed RAM (Mb)12.512.524.636.724.636.736.7Block RAM Blocks6726721,3442,0161,3442,0162,016Block RAM (Mb)23.623.647.370.947.370.970.9UltraRAM Blocks320320640960640960960UltraRAM (Mb)90.090.0180.0270.0180.0270.0270.0HBM DRAM (GB)4888161616CMTs (1 MMCM and 2 Max. HPI/O(1)DSP SlicesSystem MonitorGTY Transceivers 32.75Gb/s(2)GTM Transceivers 58.0Gb/s100G / 50G KP4 FEC00000016/3216163248324832PCIE4 (PCIe Gen3 x16)0012120PCIE4C (PCIe Gen3 x16 /Gen4 x8 / CCIX)(3)4444444Transceiver Fractional PLLs150G Interlaken––24244100G Ethernet w/RS-FEC22585810Notes:1. HP High-performance I/O with support for I/O voltage from 1.0V to 1.8V.2. GTY transceivers in the FLGF1924 package support data rates up to 16.3Gb/s. See Table 14.3.This block operates in compatibility mode for 16.0GT/s (Gen4) operation. Go to PG213, UltraScale Devices IntegratedBlock for PCI Express Product Guide, for details on compatibility mode.Virtex UltraScale HBM Device-Package Combinations and Maximum I/OsTable 14: Virtex UltraScale HBM Device-Package Combinations and Maximum VU47PVU57PHP, GTYHP, GTYHP, GTYHP, GTYHP, GTYHP, GTYHP, GTY, GTMFSVH192445x45208, 32FSVH210447.5x47.5208, 32416, , 64416, 64624, 96416, 64624, 96624, 32, 32Notes:1. Go to Ordering Information for package designation details.2. All packages have 1.0mm ball pitch.3. Packages with the same last letter and number sequence, e.g., A2104, are footprint compatible with all other UltraScalearchitecture-based devices with the same sequence. The footprint compatible devices within this family are outlined. See theUltraScale Architecture Product Selection Guide for details on inter-family migration.4. Consult UG583, UltraScale Architecture PCB Design User Guide for specific migration details.DS890 (v4.0) March 16, 2021Product Specificationwww.xilinx.com14
UltraScale Architecture and Product Data Sheet: OverviewZynq UltraScale MPSoC: CG Device Feature SummaryTable 15: Zynq UltraScale MPSoC: CG Device Feature Application Processing UnitDual-core Arm Cortex-A53 MPCore with CoreSight; NEON & Single/Double Precision Floating Point; 32KB/32KB L1 Cache, 1MB L2 CacheReal-Time Processing UnitDual-core Arm Cortex-R5F with CoreSight; Single/Double Precision Floating Point;32KB/32KB L1 Cache, and TCMEmbedded and ExternalMemory256KB On-Chip Memory w/ECC; External DDR4; DDR3; DDR3L; LPDDR4; LPDDR3;External Quad-SPI; NAND; eMMCGeneral Connectivity214 PS I/O; UART; CAN; USB 2.0; I2C; SPI; 32b GPIO; R
UltraScale Architecture and Product Data Sheet: Overview DS890 (v4.0) March 16, 2021 www.xilinx.com Product Specification 4 Configuration, Encryption, and System Monitoring The configuration and encryption block performs numerous device-level functions critical to the successful operation of the FPGA, MPSoC, or RFSoC.
UltraScale Architecture CLB User Guide www.xilinx.com 5 UG574 (v1.5) February 28, 2017 Chapter 1 Overview Introduction to UltraScale Architecture The Xilinx UltraScale architecture is a revo lutionary approach to creating programmable devices capable of addressing the massive I/O and memory bandwidth requirements of
The Xilinx UltraScale architecture DDR3, DDR4, and RLDRAM 3 memory interface cores provide solutions for interfacing with these SDRAM memory types. Both a complete Memory Controller and a physical (PHY) layer only solution are supported. The UltraScale architecture DDR3, DDR4,
UltraScale architecture-based FPGAs support si milar configuration interfaces as the 7 series FPGAs, with most improvements targeted at improving configuration performance. Table 1-1 summarizes the key differences in available configuration modes. Table 1-1: Configuration Modes in UltraScale Architecture-based F
This user guide describes the UltraScale archit ecture DSP Slice resources and is part of the . The UltraScale architecture DSP48E2 slice is backwards compatible with the 7 series FPGA . Designs created for the 25 x 18 multiplier in the 7 series FPGAs . UG57
UltraScale Architecture Memory Resources 7 UG573 (v1.12) March 17, 2021 www.xilinx.com Chapter 1: Block RAM Resources Zynq UltraScale MPSoC devices provide 64-bit processor scalability while combining real-
transceivers in the UltraScale architecture-based devices transfer data up to 58.0Gb/s, enabling 25G backplane designs with dramatically lower power per bit than previous generation transceivers. All transceivers, except the PS-GTR, support the required data rates for 8.0GT/s (Gen3), and 16.0GT/s (Gen4) for PCIe.
PCI Express in the Virtex-5 FPGA family, and its continued use in Virtex-6, Spartan -6, and Xilinx 7 series devices. The Xilinx UltraScale architecture-based devices include the latest generation integrated block for PCI Express within a Xilinx FPGA, including support for up to sixteen lanes (x16) of
Unit 5: American Revolution . 2 A m e r i c a n R e v o l u t i o n Political and Economic Relationships between Great Britain and the Colonies England became Great Britain in the early 1700s, and it was throughout this century that the British colonies in America grew and prospered. The growth of the colonies made it more and more difficult for Great Britain to remain in control. King .
