UltraScale Architecture Configuration User Guide

eFUSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130Device Identifier (Device DNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135Chapter 9: Configuration DetailsIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Configuration Data File Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Configuration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Configuration Bitstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139139143156162Chapter 10: Readback Verification and CRCIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Persist Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Readback Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Verifying Readback Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SEU Detection and Correction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Readback Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178179179189192193Chapter 11: MultiBoot and ReconfigurationIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Fallback MultiBoot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IPROG Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Status Register for Fallback and IPROG Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Dynamic Reconfiguration of Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195195202205206Chapter 12: Configuring Multiple FPGAsIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207Serial Configuration Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207Parallel Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212Chapter 13: Configuration DebuggingIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .File Generation Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Status Pin Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Status Register Use and JTAG Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Verification and Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Configuration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Initial Debug Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216216217218218218219Appendix A: Additional Resources and Legal NoticesXilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221UltraScale Architecture ConfigurationUG570 (v1.16) January 14, 2022www.xilinx.comSend Feedback4

Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UltraScale Architecture ConfigurationUG570 (v1.16) January 14, 2022www.xilinx.comSend Feedback2212222232265

Chapter 1IntroductionIntroduction to the UltraScale ArchitectureThe Xilinx UltraScale architecture is the first ASIC-class programmable architecture toenable multi-hundred gigabit-per-second levels of system performance with smartprocessing, while efficiently routing and processing data on-chip. UltraScalearchitecture-based devices address a vast spectrum of high-bandwidth, high-utilizationsystem requirements by using industry-leading technical innovations, includingnext-generation routing, ASIC-like clocking, 3D-on-3D ICs, multiprocessor SoC (MPSoC)technologies, and new power reduction features. The devices share many building blocks,providing scalability across process nodes and product families to leverage system-levelinvestment across platforms.Virtex UltraScale devices provide the highest performance and integration capabilitiesin a FinFET node, including both the highest serial I/O and signal processing bandwidth, aswell as the highest on-chip memory density. As the industry's most capable FPGA family,the Virtex UltraScale devices are ideal for applications including 1 Tb/s networking anddata center and fully integrated radar/early-warning systems.Virtex UltraScale devices provide the greatest performance and integration at 20 nm,including serial I/O bandwidth and logic capacity. As the industry's only high-end FPGA atthe 20 nm process node, this family is ideal for applications including 400G networking,large scale ASIC prototyping, and emulation.Kintex UltraScale devices provide the best price/performance/watt balance in a FinFETnode, delivering the most cost-effective solution for high-end capabilities, includingtransceiver and memory interface line rates as well as 100G connectivity cores. Our newestmid-range family is ideal for both packet processing and DSP-intensive functions and is wellsuited for applications including wireless MIMO technology, Nx100G networking, and datacenter.Artix UltraScale devices provide high serial bandwidth and signal compute density in acost-optimized device for critical networking applications, vision and video processing, andsecured connectivity. Coupled with the innovative InFO packaging, which provides excellentthermal and power distribution, Artix UltraScale devices are perfectly suited toapplications requiring high compute density in a small footprint.UltraScale Architecture ConfigurationUG570 (v1.16) January 14, 2022www.xilinx.comSend Feedback6

Chapter 1: IntroductionKintex UltraScale devices provide the best price/performance/watt at 20 nm and includethe highest signal processing bandwidth in a mid-range device, next-generationtransceivers, and low-cost packaging for an optimum blend of capability andcost-effectiveness. The family is ideal for packet processing in 100G networking and datacenters applications as well as DSP-intensive processing needed in next-generation medicalimaging, 8k4k video, and heterogeneous wireless infrastructure.Zynq UltraScale MPSoC devices provide 64-bit processor scalability while combiningreal-time control with soft and hard engines for graphics, video, waveform, and packetprocessing. Integrating an Arm -based system for advanced analytics and on-chipprogrammable logic for task acceleration creates unlimited possibilities for applicationsincluding 5G Wireless, next generation ADAS, and Industrial Internet-of-Things.This user guide describes the UltraScale architecture-based FPGAs configuration and is partof the UltraScale architecture documentation suite available at:www.xilinx.com/documentation.OverviewThis chapter provides a brief overview of the configuration methods and features for theUltraScale architecture-based FPGAs. Subsequent chapters provide more detaileddescriptions of each configuration method and feature.Xilinx FPGAs are highly flexible, reprogrammable logic devices. Like processors, XilinxFPGAs are fully user programmable. For FPGAs, the program is called a bitstream, whichdefines the application-specific FPGA functionality. The bitstream loads into the FPGAinternal memory at system power-up or on demand by the system.Like processors and processor peripherals, Xilinx FPGAs can be reprogrammed, in system,on demand, an unlimited number of times. After programming, the FPGA bitstream isstored in highly robust CMOS configuration latches (CCLs). Although CCLs arereprogrammable like SRAM memory, CCLs are designed primarily for data integrity. Becausethe Xilinx FPGA bitstream is stored in CCLs, the device must be reconfigured after it ispower cycled.The process whereby the defining data is loaded or programmed into the FPGA is calledconfiguration. Configuration is designed to be flexible to accommodate differentapplication needs and, wherever possible, to leverage existing system resources tominimize system costs.Similar to processors, Xilinx FPGAs optionally load or boot themselves automatically froman external nonvolatile memory device. Alternatively, similar to processor peripherals, XilinxFPGAs can be downloaded or programmed by an external device, such as a microprocessor,DSP processor, microcontroller, PC, or board tester. The configuration datapath can be serialto minimize pin requirements, including configuration through the industry-standard IEEEUltraScale Architecture ConfigurationUG570 (v1.16) January 14, 2022www.xilinx.comSend Feedback7

Chapter 1: Introduction1149.1 JTAG boundary scan interface. A parallel configuration datapath provides maximumperformance and access to industry-standard interfaces, ideal for external data sources likeprocessors, or x8- or x16-parallel flash memory.The configuration bitstream is loaded into the FPGA through special configuration pins.These configuration pins serve as the interface for a number of different configurationmodes: Slave serial Slave SelectMAP (parallel) (x8, x16, and x32) JTAG boundary scan Master SPI (serial peripheral interface) (serial NOR flash x1, x2, x4, and dual x4,effectively x8) Master BPI (byte peripheral interface) (parallel NOR flash x8 and x16) Master serial Master SelectMAP (parallel) (x8 and x16)The terms master and slave refer to the direction of the configuration clock (CCLK): In master configuration modes, the FPGA drives CCLK from an internal oscillator.Configuration options are used to select the desired frequency. After configuration, theCCLK is turned off by default, and the CCLK pin is 3-stated with a weak pull-up. In slave configuration modes, CCLK is an input.The specific configuration mode is selected by setting the appropriate level on the modeinput pins M[2:0]. The M2, M1, and M0 mode pins should be set at a constant DC voltagelevel, either through pull-up or pull-down resistors ( 1 kΩ ), or tied directly to ground orVCCO 0. The JTAG (boundary scan) configuration interface is always available, regardless ofthe mode pin settings.The configuration modes are explained in detail in Chapter 2 through Chapter 5.The FPGA can also control its own configuration through internal connections from theFPGA logic to the configuration logic. The device can be either fully reprogrammed with analternative design it has selected, or partial reconfiguration allows specific regions of theFPGA to be reprogrammed with new functionality while applications continue to run in theremainder of the device.UltraScale Architecture ConfigurationUG570 (v1.16) January 14, 2022www.xilinx.comSend Feedback8

Chapter 1: IntroductionDifferences Between UltraScale FPGA FamiliesThis document uses the Kintex UltraScale and Virtex UltraScale families as the basis fordescriptions and examples. The following defines some of the differences in the ArtixUltraScale , Kintex UltraScale , and Virtex UltraScale families: Master serial and master SelectMAP configuration modes are not supported in theUltraScale FPGAs. These modes are not recommended in the other UltraScale families. The configuration interface can operate only at 1.8V or 1.5V in the UltraScale FPGAs.There is no CFGBVS pin in UltraScale devices. When migrating from an UltraScaleFPGA to an UltraScale FPGA, the CFGBVS pin location becomes RSVDGND and mustbe connected to GND. The configuration timing and configuration rate options are different betweenUltraScale FPGAs and UltraScale FPGAs. The configuration frame size is 93 32-bitwords in the UltraScale FPGAs and 123 32-bit words in the UltraScale FPGAs.Differences from Previous GenerationsUltraScale architecture-based FPGAs support similar configuration interfaces as the 7 seriesFPGAs, with most improvements targeted at improving configuration performance.Table 1-1 summarizes the key differences in available configuration modes.Table 1-1:FPGAsConfiguration Modes in UltraScale Architecture-based FPGAs Compared to 7 SeriesUltraScaleArchitecture7 SeriesSlave serial modeYesYesSlave SelectMAP modeYesYesJTAG modeYesYesMaster SPI mode (x1, x2, x4)YesYesMaster SPI mode (dual quad, x8)YesNoMaster BPI modeYesYesConfiguration ModeMaster serial modeNotrecommended (1)YesMaster SelectMAP modeNot recommended(1)YesNotes:1. The master SPI and BPI configuration modes are recommended over the legacy masterserial and master SelectMAP modes because they provide a wider flash density selectionand lower cost solution. See Differences Between UltraScale FPGA Families, page 9.UltraScale Architecture ConfigurationUG570 (v1.16) January 14, 2022www.xilinx.comSend Feedback9

Chapter 1: IntroductionThe master configuration modes are optimized to work with standard third-party flashmemories. The SPI mode interfaces to standard x1, x2, or x4 serial NOR flash memories,while the BPI mode interfaces to x8 or x16 parallel NOR flash memories.TIP: The master serial and master SelectMAP configuration modes are supported but not needed formost applications. The 7 series FPGAs supported master serial mode for configuration from legacyserial PROMs or for custom, CPLD-based configuration state machines driven by the FPGA CCLK. Themaster SelectMAP mode has been superseded by the BPI configuration mode for direct configurationfrom parallel flash. See Differences Between UltraScale FPGA Families, page 9.The UltraScale architecture-based FPGAs add a new configuration mode for configuringfrom two quad SPI flash memories in parallel. The resulting x8 configuration reduces theconfiguration time while still allowing for the use of standard, high-speed, low-cost serialNOR configuration memories.This section describes other performance improvements. A higher performance internal configuration clock (CCLK) provides up to double themax frequency with less frequency variation. Because a significant amount of the power-up configuration time can be the power-onreset (POR) delay, the UltraScale architecture-based FPGAs offer a dedicated pin(POR OVERRIDE) that can be set to reduce the delay when the user knows the powersupplies will ramp quickly enough. The internal scanning for configuration bit errors caused by single event upsets (SEU) isalso faster, reducing the time to mitigate an error. A new AES-GCM algorithm for decrypting encrypted bitstreams makes secureconfiguration performance on par with unencrypted configuration. The pin name forthe RAM-based encryption key backup supply is V BATT instead of VCCBATT . The Device DNA unique identifier is increased from 57 bits to 96 bits.The UltraScale architecture-based FPGAs combine RDWR B and FCS B on one pin and moveit into the dedicated configuration bank 0. CSI B and ADV B are combined on another pin.The I/O flexibility is maximized by reducing the number of pins required for configuration.Other configuration pins that were dual-purpose I/O in the 7 series and are dedicated inbank 0 for the UltraScale architecture-based FPGAs include the first four data pins D[03:00]and the control pin for pull-ups during configuration, PUDC B.The UltraScale architecture-based FPGAs use only one I/O bank (bank 65) for multi-functionpins needed for some configuration modes. The pin-outs describe the banks for each pin.Configuration interfaces can be powered at 1.5V, 1.8V, 2.5V, or 3.3V. See ConfigurationBanks Voltage Select (Kintex UltraScale and Virtex UltraScale FPGAs), page 35 for voltageranges supported by mode and by device.UltraScale Architecture ConfigurationUG570 (v1.16) January 14, 2022www.xilinx.comSend Feedback10

Chapter 1: IntroductionThe UltraScale architecture-based FPGAs continue to support the Internal ConfigurationAccess Port (ICAP), providing direct access between FPGA logic and configurationfunctions. The ICAP interface is similar to the SelectMAP interface, and allows user logic toinitiate active reconfiguration. A new Media Configuration Access Port (MCAP) provides asimilar connection to the integrated block for PCI Express. A small initial bitstream can beloaded quickly at power-up to enable the PCIe interface, and then the rest of theconfiguration can be loaded through the PCIe interface - this known as Tandem PCIe.Alternatively, the second part of the configuration can be loaded through the standardconfiguration interfaces - this is known as Tandem PROM. See the UltraScale ArchitectureGen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156) [Ref 1] or theUltraScale Devices Integrated Block for PCI Express Product Guide (PG213) [Ref 2] forinformation on tandem configuration solutions.Chapter 7, Design Entry provides details on the configuration and boundary scancomponents. The following primitives are different than the 7 series primitives: DNA PORTE2 FRAME ECCE3 Adds access to more configuration pins (FCS B and D[03:00])MASTER JTAG Used by Soft Error Mitigation (SEM) IPSTARTUPE3 Used by Soft Error Mitigation (SEM) IPFRAME ECCE4 Extended to 96 bitsNew feature to provide internal, secure access to the JTAG logicCAPTUREE2 No longer supported Use the Vivado Integrated Logic Analyzer to monitor the internal signals of adesign. See Integrated Logic Analyzer Product Guide (PG172) [Ref 3].ICAPE3 Adds additional status signals Supports x32 onlyKU025 DifferencesThe smallest Kintex UltraScale device, the KU025, has a reduced set of configurationfeatures. The KU025 does not support RSA authentication, SEU mitigation (SEM) IP, orpost-configuration CRC.UltraScale Architecture ConfigurationUG570 (v1.16) January 14, 2022www.xilinx.comSend Feedback11

Chapter 1: IntroductionTable 1-2 summarizes the differences between the 7 series and UltraScale families,including the features that are restricted in the Kintex UltraScale KU025 device.Table 1-2:Differences Between FamiliesFeatureArtix UltraScale ,Kintex UltraScale , andVirtex UltraScale Kintex UltraScale andVirtex UltraScale7 SeriesInternal CCLK 100 MHz 100 MHz 100 MHzPOR OVERRIDENoYesYesSEM IPYes, usesFRAME ECCE2Yes (except KU025), faster, usesenhanced FRAME ECCE3Yes, faster, uses enhancedFRAME ECCE4Readback CRCYesNo, use SEM IP instead (SEM IP isnot supported in KU025)No, use SEM IP insteadEncryptionAES-CBCAES-GCM; similar performance tostandard configurationAES-GCM; similar performance tostandard configurationAuthenticationHMACAES-GCM and RSA (except KU025)AES-GCM and RSADevice DNADNA PORT, 57bitsDNA PORTE2, 96 bitsDNA PORT

UltraScale architecture-based FPGAs support si milar configuration interfaces as the 7 series FPGAs, with most improvements targeted at improving configuration performance. Table 1-1 summarizes the key differences in available configuration modes. Table 1-1: Configuration Modes in UltraScale Architecture-based F