Kintex UltraScale FPGAs Data Sheet: DC And AC Switching .
Kintex UltraScale FPGAs Data Sheet:DC and AC Switching CharacteristicsDS922 (v1.3) May 8, 2017Preliminary Product SpecificationSummaryThe Xilinx Kintex UltraScale FPGAs are available in -3, -2, -1 speed grades, with -3E devices havingthe highest performance. The -2LE and -1LI devices can operate at a V CCINT voltage at 0.85V or 0.72V andprovide lower maximum static power. When operated at VCCINT 0.85V, using -2LE and -1LI devices, thespeed specification for the L devices is the same as the -2I or -1I speed grades. When operated atVCCINT 0.72V, the -2LE and -1LI performance and static and dynamic power is reduced.DC and AC characteristics are specified in extended (E) and industrial (I) temperature ranges. Except theoperating temperature range or unless otherwise noted, all the DC and AC electrical parameters are thesame for a particular speed grade (that is, the timing characteristics of a -1 speed grade extended deviceare the same as for a -1 speed grade industrial device). However, only selected speed grades and/ordevices are available in each temperature range.All supply voltage and junction temperature specifications are representative of worst-case conditions.The parameters included are common to popular designs and typical applications.This data sheet, part of an overall set of documentation on the Kintex UltraScale FPGAs, is available onthe Xilinx website at www.xilinx.com/documentation.DC CharacteristicsAbsolute Maximum RatingsTable 1: Absolute Maximum Ratings(1)SymbolDescriptionMinMaxUnitsInternal supply voltage.–0.5001.000VInternal supply voltage for the I/O banks.–0.5001.000VVCCAUXAuxiliary supply voltage.–0.5002.000VVCCBRAMSupply voltage for the block RAM memories.–0.5001.000VOutput drivers supply voltage for HD I/O banks.–0.5003.400VFPGA LogicVCCINTVCCINT IO(2)VCCOOutput drivers supply voltage for HP I/O banks.–0.5002.000VVCCAUX IO(3)Auxiliary supply voltage for the I/O banks.–0.5002.000VVREFInput reference voltage.–0.5002.000V–0.550VCCO 0.550V–0.550VCCO 0.550VVIN(4)(6)(7)I/O input voltage for HD I/Obanks.(5)I/O input voltage for HP I/O banks. Copyright 2015–2017 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks ofXilinx in the United States and other countries.DS922 (v1.3) May 8, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback1
Kintex UltraScale FPGAs Data Sheet: DC and AC Switching CharacteristicsTable 1: Absolute Maximum Ratings(1) (Cont’d)SymbolDescriptionMinMaxUnitsVBATTKey memory battery backup supply.–0.5002.000VIDCAvailable output current at the pad.–2020mAIRMSAvailable RMS output current at the pad.–2020mAGTH or GTY TransceiverVMGTAVCCAnalog supply voltage for transceiver circuits.–0.5001.000VVMGTAVTTAnalog supply voltage for transceiver termination circuits.–0.5001.300VVMGTVCCAUXAuxiliary analog Quad PLL (QPLL) voltage supply r reference clock absolute input voltage.–0.5001.300VVMGTAVTTRCALAnalog supply voltage for the resistor calibration circuit ofthe transceiver column.–0.5001.300VVINReceiver (RXP/RXN) and transmitter (TXP/TXN) absoluteinput voltage.–0.5001.200VIDCIN-FLOATDC input current for receiver input pins DC coupled RXtermination floating.(8)–10mAIDCIN-MGTAVTTDC input current for receiver input pins DC coupled RXtermination VMGTAVTT.–10mAIDCIN-GNDDC input current for receiver input pins DC coupled RXtermination GND.(9)–0mAIDCIN-PROGDC input current for receiver input pins DC coupled RXtermination programmable.(10)–0mAIDCOUT-FLOATDC output current for transmitter pins DC coupled RXtermination floating.–6mAIDCOUT-MGTAVTTDC output current for transmitter pins DC coupled RXtermination VMGTAVTT.–6mASystem MonitorVCCADCSystem Monitor supply relative to GNDADC.0.5002.000VVREFPSystem Monitor reference input relative to GNDADC.0.5002.000VDS922 (v1.3) May 8, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback2
Kintex UltraScale FPGAs Data Sheet: DC and AC Switching CharacteristicsTable 1: Absolute Maximum Ratings(1) (Cont’d)SymbolDescriptionMinMaxUnits–65150 C–260 C–125 CTemperatureTSTGTSOLTjStorage temperature (ambient).Maximum solderingMaximum resses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These arestress ratings only, and functional operation of the device at these or any other conditions beyond those listed underOperating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time mightaffect device reliability.2. VCCINT IO must be connected to VCCBRAM.3. VCCAUX IO must be connected to VCCAUX.4. The lower absolute voltage specification always applies.5. If VCCO is 3.3V, the maximum voltage is 3.4V.6. For I/O operation, see the UltraScale Architecture SelectIO Resources User Guide (UG571).7. When operating outside of the recommended operating conditions, refer to Table 4 and Table 5 for maximum overshootand undershoot specifications.8. AC coupled operation is not supported for RX termination floating.9. For GTY transceivers, DC coupled operation is not supported for RX termination GND.10. DC coupled operation is not supported for RX termination programmable.11. For more information on supported GTH or GTY transceiver terminations see the UltraScale Architecture GTH TransceiverUser Guide (UG576) or UltraScale Architecture GTY Transceiver User Guide (UG578).12. For soldering guidelines and thermal considerations, see the UltraScale and UltraScale FPGAs Packaging and PinoutSpecifications (UG575).Recommended Operating ConditionsTable 2: Recommended Operating ernal supply voltage.0.8250.8500.876VFor -1LI and -2LE devices (VCCINT 0.72V):internal supply voltage.0.6980.7200.742VFor -3E devices: internal supply voltage.0.8730.9000.927VInternal supply voltage for the I/O banks.0.8250.8500.876VFor -1LI and -2LE devices (VCCINT 0.72V):internal supply voltage for the I/O banks.0.8250.8500.876VFor -3E devices: internal supply voltage for the I/O banks.0.8730.9000.927VBlock RAM supply voltage.0.8250.8500.876VFor -3E devices: block RAM supply voltage.0.8730.9000.927VAuxiliary supply voltage.1.7461.8001.854VSupply voltage for HD I/O banks.1.140–3.400VSupply voltage for HP I/O banks.0.950–1.900VAuxiliary I/O supply voltage.1.7461.8001.854V–0.200–VCCO 0.200V––10mA1.000–1.890VFPGA LogicVCCINTVCCINT IO(3)VCCBRAMVCCAUXVCCO(4)(5)VCCAUX IO(6)VIN(7)I/O input voltage.IIN(8)Maximum current through any pin in a powered orunpowered bank when forward biasing the clamp diode.VBATT(9)Battery voltageDS922 (v1.3) May 8, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback3
Kintex UltraScale FPGAs Data Sheet: DC and AC Switching CharacteristicsTable 2: Recommended Operating Conditions(1)(2) (Cont’d)SymbolDescriptionMinTypMaxUnitsGTH or GTY TransceiverVMGTAVCC(10)Analog supply voltage for the GTH or GTY transceiver.0.8730.9000.927VVMGTAVTT(10)Analog supply voltage for the GTH or GTY transmitter andreceiver termination circuits.1.1641.2001.236VVMGTVCCAUX(10)Auxiliary analog QPLL voltage supply for the g supply voltage for the resistor calibration circuit ofthe GTH or GTY transceiver column.1.1641.2001.236VVCCADCSYSMON supply relative to GNDADC.1.7461.8001.854VVREFPSYSMON externally supplied reference voltage relative toGNDADC.1.2001.2501.300VJunction temperature operating range for extended (E)temperature devices.(11)0–100 CJunction temperature operating range for industrial (I)temperature devices.–40–100 CJunction temperature operating range for eFUSEprogramming.(13)–40–125 .11.12.13.All voltages are relative to GND.For the design of the power distribution system consult UltraScale Architecture PCB Design Guide (UG583).VCCINT IO must be connected to VCCBRAM.For VCCO 0, the minimum recommended operating voltage for power on and during configuration is 1.425V. Afterconfiguration, data is retained even if VCCO drops to 0V.Includes VCCO of 1.0V (HP I/O only), 1.2V, 1.35V, 1.5V, 1.8V, 2.5V (HD I/O only) at 5%, and 3.3V (HD I/O only) at 3/–5%.VCCAUX IO must be connected to VCCAUX.The lower absolute voltage specification always applies.A total of 200 mA per bank should not be exceeded.If battery is not used, connect VBATT to either GND or VCCAUX.Each voltage listed requires filtering as described in UltraScale Architecture GTH Transceiver User Guide (UG576) orUltraScale Architecture GTY Transceiver User Guide (UG578).Devices labeled with the speed/temperature grade of -2LE normally operate under Extended (E) temperature gradespecifications with a maximum junction temperature of 100 C. However, E temperature grade devices can operate for a fora limited time at a junction temperature of 110 C. Timing parameters adhere to the same speed file at 110 C as they doat 100 C, regardless of operating voltage (nominal voltage of 0.85V or a low-voltage of 0.72V). Operation at Tj 110 Cis limited to 1% of the device lifetime and can occur sequentially or at regular intervals as long as the total time does notexceed 1% of the device lifetime.Xilinx recommends measuring the Tj of a device using the system monitor as described in the UltraScale ArchitectureSystem Monitor User Guide (UG580). The SYSMON temperature measurement errors (that are described in Table 76) mustbe accounted for in your design. For example, by using an external reference of 1.25V, when SYSMON reports 97 C, thereis a measurement error 3 C. A reading of 97 C is considered the maximum adjusted Tj (100 C – 3 C 97 C).Do not program eFUSE during device configuration (e.g., during configuration, during configuration readback, or whenreadback CRC is active).DS922 (v1.3) May 8, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback4
Kintex UltraScale FPGAs Data Sheet: DC and AC Switching CharacteristicsDC Characteristics Over Recommended Operating ConditionsTable 3: DC Characteristics Over Recommended Operating Data retention VCCINT voltage (below which configurationdata might be lost).0.68––VVDRAUXData retention VCCAUX voltage (below which configurationdata might be lost).1.5––VIREFVREF leakage current per pin.––15µA––15µADie input capacitance at the pad (HP I/O).––3.1pFDie input capacitance at the pad (HD I/O).––4.75pFPad pull-up (when selected) at VIN 0V, VCCO 3.3V.75–190µAPad pull-up (when selected) at VIN 0V, VCCO 2.5V.50–169µAPad pull-up (when selected) at VIN 0V, VCCO 1.8V.60–120µAPad pull-up (when selected) at VIN 0V, VCCO 1.5V.30–120µAPad pull-up (when selected) at VIN 0V, VCCO 1.2V.10–100µAPad pull-down (when selected) at VIN 3.3V.60–200µAPad pull-down (when selected) at VIN 1.8V.29–120µAILCIN(3)IRPUIRPDInput or output leakage current per pin(sample-tested).(2)ICCADCONAnalog supply current for the SYSMON circuits in thepower-up state.––8mAICCADCOFFAnalog supply current for the SYSMON circuits in thepower-down state.––1.5mABattery supply current at VBATT 1.89V.––650nABattery supply current at VBATT 1.20V.––150nAVCCAUX additional supply current during eFUSE d programmable on-die termination (DCI) in HP I/O banks(7) (measured per JEDEC specification).R(9)Thevenin equivalent resistance of programmable inputtermination to VCCO/2 where ODT RTT 40.–10%(8)40 10%(8)ΩThevenin equivalent resistance of programmable inputtermination to VCCO/2 where ODT RTT 48.–10%(8)48 10%(8)ΩThevenin equivalent resistance of programmable inputtermination to VCCO/2 where ODT RTT 60.–10%(8)60 10%(8)ΩProgrammable input termination to VCCO whereODT RTT 40.–10%(8)40 10%(8)ΩProgrammable input termination to VCCO whereODT RTT 48.–10%(8)48 10%(8)ΩProgrammable input termination to VCCO whereODT RTT 60.–10%(8)60 10%(8)ΩProgrammable input termination to VCCO whereODT RTT 120.–10%(8)120 10%(8)ΩProgrammable input termination to VCCO whereODT RTT 240.–10%(8)240 10%(8)ΩDS922 (v1.3) May 8, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback5
Kintex UltraScale FPGAs Data Sheet: DC and AC Switching CharacteristicsTable 3: DC Characteristics Over Recommended Operating Conditions brated programmable on-die termination in HP I/O banks (measured per JEDEC specification).R(9)Thevenin equivalent resistance of programmable inputtermination to VCCO/2 where ODT RTT 40.–50%40 50%ΩThevenin equivalent resistance of programmable inputtermination to VCCO/2 where ODT RTT 48.–50%48 50%ΩThevenin equivalent resistance of programmable inputtermination to VCCO/2 where ODT RTT 60.–50%60 50%ΩProgrammable input termination to VCCO whereODT RTT 40.–50%40 50%ΩProgrammable input termination to VCCO whereODT RTT 48.–50%48 50%ΩProgrammable input termination to VCCO whereODT RTT 60.–50%60 50%ΩProgrammable input termination to VCCO whereODT RTT 120.–50%120 50%ΩProgrammable input termination to VCCO whereODT RTT 240.–50%240 50%ΩUncalibrated programmable on-die termination in HD I/O banks (measured per JEDEC specification).Thevenin equivalent resistance of programmable inputtermination to VCCO/2 where ODT RTT 48.–50%48 50%Ω50% VCCOVCCO x0.49VCCO x0.50VCCO x0.51V70% VCCOVCCO x0.69VCCO x0.70VCCO x0.71VDifferentialterminationProgrammable differential termination (TERM 100)for HP I/O banks.–35%100 35%ΩnTemperature diode ideality factor.–1.026––rTemperature diode series resistance.–2–ΩR(9)Internal VREFNotes:1.2.3.4.5.6.7.8.9.Typical values are specified at nominal voltage, 25 C.For HP I/O banks with a VCCO of 1.8V and separated VCCO and VCCAUX IO power supplies, the IL maximum current is 70 µA.This measurement represents the die capacitance at the pad, not including the package.Maximum value specified for worst case process at 25 C.IBATT is measured when the battery-backed RAM (BBRAM) is enabled.Do not program eFUSE during device configuration (e.g., during configuration, during configuration readback, or whenreadback CRC is active).If VRP resides at a different bank (DCI cascade), the range increases to 15%.VRP resistor tolerance is (240Ω 1%)On-die input termination resistance, for more information see the UltraScale Architecture SelectIO Resources User Guide(UG571).DS922 (v1.3) May 8, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback6
Kintex UltraScale FPGAs Data Sheet: DC and AC Switching CharacteristicsVIN Maximum Allowed AC Voltage Overshoot and UndershootTable 4: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HD I/O Banks(1)AC Voltage Overshoot % of UI at –40 C to 100 C AC Voltage Undershoot % of UI at –40 C to 100 CVCCO 0.30100%–0.30100%VCCO 0.35100%–0.3590%VCCO 0.40100%–0.4078%VCCO 0.45100%–0.4540%VCCO 0.50100%–0.5024%VCCO 0.55100%–0.5518.0%VCCO 0.60100%–0.6013.0%VCCO 0.65100%–0.6510.8%VCCO 0.7092%–0.709.0%VCCO 0.7592%–0.757.0%VCCO 0.8092%–0.806.0%VCCO 0.8592%–0.855.0%VCCO 0.9092%–0.904.0%VCCO 0.9592%–0.952.5%Notes:1.A total of 200 mA per bank should not be exceeded.Table 5: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HP I/O Banks(1)(2)AC Voltage Overshoot % of UI at –40 C to 100 C AC Voltage Undershoot % of UI at –40 C to 100 CVCCO 0.30100%–0.30100%VCCO 0.35100%–0.3590%VCCO 0.4092%–0.4092%VCCO 0.4550%–0.4550%VCCO 0.5020%–0.5020%VCCO 0.5510%–0.5510%VCCO 0.606%–0.606%VCCO 0.652%–0.652%VCCO 0.702%–0.702%Notes:1.2.A total of 200 mA per bank should not be exceeded.For UI smaller than 20 µs.DS922 (v1.3) May 8, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback7
Kintex UltraScale FPGAs Data Sheet: DC and AC Switching CharacteristicsQuiescent Supply CurrentTable 6: Typical Quiescent Supply Current(1)(2)(3)SymbolICCINTQICCINT IOQICCOQICCAUXQICCAUX IOQICCBRAMQDescriptionQuiescent VCCINT supply current.Quiescent VCCINT IO supply current.Quiescent VCCO supply current.Quiescent VCCAUX supply current.Quiescent VCCAUX IO supply current.Quiescent VCCBRAM supply current.DeviceSpeed Grade andVCCINT Operating All devicesNotes:1.2.3.Typical values are specified at nominal voltage, 85 C junction temperatures (Tj) with single-ended SelectIO resources.Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pinsare 3-state and floating.Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) to estimate static powerconsumption for conditions other than those specified.DS922 (v1.3) May 8, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback8
Kintex UltraScale FPGAs Data Sheet: DC and AC Switching CharacteristicsPower-On/Off Power Supply SequencingThe recommended power-on sequence is VCCINT , VCCINT IO/VCCBRAM, VCCAUX/VCCAUX IO, and VCCO toachieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommendedpower-off sequence is the reverse of the power-on sequence. If V CCINT and V CCINT IO/V CCBRAM have thesame recommended voltage levels, they can be powered by the same supply and ramped simultaneously.VCCINT IO must be connected to VCCBRAM. If VCCAUX/VCCAUX IO and V CCO have the same recommendedvoltage levels, they can be powered by the same supply and ramped simultaneously. V CCAUX and VCCAUX IOmust be connected together. VCCADC and VREF can be powered at any time and have no power-upsequencing requirements.The recommended power-on sequence to achieve minimum current draw for the GTH or GTY transceiversis V CCINT, VMGTAVCC, V MGTAVTT OR V MGTAVCC, VCCINT, VMGTAVTT. There is no recommended sequencing forVMGTVCCAUX. Both VMGTAVCC and VCCINT can be ramped simultaneously. The recommended power-offsequence is the reverse of the power-on sequence to achieve minimum current draw.If these recommended sequences are not met, current drawn from V MGTAVTT can be higher thanspecifications during power-up and power-down.DS922 (v1.3) May 8, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback9
Kintex UltraScale FPGAs Data Sheet: DC and AC Switching CharacteristicsPower Supply RequirementsTable 7 shows the minimum current, in addition to ICCQ maximum, required by each Kintex UltraScale FPGA for proper power-on and configuration. If the current minimums shown in Table 7 are met, thedevice powers on after all supplies have passed through their power-on reset threshold voltages. Thedevice must not be configured until after VCCINT is applied. Once initialized and configured, use the XilinxPower Estimator (XPE) tools to estimate current drain on these supplies.Table 7: Power-on Current by Device(1)DeviceICCINTMINICCINT IOMIN ICCBRAMMINICCOMINICCAUXMIN ICCAUX IOMIN UnitsXCKU3PICCINTQ 770ICCBRAMQ ICCINT IOQ 229ICCOQ 50ICCAUXQ ICCAUX IOQ 386mAXCKU5PICCINTQ 770ICCBRAMQ ICCINT IOQ 305ICCOQ 50ICCAUXQ ICCAUX IOQ 515mAXCKU9PICCINTQ 1800ICCBRAMQ ICCINT IOQ 600ICCOQ 50ICCAUXQ ICCAUX IOQ 650mAXCKU11PICCINTQ 1961ICCBRAMQ ICCINT IOQ 654ICCOQ 55ICCAUXQ ICCAUX IOQ 709mAXCKU13PICCINTQ 2242ICCBRAMQ ICCINT IOQ 748ICCOQ 63ICCAUXQ ICCAUX IOQ 810mAXCKU15PICCINTQ 3433ICCBRAMQ ICCINT IOQ 1145ICCOQ 96ICCAUXQ ICCAUX IOQ 1240mANotes:1.Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) to estimate power-on currentfor all supplies.Table 8 shows the power supply ramp time.Table 8: Power Supply Ramp TimeSymbolDescriptionMinMaxUnitsTVCCINTRamp time from GND to 95% of VCCINT.0.240msTVCCINT IORamp time from GND to 95% of VCCINT IO.0.240msTVCCORamp time from GND to 95% of VCCO.0.240msTVCCAUXRamp time from GND to 95% of VCCAUX.0.240msTVCCBRAMRamp time from GND to 95% of VCCBRAM.0.240msTMGTAVCCRamp time from GND to 95% of VMGTAVCC.0.240msTMGTAVTTRamp time from GND to 95% of VMGTAVTT.0.240msTMGTVCCAUXRamp time from GND to 95% of VMGTVCCAUX.0.240msDS922 (v1.3) May 8, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback10
Kintex UltraScale FPGAs Data Sheet: DC and AC Switching CharacteristicsDC Input and Output LevelsValues for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over therecommended operating conditions at the VOL and V OH test points. Only selected standards are tested.These are chosen to ensure that all standards meet their specifications. The selected standards are testedat a minimum V CCO with the respective VOL and VOH voltage levels shown. Other standards are sampletested.Table 9: SelectIO DC Input and Output Levels For HD I/O Banks(1)(2)(3)I/OStandardVILV, MinV, MaxVIHV, MinV, MaxVOLVOHIOLIOHV, MaxV, MinmAmAHSTL I–0.300 VREF – 0.100 VREF 0.100 VCCO 0.3000.400VCCO – 0.4008.0–8.0HSTL I 18–0.300 VREF – 0.100 VREF 0.100 VCCO 0.3000.400VCCO – 0.4008.0–8.0HSUL 12–0.300 VREF – 0.130 VREF 0.130 VCCO 0.30020% VCCO80% VCCO0.1–0.1LVCMOS12–0.30035% VCCO65% VCCOVCCO 0.3000.400VCCO – 0.400Note 4Note 4LVCMOS15–0.30035% VCCO65% VCCOVCCO 0.3000.450VCCO – 0.450Note 5Note 5LVCMOS18–0.30035% VCCO65% VCCOVCCO 0.3000.450VCCO – 0.450Note 5Note 5LVCMOS25–0.3000.7001.700VCCO 0.3000.400VCCO – 0.400Note 5Note 5LVCMOS33–0.3000.8002.0003.4000.400VCCO – 0.400Note 5Note 5LVTTL–0.3000.8002.0003.4000.4002.400Note 5Note 5SSTL12–0.300 VREF – 0.100 VREF 0.100 VCCO 0.300 VCCO/2 – 0.150 VCCO/2 0.15014.25–14.25SSTL135–0.300 VREF – 0.090 VREF 0.090 VCCO 0.300 VCCO/2 – 0.150 VCCO/2 0.1508.9–8.9SSTL135 II–0.300 VREF – 0.090 VREF 0.090 VCCO 0.300 VCCO/2 – 0.150 VCCO/2 0.15013.0–13.0SSTL15–0.300 VREF – 0.100 VREF 0.100 VCCO 0.300 VCCO/2 – 0.175 VCCO/2 0.1758.9–8.9SSTL15 II–0.300 VREF – 0.100 VREF 0.100 VCCO 0.300 VCCO/2 – 0.175 VCCO/2 0.17513.0–13.0SSTL18 I–0.300 VREF – 0.125 VREF 0.125 VCCO 0.300 VCCO/2 – 0.470 VCCO/2 0.4708.0–8.0SSTL18 II–0.300 VREF – 0.125 VREF 0.125 VCCO 0.300 VCCO/2 – 0.600 VCCO/2 0.60013.4–13.4Notes:1.2.3.4.5.Tested according to relevant specifications.Standards specified using the default I/O standard configuration. For details, see the UltraScale ArchitectureSelectIO Resources User Guide (UG571).POD10 and POD12 DC input and output levels are shown in Table 11, Table 15, Table 16, and Table 17.Supported drive strengths of 4, 8, or 12 mA in HD I/O banks.Supported drive strengths of 4, 8, 12, or 16 mA in HD I/O banks.DS922 (v1.3) May 8, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback11
Kintex UltraScale FPGAs Data Sheet: DC and AC Switching CharacteristicsTable 10: SelectIO DC Input and Output Levels for HP I/O Banks(1)(2)(3)I/OStandardVIHVILV, MinV, MaxV, MinV, MaxVOLVOHIOLIOHV, MaxV, MinmAmAHSTL I–0.300 VREF – 0.100 VREF 0.100 VCCO 0.3000.400VCCO – 0.4005.8–5.8HSTL I 12–0.300 VREF – 0.080 VREF 0.080 VCCO 0.30025% VCCO75% VCCO4.1–4.1HSTL I 18–0.300 VREF – 0.100 VREF 0.100 VCCO 0.3000.400VCCO – 0.4006.2–6.2HSUL 12–0.300 VREF – 0.130 VREF 0.130 VCCO 0.30020% VCCO80% VCCO0.1–0.1LVCMOS12–0.30035% VCCO65% VCCOVCCO 0.3000.400VCCO – 0.400Note 4 Note 4LVCMOS15–0.30035% VCCO65% VCCOVCCO 0.3000.450VCCO – 0.450Note 5 Note 5LVCMOS18–0.30035% VCCO65% VCCOVCCO 0.3000.450VCCO – 0.450Note 5 Note 5LVDCI 15–0.30035% VCCO65% VCCOVCCO 0.3000.450VCCO – 0.4507.0–7.0LVDCI 18–0.30035% VCCO65% VCCOVCCO 0.3000.450VCCO – 0.4507.0–7.0SSTL12–0.300 VREF – 0.100 VREF 0.100 VCCO 0.300 VCCO/2 – 0.150 VCCO/2 0.1508.0–8.0SSTL135–0.300 VREF – 0.090 VREF 0.090 VCCO 0.300 VCCO/2 – 0.150 VCCO/2 0.1509.0–9.0SSTL15–0.300 VREF – 0.100 VREF 0.100 VCCO 0.300 VCCO/2 – 0.175 VCCO/2 0.17510.0–10.0SSTL18 I–0.300 VREF – 0.125 VREF 0.125 VCCO 0.300 VCCO/2 – 0.470 VCCO/2 0.4707.0–7.0MIPI DPHYDCI LP(6)–0.3000.01–0.010.5500.880VCCO 0.3000.0501.100Notes:1.2.3.4.5.6.Tested according to relevant specifications.Standards specified using the default I/O standard configuration. For details, see the UltraScale ArchitectureSelectIO Resources User Guide (UG571).POD10 and POD12 DC input and output levels are shown in Table 11, Table 15, Table 16, and Table 17.Supported drive strengths of 2, 4, 6, or 8 mA in HP I/O banks.Supported drive strengths of 2, 4, 6, 8, or 12 mA in HP I/O banks.Low-power option for MIPI DPHY DCI.Table 11: DC Input Levels for Single-ended POD10 and POD12 I/O Standards(1)(2)I/OStandardVILVIHV, MinV, MaxV, MinV, MaxPOD10–0.300VREF – 0.068VREF 0.068VCCO 0.300POD12–0.300VREF – 0.068VREF 0.068VCCO 0.300Notes:1.2.Tested according to relevant specifications.Standards specified using the default I/O standard configuration. For details, see the UltraScale ArchitectureSelectIO Resources User Guide (UG571).DS922 (v1.3) May 8, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback12
Kintex UltraScale FPGAs Data Sheet: DC and AC Switching CharacteristicsTable 12: Differential SelectIO DC Input and Output LevelsVICM (V)(1)I/OStandardMinTypMaxVILHS(3) VIHHS(3)VID(V)(2)MinTyp MaxSUB LVDS(8)0.500 0.900 1.300 0.070LVPECL0.300 1.200 1.425 0.100 0.350 pMax––––––––––0.700 0.900 1.100 0.100 0.150 0.200SLVS 400 18 0.070 0.200 0.330 0.140–0.450––––––––SLVS 400 25 0.070 0.200 0.330 0.140–0.450––––––––MIPI DPHYDCI HS(9)–––0.0400.4600.070–0.330 0.0700.150 0.200 0.250 0.140 0.200 0.270Notes:1.2.3.4.5.6.7.8.9.VICM is the input common mode voltage.VID is the input differential voltage (Q – Q).VIHHS and VILHS are the single-ended input high and low voltages, respectively.VOCM is the output common mode voltage.VOD is the output differential voltage (Q – Q).LVDS 25 is specified in Table 18.LVDS is specified in Table 19.Only the SUB LVDS receiver is supported in HD I/O banks.High-speed option for MIPI DPHY DCI. The VID maximum is aligned with the standard’s specification. A higher VID isacceptable as long as the VIN specification is also met.Table 13: Complementary Differential SelectIO DC Input and Output Levels for HD I/O BanksI/O StandardVICM (V)(1)MinTypMaxVID (V)(2)MinVOL (V)(3)VOH (V)(4)IOLIOHMaxMaxMinmAmADIFF HSTL I0.300 0.750 1.125 0.100–0.400VCCO – 0.4008.0–8.0DIFF HSTL I 180.300 0.900 1.425 0.100–0.400VCCO – 0.4008.0–8.0DIFF HSUL 120.300 0.600 0.850 0.100–20% VCCO80% VCCO0.1–0.1DIFF SSTL120.300 0.600 0.850 0.100–(VCCO/2) – 0.150 (VCCO/2) 0.15014.25–14.25DIFF SSTL1350.300 0.675 1.000 0.100–(VCCO/2) – 0.150 (VCCO/2) 0.1508.9–8.9DIFF SSTL135 II0.300 0.675 1.000 0.100–(VCCO/2) – 0.150 (VCCO/2) 0.15013.0–13.0DIFF SSTL150.300 0.750 1.125 0.100–(VCCO/2) – 0.175 (VCCO/2) 0.1758.9–8.9DIFF SSTL15 II0.300 0.750 1.125 0.100–(VCCO/2) – 0.175 (VCCO/2) 0.17513.0–13.0DIFF SSTL18 I0.300 0.900 1.425 0.100–(VCCO/2) – 0.470 (VCCO/2) 0.4708.0–8.0DIFF SSTL18 II0.300 0.900 1.425 0.100–(VCCO/2) – 0.600 (VCCO/2) 0.60013.4–13.4Notes:1.2.3.4.VICM is the input common mode voltage.VID is the input differential voltage.VOL is the single-ended low-output voltage.VOH is the single-ended high-output voltage.DS922 (v1.3) May 8, 2017Preliminary Product Specificationwww.xilinx.comSend Feedback13
Kintex UltraScale FPGAs Data Sheet: DC and AC Switching CharacteristicsTable 14: Complementary Differential SelectIO DC Input and Output Levels for HP I/O Banks(1)VOL (V)(4)VOH (V)(5)IOL IOHMaxMaxMinmA mAVCCO/2 (VCCO/2) 0.150 0.100–0.400VCCO – 0.4005.8–5.8VCCO/20.100–0.250 x VCCO0.750 x VCCO4.1–4.1DIFF HSTL I 18(VCCO/2) – 0.175 VCCO/2 (VCCO/2) 0.175 0.100–0.400VCCO – 0.4006.2–6.2DIFF HSUL 12(VCCO/2) – 0.120 VCCO/2 (VCCO/2) 0.120 0.100–20% VCCO80% VCCO0.1–0.1DIFF SSTL12(VCCO/2) – 0.150 VCCO/2 (VCCO/2) 0.150 0.100–(VCCO/2) – 0.150 (VCCO/2) 0.1508.0–8.0DIFF SSTL135(VCCO/2) – 0.150 VCCO/2 (VCCO/2) 0.150 0.100–(VCCO/2) – 0.150 (VCCO/2) 0.1509.0–9.0DIFF SSTL15(VCCO/2) – 0.175 VCCO/2 (VCCO/2) 0.175 0.100–(VCCO/2) – 0.175 (VCCO/2) 0.175 10.0 –10.0DIFF SSTL18 I(VCCO/2) – 0.175 VCCO/2 (VCCO/2) 0.175 0.100–(VCCO/2) – 0.470 (VCCO/2) 0.470I/O StandardDIFF HSTL IVICM (V)(2)Min0.680DIFF HSTL I 120.400 x VCCOTypVID (V)(3)Max0.600 x VCCOMin7.0–7.0Notes:1.2.3.4.5.DIFF POD10 and DIFF POD12 HP I/O bank specifications are shown in Table 15, Table 16, and Table 17.VICM is the input common mode voltage.VID is the input differential voltage.VOL is the single-ended low-output voltage.VOH is the single-ended high-output voltage.Table 15: DC Input Levels for Differential POD10 and POD12 I/O Standards(1)(2)I/O StandardVICM (V)VID (V)MinTypMaxMinMaxDIFF POD100.630.700.770.14–DIFF POD120.760.840.920.16–Notes:1.2.Tested according to relevant specifications.Standards specified using the default I/O standard configuration. For details, see the UltraScale ArchitectureSelectIO Resources User Guide (UG571).Table 16: DC Output Levels for Single-ended and Differential POD10 and POD12 ROLPull-down resistance.VOM DC (as described in Table 17)364044ΩROHPull-up resistance.VOM DC (as described in Table 17)364044ΩNotes:1.2.Tested according to relevant specifications.Standards specified using the default I/O standard configuration. For details, see the UltraScale ArchitectureSelectIO Resources User Guide (UG571).Table 17: Table 16 Definitions for DC Output Levels for POD StandardsSymbolVOM DC
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