Xilinx DS182 Kintex-7 FPGAs Data Sheet: DC And Switching .
Kintex-7 FPGAs Data Sheet:DC and Switching CharacteristicsDS182 (v1.4) February 13, 2012Advance Product SpecificationKintex-7 FPGA Electrical CharacteristicsKintex -7 FPGAs are available in -3, -2, -1, and -2L speedgrades, with -3 having the highest performance. The -2Ldevices can operate at either of two VCCINT voltages, 0.9Vand 1.0V and are screened for lower maximum static power.When operated at VCCINT 1.0V, the speed specification ofa -2L device is the same as the -2 speed grade. Whenoperated at VCCINT 0.9V, the -2L performance and staticand dynamic power is reduced.Kintex-7 FPGA DC and AC characteristics are specified incommercial, extended, and industrial temperature ranges.Except the operating temperature range or unlessotherwise noted, all the DC and AC electrical parametersare the same for a particular speed grade (that is, the timingcharacteristics of a -1 speed grade industrial device are thesame as for a -1 speed grade commercial device). However,only selected speed grades and/or devices are available ineach temperature range.All supply voltage and junction temperature specificationsare representative of worst-case conditions. Theparameters included are common to popular designs andtypical applications.This Kintex-7 FPGA data sheet, part of an overall set ofdocumentation on the 7 series FPGAs, is available on theXilinx website at www.xilinx.com/7.All specifications are subject to change without notice.Kintex-7 FPGA DC CharacteristicsTable 1: Absolute Maximum Ratings (1)SymbolDescriptionUnitsVCCINTInternal supply voltage relative to GND–0.5 to 1.1VVCCAUXAuxiliary supply voltage relative to GND–0.5 to 2.0VVCCAUX IOAuxiliary supply voltage relative to GND–0.5 to 2.06VOutput drivers supply voltage relative to GND for 3.3V HR I/O banks–0.5 to 3.6VOutput drivers supply voltage relative to GND for 1.8V HP I/O banks–0.5 to 2.0VVCCBRAMSupply voltage for the block RAM memories–0.5 to 1.1VVCCADCXADC supply relative to GNDADC–0.5 to 2.0VVCCBATTKey memory battery backup supply–0.5 to 2.0VVREFInput reference voltage–0.5 to 2.0VVREFPXADC reference input relative to GNDADC–0.5 to 2.0Vand dedicated I/Os)–0.5 to VCCO 0.5Voutput(3)–0.5 to VCCO 0.5V–65 to 150 C 220 C 125 CVCCOVIN(2)I/O input voltage relative toGND(3) (userVTSVoltage applied to 3-state 1.8V or belowTSTGStorage temperature (ambient)TSOLMaximum solderingMaximum junctionTj(user and dedicated esses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.The 3.3V and 1.8V I/O absolute maximum limit applied to DC and AC signals.For I/O operation, refer to UG471: 7 Series FPGAs SelectIO Resources User Guide.For soldering guidelines and thermal considerations, see UG475: 7 Series FPGA Packaging and Pinout Specification. 2011–2012 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Kintex, Artix, Zynq, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the UnitedStates and other countries. All other trademarks are the property of their respective owners.DS182 (v1.4) February 13, 2012Advance Product Specificationwww.xilinx.com1
Kintex-7 FPGAs Data Sheet: DC and Switching CharacteristicsTable 2: Recommended Operating Conditions (1)SymbolMinMaxUnitsInternal supply voltage relative to GND0.971.03VFor -2L (0.9V) devices: internal supply voltage relative to GND0.870.93VAuxiliary supply voltage relative to GND1.711.89VAuxiliary supply voltage when set to 1.8V relative to GND1.711.89VAuxiliary supply voltage when set to 2.0V relative to GND1.942.06VSupply voltage for 3.3V HR I/O banks relative to GND1.143.465VSupply voltage for 1.8V HP I/O banks relative to GND1.141.89VVCCBRAMBlock RAM supply voltage0.971.03VVCCBATT(3)Battery voltage relative to GND1.01.98VVINI/O input voltage relative to GNDGND – 0.20VCCO 0.2VIIN(5)Maximum current through any pin in a powered or unpowered bank when forwardbiasing the clamp diode.–10mAJunction temperature operating range for commercial (C) temperature devices085 CJunction temperature operating range for extended (E) temperature devices0100 CJunction temperature operating range for industrial (I) temperature devices–40100 CVCCINTVCCAUXVCCAUX IOVCCO(2)(4)TjDescriptionNotes:1.2.3.4.5.All voltages are relative to ground.Configuration data is retained even if VCCO drops to 0V.VCCBATT is required only when using bitstream encryption. If battery is not used, connect VCCBATT to either ground or VCCAUX.Includes VCCO of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V.A total of 100 mA per bank should not be exceeded.DS182 (v1.4) February 13, 2012Advance Product Specificationwww.xilinx.com2
Kintex-7 FPGAs Data Sheet: DC and Switching CharacteristicsTable 3: DC Characteristics Over Recommended Operating Data retention VCCINT voltage (below which configuration data might be lost)0.75––VVDRIData retention VCCAUX voltage (below which configuration data might be lost)1.5––VIREFVREF leakage current per pin15µAILInput or output leakage current per pin (sample-tested)15µACIN(2)Die input capacitance at the pad8pFPad pull-up (when selected) @ VIN 0V, VCCO 3.3V330µAPad pull-up (when selected) @ VIN 0V, VCCO 2.5V250µAPad pull-up (when selected) @ VIN 0V, VCCO 1.8V180µAPad pull-up (when selected) @ VIN 0V, VCCO 1.5V150µAPad pull-up (when selected) @ VIN 0V, VCCO 1.2V120µAPad pull-down (when selected) @ VIN 3.3V330µAPad pull-down (when selected) @ VIN 1.8V180µABattery supply current150nA1.0002–2 IRPUIRPDIBATT(3)nTemperature diode ideality factorrSeries resistanceNotes:1.2.3.Typical values are specified at nominal voltage, 25 C.This measurement represents the die capacitance at the pad, not including the package.Maximum value specified for worst case process at 25 C.Static Power ConsumptionTable 4: Typical Quiescent Supply CurrentSpeed scent VCCINT supply currentQuiescent VCCO supply currentDS182 (v1.4) February 13, 2012Advance Product AXC7K420TmAXC7K480TmAwww.xilinx.com3
Kintex-7 FPGAs Data Sheet: DC and Switching CharacteristicsTable 4: Typical Quiescent Supply Current (Cont’d)Speed GradeSymbolDescriptionDevice1.0V-3ICCAUXQQuiescent VCCAUX supply currentQuiescent VCCBRAM supply 355TmAXC7K410TmAXC7K420TmAXC7K480TmAICCAUX IOQ Quiescent VCCAUX IO supply current 480TmANotes:1.2.3.Typical values are specified at nominal voltage, 85 C junction temperatures (Tj) with single-ended SelectIO resources.Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state andfloating.Use the XPower Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate static power consumption forconditions other than those specified.DS182 (v1.4) February 13, 2012Advance Product Specificationwww.xilinx.com4
Kintex-7 FPGAs Data Sheet: DC and Switching CharacteristicsPower-On/Off Power Supply SequencingThe recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, VCCAUX IO, and VCCO to achieve minimum currentdraw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the poweron sequence. If VCCINT and VCCBRAM have the same recommended voltage levels then both can be powered by the samesupply and ramped simultaneously. If VCCAUX, VCCAUX IO, and VCCO have the same recommended voltage levels then theycan be powered by the same supply and ramped simultaneously.For VCCO voltages of 3.3V in HR I/O banks and configuration bank 0: The voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for eachpower-on/off cycle to maintain device reliability levels. The TVCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps.There are no sequencing requirements for the GTX transceiver supplies with respect to the other FPGA supply voltages.Table 5 shows the minimum current, in addition to ICCQ, that are required by Kintex-7 devices for proper power-on andconfiguration. If the current minimums shown in Table 4 and Table 5 are met, the device powers on after all five supplies havepassed through their power-on reset threshold voltages. The FPGA must not be configured until after VCCINT is applied.Once initialized and configured, use the XPower tools to estimate current drain on these supplies.Table 5: Power-On Current for Kintex-7 DevicesDeviceICCINTMINICCAUXMINICCOMINICCAUX TmAXC7K480TmANotes:1.2.Typical values are specified at nominal voltage, 25 C.Use the XPower Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate maximum power-on currents.DS182 (v1.4) February 13, 2012Advance Product Specificationwww.xilinx.com5
Kintex-7 FPGAs Data Sheet: DC and Switching CharacteristicsTable 6: Power Supply Ramp amp time from GND to 90% of VCCINT0.250msTVCCORamp time from GND to 90% of VCCO0.250msTVCCAUXRamp time from GND to 90% of VCCAUX0.250msTVCCAUX IORamp time from GND to 90% of TVCCAUX IO0.250msTVCCBRAMRamp time from GND to 90% of VCCBRAMmsTJ 0.250100 C(1)–50085 C(1)–800TVCCO2VCCAUXAllowed time per power cycle for VCCO – VCCAUX 2.625VTMGTAVCCRamp time from GND to 90% of MGTAVCC0.250msTMGTAVTTRamp time from GND to 90% of MGTAVTT0.250msTMGTVCCAUXRamp time from GND to 90% of MGTVCCAUX0.250msTJ msNotes:1.Based on 240,000 power cycles with nominal VCCO of 3.3V or 36,500 power cycles with a worst case VCCO of 3.465V.DS182 (v1.4) February 13, 2012Advance Product Specificationwww.xilinx.com6
Kintex-7 FPGAs Data Sheet: DC and Switching CharacteristicsSelectIO DC Input and Output LevelsValues for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommendedoperating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure thatall standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL andVOH voltage levels shown. Other standards are sample tested.Table 7: SelectIO DC Input and Output Levels (1)(2)I/O StandardVILVIHVOLVOHIOLIOHV, MinV, MaxV, MinV, MaxV, MaxV, MinmAmAHSTL I–0.300VREF – 0.100VREF 0.100VCCO 0.3000.400VCCO – 0.4008–8HSTL I 12–0.300VREF – 0.100VREF 0.100VCCO 0.30025% VCCO75% VCCO6.3–6.3HSTL I 18–0.300VREF – 0.100VREF 0.100VCCO 0.3000.400VCCO – 0.4008–8HSTL II–0.300VREF – 0.100VREF 0.100VCCO 0.3000.400VCCO – 0.40016–16HSTL II 18–0.300VREF – 0.100VREF 0.100VCCO 0.3000.400VCCO – 0.40016–16HSUL 12–0.300VREF – 0.120VREF 0.120VCCO 0.300VREF – 0.12VREF 0.120LVCMOS12–0.30035% VCCO65% VCCOVCCO 0.3000.400VCCO – 0.400Note 3Note 3LVCMOS15,LVDCI 15–0.30030% VCCO70% VCCOVCCO 0.30025% VCCO75% VCCONote 4Note 4LVCMOS18,LVDCI 18–0.30035% VCCO65% VCCOVCCO 0.3000.450VCCO – 0.450Note 5Note 5LVCMOS25–0.3000.7001.700VCCO 0.3000.400VCCO – 0.400Note 6Note 6LVCMOS33–0.3000.8002.0003.4500.400VCCO – 0.400Note 6Note 6LVTTL–0.3000.8002.0003.4500.4002.400Note 7Note 7MOBILE DDR–0.30020% VCCO80% VCCOVCCO 0.30010% VCCO90% VCCO0.1–0.1PCI33 3–0.50030% VCCO50% VCCOVCCO 0.50010% VCCO90% VCCO1.5–0.5SSTL12–0.300VREF – 0.100VREF 0.100VCCO 0.300 VREF – 0.150VREF 0.150SSTL135–0.300VREF – 0.900VREF 0.900VCCO 0.300 VREF – 0.150VREF 0.150SSTL135 R–0.300VREF – 0.900VREF 0.900VCCO 0.300 VREF – 0.150VREF 0.150SSTL15–0.300VREF – 0.100VREF 0.100VCCO 0.300VTT – 0.175VTT 0.17517.8–17.8SSTL15 R–0.300VREF – 0.100VREF 0.100VCCO 0.300VTT – 0.175VTT 0.175SSTL18 I–0.300VREF – 0.125VREF 0.125VCCO 0.300VTT – 0.470VTT 0.4708–8SSTL18 II–0.300VREF – 0.125VREF 0.125VCCO 0.300VTT – 0.600VTT 0.60013.4–13.4Notes:1.2.3.4.5.6.7.8.Tested according to relevant specifications.3.3V and 2.5V standards are only supported in 3.3V I/O banks.Supported drive strengths of 2, 4, 6, or 8 mA in HP I/O banks and 4, 8, or 12 mA in HR I/O banks.Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, or 16 mA in HR I/O banks.Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, 16, or 24 mA in HR I/O banks.Supported drive strengths of 4, 8, 12, or 16 mASupported drive strengths of 4, 8, 12, 16, or 24 mAFor detailed interface specific DC voltage levels, see UG471: 7 Series FPGAs SelectIO Resources User Guide.DS182 (v1.4) February 13, 2012Advance Product Specificationwww.xilinx.com7
Kintex-7 FPGAs Data Sheet: DC and Switching CharacteristicsTable 8: Differential SelectIO DC Input and Output LevelsI/O StandardVICM(1)V, Min V, TypVID(2)VOCM(3)VOD(4)V, MaxV, Min V, Typ V, MaxV, MinV, TypV, MaxV, Min V, Typ V, MaxMINI LVDS 25 00.4500.600PPDS 1000.2500.400RSDS 000.3500.600TMDS 332.7002.9653.2300.1500.6751.200 VCCO–0.405 VCCO–0.300 VCCO–0.190 0.4000.6000.800Notes:1.2.3.4.5.6.VICM is the input common mode voltage.VID is the input differential voltage (Q – Q).VOCM is the output common mode voltage.VOD is the output differential voltage (Q – Q).LVDS 25 is specified in Table 10.LVDS is specified in Table 11.Table 9: Complementary Differential SelectIO DC Input and Output LevelsVICM(1)I/O StandardVID(2)VOCM(3)VOD(4)VOX(5)V, V,V,V,V, V, V, V,V, V, V, V, V, V,V,Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ MaxVOL(6)VOH(7)V, MaxV, MinBLVDS 251.2500.1001.250N/A N/A N/AN/AN/ADIFF HSTL I0.7500.1000.7500.750N/AN/ADIFF HSTL I 180.9000.1000.9000.900N/AN/ADIFF HSTL II0.7500.1000.7500.750N/AN/ADIFF HSTL II 180.9000.1000.9000.900N/AN/ADIFF MOBILE DDR0.9000.1000.9000.900N/AN/ADIFF SSTL120.6000.1000.6000.600DIFF SSTL1350.6750.1000.6750.675(VCCO/2) – 0.160 (VCCO/2) 0.160DIFF SSTL150.7500.1000.7500.750(VCCO/2) – 0.175 (VCCO/2) 0.175DIFF SSTL18 I0.9000.1000.9000.900N/AN/ADIFF SSTL18 CM is the input common mode voltage.VID is the input differential voltage (Q – Q).VOCM is the output common mode voltage.VOD is the output differential voltage (Q – Q).VOX is the output crossing voltage (see JEDEC specifications for SSTL)VOL is the single-ended low-output voltage.VOH is the single-ended high-output voltage.DS182 (v1.4) February 13, 2012Advance Product Specificationwww.xilinx.com8
Kintex-7 FPGAs Data Sheet: DC and Switching CharacteristicsLVDS DC Specifications (LVDS 25)The LVDS 25 standard is available in the HR I/O banks. See UG471: 7 Series FPGAs SelectIO Resources User Guide formore information.Table 10: LVDS 25 DC SpecificationsSymbolDC CCOSupply VoltageVOHOutput High Voltage for Q and QRT 100 across Q and Q signals––1.675VVOLOutput Low Voltage for Q and QRT 100 across Q and Q signals0.825––VVODIFFDifferential Output Voltage (Q – Q),Q High (Q – Q), Q HighRT 100 across Q and Q signals247350600mVVOCMOutput Common-Mode VoltageRT 100 across Q and Q signals1.0001.2501.425VVIDIFFDifferential Input Voltage (Q – Q),Q High (Q – Q), Q High100350600mVVICMInput Common-Mode Voltage0.3001.2001.425VLVDS DC Specifications (LVDS)The LVDS standard is available in the HP I/O banks. See UG471: 7 Series FPGAs SelectIO Resources User Guide for moreinformation.Table 11: LVDS DC SpecificationsSymbolDC CCOSupply VoltageVOHOutput High Voltage for Q and QRT 100 across Q and Q signals––1.675VVOLOutput Low Voltage for Q and QRT 100 across Q and Q signals0.825––VVODIFFDifferential Output Voltage (Q – Q),Q High (Q – Q), Q HighRT 100 across Q and Q signals247350600mVVOCMOutput Common-Mode VoltageRT 100 across Q and Q signals1.0001.2501.425VVIDIFFDifferential Input Voltage (Q – Q),Q High (Q – Q), Q HighCommon-mode input voltage 1.25V100350600mVVICMInput Common-Mode VoltageDifferential input voltage 350 mV0.3001.2001.425VeFUSE Programming ConditionsTable 12 lists the programming conditions specifically for eFUSE. For more information, see UG470: 7 Series FPGAConfiguration User Guide.Table 12: eFUSE Programming AUX supply current––115mAtjTemperature range15–125 CNotes:1.The FPGA must not be configured during eFUSE programming.DS182 (v1.4) February 13, 2012Advance Product Specificationwww.xilinx.com9
Kintex-7 FPGAs Data Sheet: DC and Switching CharacteristicsGTX Transceiver SpecificationsGTX Transceiver DC CharacteristicsTable 13: Absolute Maximum Ratings for GTX Analog supply voltage for the GTX transmitter and receiver circuits relative toGND–0.51.1VMGTAVTTAnalog supply voltage for the GTX transmitter and receiver termination circuitsrelative to GND–0.51.32VMGTAVTTRCALAnalog supply voltage for the resistor calibration circuit of the GTX transceivercolumn–0.51.32VMGTVCCAUXAuxiliary analog Quad PLL (QPLL) voltage supply for the GTX transceivers–0.51.935VVINReceiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage–0.51.26VVMGTREFCLKReference clock absolute input voltage–0.51.32VNotes:1.Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.DS182 (v1.4) February 13, 2012Advance Product Specificationwww.xilinx.com10
Kintex-7 FPGAs Data Sheet: DC and Switching CharacteristicsTable 14: Recommended Operating Conditions for GTX Transceivers (1)(2)SymbolDescriptionMinTypMaxUnitsMGTAVCCAnalog supply voltage for the GTX transmitter and receiver circuits relative toGND0.971.01.03MGTAVTTAnalog supply voltage for the GTX transmitter and receiver termination circuitsrelative to GND1.171.21.23VMGTAVTTRCALAnalog supply voltage for the resistor calibration circuit of the GTX transceivercolumn1.171.21.23VMGTVCCAUXAuxiliary analog Quad PLL (QPLL) voltage supply for the transceivers1.751.801.85VVNotes:1.2.Each voltage listed requires the filter circuit described in UG476: 7 Series FPGAs Transceiver User Guide.Voltages are specified for the temperature range of Tj 0 C to 85 C.GTX Transceiver DC Input and Output LevelsTable 15 summarizes the DC output specifications of the GTX transceivers in Kintex-7 FPGAs. Consult UG476: 7 SeriesFPGAs Transceiver User Guide for further details.Table 15: GTX Transceiver DC SpecificationsSymbolDVPPINVINVCMINDC tial peak-to-peak inputvoltageExternal AC coupledAbsolute input voltageDC coupledMGTAVTT 1.2V–200–MGTAVTTmVCommon mode input voltageDC coupledMGTAVTT 1.2V–2/3 MGTAVTT–mV––1000mVDVPPOUTDifferential peak-to-peak output Transmitter output swing is set tovoltage (1)maximum settingVCMOUTDCDC common mode outputvoltage.Equation basedIDCINDC input current for receiverinput pinsDC coupledMGTAVTT 1.2V––14mAIDCOUTDC output current fortransmitter pinsDC coupledMGTAVTT 1.2V––14mARINDifferential input resistance100 ROUTDifferential output resistance100 TOSKEWTransmitter output pair (TXP and TXN) intra-pair skewCEXTRecommended external AC couplingcapacitor(2)MGTAVTT – DVPPOUT/4mV–212ps–100–nFNotes:1.2.The output swing and preemphasis levels are programmable using the attributes discussed in UG476: 7 Series FPGAs Transceiver UserGuide and can result in values lower than reported in this table.Other values can be used as appropriate to conform to specific protocols and standards.DS182 (v1.4) February 13, 2012Advance Product Specificationwww.xilinx.com11
Kintex-7 FPGAs Data Sheet: DC and Switching CharacteristicsX-Ref Target - Figure 1 VPSingle-EndedVoltageN0ds182 02 051111Figure 1: Single-Ended Peak-to-Peak VoltageX-Ref Target - Figure 2 VDifferentialVoltage0–VP–Nds182 03 051111Figure 2: Differential Peak-to-Peak VoltageTable 16 summarizes the DC specifications of the clock input of the GTX transceiver. Consult UG476: 7 Series FPGAsTransceiver User Guide for further details.Table 16: GTX Transceiver Clock DC Input Level SpecificationSymbolDC ParameterVIDIFFDifferential peak-to-peak input voltageRINDifferential input resistanceCEXTRequired external AC coupling capacitorDS182 (v1.4) February 13, 2012Advance Product SpecificationMinTyp250MaxUnits2000mV 100–100–nFwww.xilinx.com12
Kintex-7 FPGAs Data Sheet: DC and Switching CharacteristicsGTX Transceiver Switching CharacteristicsConsult UG476: 7 Series FPGAs Transceiver User Guide for further information.Table 17: GTX Transceiver PerformanceSpeed L-2L(1)-1UnitsPackage Maximum GTX transceiver data rate12.56.610.31256.66.66.66.66.6Gb/sMinimum GTX transceiver data LL line rate .5–0.825Gb/s16N/AGb/s1FGTXQRANGE1QPLL line rate range /s0.6125–0.781250.6125–0.64453125N/AN/AGb/sGTX transceiver CPLL GHzFGCPLLRANGE1 GTX transceiver QPLL frequencyrange RANGE2 GTX transceiver QPLL frequencyrange 29.8–12.59.8–10.3125N/AN/AGHzFGTXQRANGE2QPLL line rate range2(3)16FGCPLLRANGENotes:1.2.3.The -2L speed grade requires a 4-byte internal data width for operation above 5.0 Gb/s.Data rates between 8.0 Gb/s and 9.8 Gb/s are not available.For QPLL line rate range 2, the maximum line rate with the divider N set to 66 is 10.3125Gb/s.Table 18: GTX Transceiver Dynamic Reconfiguration Port (DRP) Switching CharacteristicsSpeed GradeSymbolFGTXDRPCLKDescription1.0VGTXDRPCLK maximum frequencyDS182 (v1.4) February 13, 2012Advance Product www.xilinx.com13
Kintex-7 FPGAs Data Sheet: DC and Switching CharacteristicsTable 19: GTX Transceiver Reference Clock Switching CharacteristicsSymbolDescriptionAll Speed GradesConditionsUnitsMinTypMax-3 speed grade60–700MHzAll other speed grades60–670MHzFGCLKReference clock frequency rangeTRCLKReference clock rise time20% – 80%–200–psTFCLKReference clock fall time80% – 20%–200–psTDCREFReference clock duty cycleTransceiver PLL only405060%TLOCKClock recovery frequency acquisitiontimeInitial PLL lock––ms–UITDLOCKAfter the PLL is locked to thereference clock, this is the time ittakes to lock the data to the datapresent at the input.–Clock recovery phase acquisition andadaptation timeX-Ref Target - Figure 3TRCLK80%20%TFCLKds182 04 051111Figure 3: Reference Clock Timing ParametersTable 20: GTX Transceiver User Clock Switching Characteristics(1)(2)Speed Grade 1-2LUnitsFTXOUTTXOUTCLK maximum frequency412.5412.5312.5312.5MHzFRXOUTRXOUTCLKT maximum frequency412.5412.5312.5312.5MHzFTXINTXUSRCLK maximum frequency16-bit data path412.5412.5312.5312.5MHz32-bit data path391323206.25206.25MHzFRXINRXUSRCLK maximum frequency16-bit data path412.5412.5312.5312.5MHz32-bit data path391323206.25206.25MHz16-bit data path412.5412.5312.5312.5MHz32-bit data path391323206.25206.25MHz64-bit data path196162103.125103.125MHz16-bit data path412.5412.5312.5312.5MHz32-bit data path391323206.25206.25MHz64-bit data path196162103.125103.125MHzFTXIN2FRXIN2TXUSRCLK2 maximum frequencyRXUSRCLK2 maximum frequencyNotes:1.2.3.4.Clocking must be implemented as described in UG476: 7 Series FPGAs Transceiver User Guide.These frequencies are not supported for all possible transceiver configurations.For speed grades -3, -2, -2L (1.0V), a 16-bit data path can only be used for speeds less than 6.6 Gb/s.For speed grades -1 and -2L (0.9V), a 16-bit data path can only be used for speeds less than 5.0 Gb/s.DS182 (v1.4) February 13, 2012Advance Product Specificationwww.xilinx.com14
Kintex-7 FPGAs Data Sheet: DC and Switching CharacteristicsTable 21: GTX Transceiver Transmitter Switching CharacteristicsSymbolDescriptionFGTXTXSerial data rate rangeTRTXTX Rise timeTFTXTX Fall ��80%–40–ps80%–20%ps–40–TLLSKEWTX lane-to-laneskew(1)––500psVTXOOBVDPPElectrical idle amplitude––15mVTTXOOBTRANSITIONElectrical idle transition (2)(4)DJ12.5DeterministicTJ11.18Total Jitter(2)(4)DJ11.18Deterministic DJ10.3125DeterministicTJ9.953Total Jitter(2)(4)DJ9.953Deterministic 8DeterministicTJ8.0Total Jitter(2)(4)DJ8.0Deterministic 5DeterministicTJ5.0Total Jitter(3)(4)DJ5.0Deterministic .25DeterministicTJ3.75Total Jitter(3)(4)DJ3.75Deterministic 2DeterministicTJ3.2LTotal Jitter(3)(4)DJ3.2LDeterministic 5DeterministicTJ1.25Total Jitter(3)(4)DJ1.25Deterministic icJitter(3)(4)12.5 Gb/s11.18 Gb/s10.3125 Gb/s9.953 Gb/s9.8 Gb/s8.0 Gb/s6.5 Gb/s5.0 Gb/s4.25 Gb/s3.75 Gb/s3.20 Gb/s3.20 Gb/s(5)2.5 Gb/s(6)1.25 Gb/s(7)500 Mb/sNotes:1.2.3.4.5.6.7.Using same REFCLK input with TX phase alignment enabled for up to 12 consecutive transmitters (three fully populated GTX Quads).Using QPLL FBDIV 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.Using CPLL FBDIV 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.All jitter values are based on a bit-error ratio of 1e-12.PLL frequency at 1.6 GHz and TXOUTDIV 1.PLL frequency at 2.5 GHz and TXOUTDIV 2.PLL frequency at 2.5 GHz and TXOUTDIV 4.DS182 (v1.4) February 13, 2012Advance Product Specificationwww.xilinx.com15
Kintex-7 FPGAs Data Sheet: DC and Switching CharacteristicsTable 22: GTX Transceiver Receiver Switching �FGTXMAXGb/sFGTXRXSerial data rateTRXELECIDLETime for RXELECIDLE to respond to loss or restoration of data–75–nsRXOOBVDPPOOB detect threshold peak-to-peak60–150mVRXSSTReceiver spread-spectrumtracking(1)Modulated @ 33 KHz–5000–0ppmRXRLRun length (CID)Internal AC capacitor bypassed––512UIData/REFCLK PPM offsettoleranceBit rates 6.6 Gb/s–1250–1250ppmBit rates 6.6 Gb/s and 8.0 Gb/s–700–700ppmBit rates 8.0 Gb/s–200–200ppmRXPPMTOLSJ JitterRX oversampler not enabledMinTolerance(2)JT SJ12.5JT SJ11.18JT SJ10.32JT SJ9.95JT SJ9.8JT SJ8.0JT SJ6.5JT SJ5.0JT SJ4.25JT SJ3.75JT SJ3.2JT SJ3.2LJT SJ2.5JT SJ1.25JT SJ500Sinusoidal Jitter(3)12.5 Gb/s0.3––UISinusoidalJitter(3)11.18 Gb/s0.3––UISinusoidalJitter(3)10.32 Gb/s0.3––UISinusoidalJitter(3)9.95 Gb/s0.3––UISinusoidalJitter(3)9.8 Gb/s0.3––UISinusoidalJitter(3)8.0 Gb/s0.44––UISinusoidalJitter(3)6.5 Gb/s0.44––UISinusoidalJitter(3)5.0 Gb/s0.44––UISinusoidalJitter(3)4.25 Gb/s0.44––UISinusoidalJitter(3)3.75 Gb/s0.44––UISinusoidalJitter(3)3.2 alJitter(3)1.25SinusoidalJitter(3)SJ Jitter Tolerance with 5)0.5––UI0.5––UI500 Mb/s0.4––UI3.2 Gb/s0.70––UI6.6 Gb/s0.70––UI3.2 Gb/s0.1––UI6.6 Gb/s0.1––UIGb/s(6)Eye(2)JT TJSE3.2Total Jitter with Stressed Eye(7)JT SJSE3.2Sinusoidal Jitter with StressedEye(7)Notes:1.2.3.4.5.6.7.Using RXOUTDIV 1, 2, and 4.All jitter values are based on a bit error ratio of 1e–12.The frequency of the injected sinusoidal jitter is 80 MHz.PLL frequency at 1.6 GHz and RXOUTDIV 1.PLL frequency at 2.5 GHz and RXOUTDIV 2.PLL frequency at 2.5 GHz and RXOUTDIV 4.Composite jitter with RX equalizer enabled. DFE disabled.DS182 (v1.4) February 13, 2012Advance Product Specificationwww.xilinx.com16
Kintex-7 FPGAs Data Sheet: DC and Switching CharacteristicsGTX Transceiver Protocol Jitter ParametersTable 23: Gigabit Ethernet Protocol ParametersDescriptionLine Rate (Mb/s)MinMaxUnits1250–0.24UI12500.71–UILine Rate (Mb/s)MinMaxUnits3125–0.35UI31250.65–UIGigabit Ethernet Transmitter Jitter GenerationTotal transmitter jitter (T TJ)Gigabit Ethernet Receiver High Frequency Jitter ToleranceTotal receiver jitter toleranceTable 24: XAUI Protocol ParametersDescriptionXAUI Transmitter Jitter GenerationTotal transmitter jitter (T TJ)XAUI Receiver High Frequency Jitter ToleranceTotal receiver jitter toleranceTable 25: PCI Express Protocol ParametersStandardDescriptionLine Rate (Mb/s)MinMaxUnitsPCI Express Transmitter Jitter GenerationPCI Express Gen 1Total trans
Kintex-7 FPGA Electrical Characteristics Kintex -7 FPGAs are available in -3, -2, -1, and -2L speed grades, with -3 having the highest performance. The -2L devices can operate at either of two VCCINT voltages, 0.9V and 1.0V and are screened for lower maximum static power. When operated at V CCINT 1.0V, the speed specification ofFile Size: 1MBPage Count: 63
Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.19) March 26, 2021 www.xilinx.com Product Specification 4 Table 3: DC Characteristics Over Recommended Operating Conditions Symbol Description Min Typ(1) Max Units VDRINT Data retention VCCINT voltage (below which configuration data might be lost) 0.75 – – V VDRI Data retention VCCAUX voltage (below which .
For I/O operation, refer to the 7 Series FPGAs SelectIO Resources User Guide (UG471). 4. The maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see Table 4 and Table 5 . . Each voltage listed requires the filter circuit described in the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476). 11. For .
6. For more information, refer to the VCCAUX_IO section of 7 Series FPGAs SelectIO Resources User Guide (UG471). 7. The lower absolute voltage specification always applies. 8. See Table 10 for TMDS_33 specifications. 9. A total of 200 mA per bank should not be exceeded. 10. VCCBATT is required only when using bitstream encryption.
Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS922 (v1.3) May 8, 2017 www.xilinx.com Preliminary Product Specification 2 VBATT Key memory battery backup supply. –0.500 2.000 V IDC Available output current at the pad. –20 20 mA IRMS Available RMS ou
Kintex-7 devices are half the cost of the Virtex-6 HXT device and offer essentially equivalent performance. With similar fabric architecture, the Kintex-7 family is an attractive option for Virtex
3. See DS180, 7 Series FPGAs Overview, for package details. 4. GTX transceivers in FB packages support the following maximum data rates: 10.3Gb/s in FBG484; 6.6Gb/s in FBG676 and FBG900. See DS182, Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics, for details. Optimized for Best Price-Performance (1.0V, 0.95V, 0.9V)
7 Series FPGAs PCB Design Guide www.xilinx.com UG483 (v1.14) May 21, 2019 The information disclosed to you hereunder (the "Materials") is provided solely for the selecti on and use of Xilinx products. T o the maximum extent permitted by applicable law: (1) Materials are made availa ble "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL
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