Multiphase PWM Regulator For IMVP-6.5 Mobile CPUs And
ISL62883CFeaturesThe ISL62883C is a multiphase PWM buck regulator formiroprocessor or graphics processor core power supply.The multiphase buck converter uses interleaved phase toreduce the total output voltage ripple with each phasecarrying a portion of the total load current, providingbetter system performance, superior thermalmanagement, lower component cost, reduced powerdissipation, and smaller implementation area. TheISL62883C uses two integrated gate drivers and anexternal gate driver to provide a complete solution. ThePWM modulator is based on Intersil's Robust RippleRegulator (R3) technology . Compared with traditionalmodulators, the R3 modulator commands variableswitching frequency during load transients, achievingfaster transient response. With the same modulator, theswitching frequency is reduced at light load, increasingthe regulator efficiency. Programmable 1, 2- or 3-Phase CPU or GPU Mode ofOperation Precision Multiphase Core Voltage Regulation- 0.5% System Accuracy Over-Temperature- Enhanced Load Line Accuracy Microprocessor Voltage Identification Input- 7-Bit VID Input, 0V to 1.500V in 12.5mV Steps- Supports VID Changes On-The-Fly Supports Multiple Current Sensing Methods- Lossless Inductor DCR Current Sensing- Precision Resistor Current Sensing The ISL62883C can be configured as CPU or graphicsVcore controller and is fully compliant with IMVP-6.5 specifications. It responds to PSI# and DPRSLPVR signalsby adding or dropping PWM3 and Phase 2 respectively,adjusting overcurrent protection threshold accordingly,and entering/exiting diode emulation mode. It reportsthe regulator output current through the IMON pin. Itsenses the current by using either discrete resistor orinductor DCR whose variation over temperature can bethermally compensated by a single NTC thermistor. Ituses differential remote voltage sensing to accuratelyregulate the processor die voltage. The adaptive bodydiode conduction time reduction function minimizesthe body diode conduction loss in diode emulationmode. User-selectable overshoot reduction functionoffers an option to aggressively reduce the outputcapacitors as well as the option to disable it for usersconcerned about increased system thermal stress. In2-Phase configuration, the ISL62883C offers the FB2function to optimize 1-Phase performance.Supports PSI# and DPRSLPVR modesSuperior Noise Immunity and Transient ResponseCurrent Monitor and Thermal MonitorDifferential Remote Voltage SensingHigh Efficiency Across Entire Load RangeTwo Integrated Gate DriversExcellent Dynamic Current BalanceFB2 Function Optimizes 1-Phase Mode Performance Adaptive Body Diode Conduction Time Reduction User-selectable Overshoot Reduction Function Small Footprint 40 Ld 5x5 TQFN Packages Pb-Free (RoHS Compliant)Applications*(see page 42) Notebook Core Voltage Regulator Notebook GPU Voltage RegulatorRelated Literature*(see page 42) See AN1460 for ISL62883/ISL62883C EvaluationBoard Application Note “ISL62883EVAL2Z UserGuide”Load Line Regulation1.101.081.06VIN 8VVOUT (V)1.04VIN 12V1.02VIN 19V1.000.980.960.940.92March 18, 2010FN7557.11051015202530 35 40IOUT (A)4550556065CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.1-888-INTERSIL or 1-888-468-3774 Intersil (and design) is a registered trademark of Intersil Americas Inc.Copyright Intersil Americas Inc. 2009, 2010. All Rights ReservedAll other trademarks mentioned are the property of their respective owners.ISL62883CMultiphase PWM Regulator for IMVP-6.5 MobileCPUs and GPUs
ISL62883COrdering InformationPART NUMBER(Note 3)TEMP. RANGE( C)PART MARKINGPACKAGE(Pb-Free)PKG.DWG. #ISL62883CIRTZ (Note 2)62883C IRTZ-40 to 10040 Ld 5x5 TQFNL40.5x5ISL62883CIRTZ-T (Notes 1, 2)62883C IRTZ-40 to 10040 Ld 5x5 TQFNL40.5x5ISL62883CHRTZ (Note 2)62883C HRTZ-10 to 10040 Ld 5x5 TQFNL40.5x5ISL62883CHRTZ-T (Notes 1, 2)62883C HRTZ-10 to 10040 Ld 5x5 TQFNL40.5x5NOTES:1. Please refer to TB347 for details on reel specifications.2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attachmaterials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with bothSnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures thatmeet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.3. For Moisture Sensitivity Level (MSL), please see device information page for ISL62883C. For more information on MSL pleasesee techbrief TB363.Pin R ONCLK EN#ISL62883C(40 LD TQFN)TOP VIEW40 39 38 37 36 35 34 33 32 3130 BOOT2PGOOD 1PSI# 229 UGATE2RBIAS 328 PHASE2VR TT# 427 VSSP2NTC 526 LGATE2GND PAD(BOTTOM)VW 625 VCCPCOMP 724 PWM3FB 823 LGATE122 VSSP1ISEN3/FB2 921 PHASE1ISEN2 102BOOT1UGATE1VINIMONVDDISUM-ISUM RTNVSENISEN111 12 13 14 15 16 17 18 19 20FN7557.1March 18, 2010
ISL62883CFunctional Pin SI#Low load current indicator input. When asserted low, indicates a reduced load-current condition.3RBIASA resistor to GND sets internal current reference. Use 147kΩ or 47kΩ. The choice of Rbias value,together with the ISEN2 pin configuration and the external resistance from the COMP pin toGND, programs the controller to enable/disable the overshoot reduction function and to selectthe CPU/GPU mode.4VR TT#Thermal overload output indicator.5NTCThermistor input to VR TT# circuit.6VWA resistor from this pin to COMP programs the switching frequency (8kΩ gives approximately300kHz).7COMPThis pin is the output of the error amplifier. Also, a resistor across this pin and GND adjusts theovercurrent threshold.8FB9INSE3/FB210ISEN2Individual current sensing for Phase 2. When ISEN2 is pulled to 5V VDD, the controller willdisable Phase 2.11ISEN1Individual current sensing for phase 1.12VSENRemote core voltage sense input. Connect to microprocessor die.13RTN14, 15ISUM- andISUM 16VDD5V bias power.17VINBattery supply voltage, used for feed-forward.18IMON19BOOT1Connect an MLCC capacitor across the BOOT1 and the PHASE1 pins. The boot capacitor ischarged through an internal boot diode connected from the VCCP pin to the BOOT1 pin, eachtime the PHASE1 pin drops below VCCP minus the voltage dropped across the internal bootdiode.20UGATE1Output of the Phase-1 high-side MOSFET gate driver. Connect the UGATE1 pin to the gate of thePhase-1 high-side MOSFET.21PHASE1Current return path for the Phase-1 high-side MOSFET gate driver. Connect the PHASE1 pin tothe node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the outputinductor of Phase-1.22VSSP1Current return path for the Phase-1 low-side MOSFET gate driver. Connect the VSSP1 pin to thesource of the Phase-1 low-side MOSFET through a low impedance path, preferably in parallelwith the traces connecting the LGATE1a and the LGATE1b pins to the gates of the Phase-1 lowside MOSFETs.23LGATE1Output of the Phase-1 low-side MOSFET gate driver. Connect the LGATE1 pin to the gate of thePhase-1 low-side MOSFET.24PWM3PWM output for Phase 3. When PWM3 is pulled to 5V VDD, the controller will disable Phase-3and allow other phases to operate.Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin.Power-Good open-drain output indicating when the regulator is able to supply regulatedvoltage. Pull up externally with a 680Ω resistor to VCCP or 1.9kΩ to 3.3V.This pin is the inverting input of the error amplifier.When the ISL62883C is configured in 3-phase mode, this pin is ISEN3. ISEN3 is the individualcurrent sensing for phase 3. When the ISL62883C is configured in 2-phase mode, this pin isFB2. There is a switch between the FB2 pin and the FB pin. The switch is on in 2-phase modeand is off in 1-phase mode. The components connecting to FB2 are used to adjust thecompensation in 1-phase mode to achieve optimum performance.Remote voltage sensing return. Connect to ground at microprocessor die.Droop current sense input.An analog output. IMON outputs a current proportional to the regulator output current.3FN7557.1March 18, 2010
ISL62883CFunctional Pin Descriptions (Continued)ISL62883CSYMBOLDESCRIPTION25VCCPInput voltage bias for the internal gate drivers. Connect 5V to the VCCP pin. Decouple with atleast 1µF of an MLCC capacitor to VSSP1 and VSSP2 pins respectively.26LGATE2Output of the Phase-2 low-side MOSFET gate driver. Connect the LGATE2 pin to the gate of thePhase-2 low-side MOSFET.27VSSP2Current return path for the Phase-2 converter low-side MOSFET gate driver. Connect the VSSP2pin to the source of the Phase-2 low-side MOSFET through a low impedance path, preferably inparallel with the trace connecting the LGATE2 pin to the gate of the Phase-2 low-side MOSFET.28PHASE2Current return path for the Phase-2 high-side MOSFET gate driver. Connect the PHASE2 pin tothe node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the outputinductor of Phase-2.29UGATE2Output of the Phase-2 high-side MOSFET gate driver. Connect the UGATE2 pin to the gate of thePhase-2 high-side MOSFET.30BOOT2Connect an MLCC capacitor across the BOOT2 and the PHASE2 pins. The boot capacitor ischarged through an internal boot diode connected from the VCCP pin to the BOOT2 pin, eachtime the PHASE2 pin drops below VCCP minus the voltage dropped across the internal bootdiode.31 thru 37VID0 thruVID638VR ON39DPRSLPVRDeeper sleep enable signal. A high level logic signal on this pin indicates that the microprocessoris in deeper sleep mode.40CLK EN#Open drain output to enable system PLL clock. It goes low 13 switching cycles after Vcore iswithin 10% of Vboot.padBOTTOMThe bottom pad of ISL62883C is electrically connected to the GND pin inside the IC.It shouldalso be used as the thermal pad for heat removal.VID input with VID0 LSB and VID6 MSB.Voltage regulator enable input. A high level logic signal on this pin enables the regulator.4FN7557.1March 18, 2010
ISL62883CBlock DiagramVDDVIN VSEN ISEN1 ISEN3 ISEN2 PGOOD CLK EN#6µA 54µA 1.20VVR ONPSI#IBAL2IBAL3IBAL1MODECONTROLPGOOD &CLK TECTIONBOOT2FLTIBAL2 VIN VDACVID1WOC RIVERIBAL3 VIN VDACVID5VID6MODULATOR RTNΣ FBVSSP2PWM3BOOT1COMPE/APWM CONTROL LOGICVID3PWM CONTROL LOGICVID0VID2VR TT#IBAL1 VIN VDACCOMPVWMODULATORIDROOPIMONIMON WOC CURRENTCOMPARATORSNUMBER OFOCPHASES2.5XISUM HASE1SHOOT-THROUGHPROTECTIONVCCPDRIVERLGATE1VSSP1 Σ ADJ. OCPTHRESHOLDCOMPGNDFN7557.1March 18, 2010
ISL62883CTable of ContentsOrdering Information . 2Pin Configuration . 2Functional Pin Descriptions . 3Block Diagram . 5Table of Contents . 6Absolute Maximum Ratings . 7Thermal Information . 7Recommended Operating Conditions . 7Electrical Specifications . 7Gate Driver Timing Diagram . 10Simplified Application Circuits . 10Theory of Operation . 13Diode Emulation and Period Stretching . 14Start-up Timing . 15Voltage Regulation and Load Line Implementation . 15Differential Sensing . 17Phase Current Balancing . 18Modes of Operation . 20Dynamic Operation . 20Protections . 21FB2 Function . 22Adaptive Body Diode Conduction Time Reduction . 22Overshoot Reduction Function . 22Key Component Selection . 23RBIAS .Inductor DCR Current-Sensing Network .Resistor Current-Sensing Network .Overcurrent Protection.Current Monitor .Compensator .Optional Slew Rate Compensation Circuit For 1-Tick VID Transition .Voltage Regulator Thermal Throttling .Current Balancing .232325252627293030Layout Guidelines . 301-PHASE GPU Application Reference Design Bill of Materials . 342-PHASE CPU Application Reference Design Bill of Materials . 35Typical Performance . 37Products . 42Package Outline Drawing . 436FN7557.1March 18, 2010
ISL62883CAbsolute Maximum RatingsThermal InformationSupply Voltage, VDD. . . . . . . . . . . . . . . . . . . .-0.3V to 7VBattery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . 28VBoot Voltage (BOOT) . . . . . . . . . . . . . . . . . . -0.3V to 33VBoot to Phase Voltage (BOOT-PHASE) . . . . -0.3V to 7V(DC). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 9V( 10ns)Phase Voltage (PHASE) . . . . . -7V ( 20ns Pulse Width, 10µJ)UGATE Voltage (UGATE) . . . . . . . PHASE-0.3V (DC) to BOOT. . . . . . . . . PHASE-5V ( 20ns Pulse Width, 10µJ) to BOOTLGATE Voltage. . . . . . . . . . . -2.5V ( 20ns Pulse Width, 5µJ) to VDD 0.3VAll Other Pins. . . . . . . . . . . . . . . . . . -0.3V to (VDD 0.3V)Open Drain Outputs, PGOOD, VR TT#,CLK EN# . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7VThermal Resistance (Typical)θJA ( C/W) θJC ( C/W)40 Ld TQFN Package (Notes 4, 5). .312Maximum Junction Temperature . . . . . . . . . . . . . . . 150 CMaximum Storage Temperature Range . . . -65 C to 150 CMaximum Junction Temperature (Plastic Package). . . 150 CStorage Temperature Range . . . . . . . . . . . -65 C to 150 CPb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link aspRecommended Operating ConditionsSupply Voltage, VDD .Battery Voltage, VIN .Ambient TemperatureISL62883CHRTZ. . .ISL62883CIRTZ . . .Junction TemperatureISL62883CHRTZ. . .ISL62883CIRTZ . . . . . . . . . . . . . . . . . . . . . . 5V 5%. . . . . . . . . . . . . . . . . . 4.5V to 25V. . . . . . . . . . . . . . . -10 C to 100 C. . . . . . . . . . . . . . . -40 C to 100 C. . . . . . . . . . . . . . . -10 C to 125 C. . . . . . . . . . . . . . . -40 C to 125 CCAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impactproduct reliability and result in failures not covered by warranty.NOTE:4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”features. See Tech Brief TB379.5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.Electrical SpecificationsPARAMETEROperating Conditions: VDD 5V, TA -40 C to 100 C, fSW 300kHz,unless otherwise noted. Boldface limits apply over the operating temperature range,-40 C to 100 C.SYMBOLTEST CONDITIONSMIN(Note 6)TYPMAX(Note 6)UNITS44.6mA1µAINPUT POWER SUPPLY 5V Supply CurrentIVDDVR ON 1VVR ON 0VBattery Supply CurrentIVINVR ON 0VVIN Input ResistanceRVINVR ON 1V1Power-On-Reset ThresholdPORrVDD risingPORfVDD falling4.00No load; closed loop, active moderangeVID 0.75V to 1.50V,-0.5µA9004.35kΩ4.54.15VVSYSTEM AND REFERENCESSystem AccuracyHRTZ%Error(VCC CORE)IRTZ%Error(VCC CORE)VID 0.5V to 0.7375V-8 8mV-15 15mVNo load; closed loop, active moderangeVID 0.75V to 1.50V-0.8 0.8%VID 0.5V to 0.7375V-10 10mV 09121.1001.1088VMaximum Output VoltageVCC CORE(max) VID [0000000]Minimum Output VoltageVCC CORE(min) VID [1100000]RBIAS VoltageRBIAS 147kΩ7%VID 0.3V to 0.4875VVID 0.3V to 0.4875VVBOOT 0.5-181.500V0.3001.451.47V1.49VFN7557.1March 18, 2010
ISL62883CElectrical SpecificationsPARAMETEROperating Conditions: VDD 5V, TA -40 C to 100 C, fSW 300kHz,unless otherwise noted. Boldface limits apply over the operating temperature range,-40 C to 100 C. (Continued)SYMBOLTEST CONDITIONSMIN(Note 6)TYPMAX(Note 6)UNITS285300315kHz200500kHz-0.15 0.15mVCHANNEL FREQUENCYNominal Channel FrequencyfSW(nom)Rfset 7kΩ, 3-channel operation,VCOMP 1VAdjustment RangeAMPLIFIERSIFB 0ACurrent-Sense Amplifier InputOffsetError Amp DC Gain (Note 7)Av0Error Amp Gain-BandwidthProduct (Note 7)GBWCL 20pF90dB18MHzISENImbalance VoltageMaximum of ISENs - Minimum ofISENs1Input Bias CurrentmV20nAPOWER-GOOD AND PROTECTION MONITORSVOLIPGOOD 4mAPGOOD Leakage CurrentIOHPGOOD 3.3VPGOOD DelaytpgdCLK ENABLE# LOW to PGOOD HIGHPGOOD Low Voltage0.260.41µA7.68.9ms1.5Ω-16.3VGATE DRIVERUGATE Pull-Up Resistance(Note 7)RUGPU200mA Source Current1.0UGATE Source Current (Note 7)IUGSRCUGATE - PHASE 2.5V2.0AUGATE Sink Resistance (Note 7)RUGPD250mA Sink Current1.0UGATE Sink Current (Note 7)IUGSNKUGATE - PHASE 2.5V2.01.5ΩLGATE Pull-Up Resistance(Note 7)RLGPU250mA Source Current1.0LGATE Source Current (Note 7)ILGSRCLGATE - VSSP 2.5V2.0LGATE Sink Resistance (Note 7)RLGPD250mA Sink Current0.5LGATE Sink Current (Note 7)ILGSNKLGATE - VSSP 2.5V4.0AUGATE to LGATE DeadtimetUGFLGRUGATE falling to LGATE rising, no load23nsLGATE to UGATE DeadtimetLGFUGRLGATE falling to UGATE rising, no load28nsA1.5Ω0.9ΩABOOTSTRAP DIODEForward VoltageVFPVCC 5V, IF 2mAReverse LeakageIRVR 25V0.58V0.2µAPROTECTIONOvervoltage ThresholdOVHSevere Overvoltage ThresholdOVHSOC Threshold Offset atRcomp Open CircuitCurrent Imbalance ThresholdVSEN rising above setpoint for 1msVSEN rising for 2µs1501952401.5251.551.575V3-phase configuration, ISUM- pincurrent28.430.332.2µA2-phase configuration, ISUM- pincurrent18.320.222.1µA1-phase configuration, ISUM- pincurrent8.210.112.0µAOne ISEN above another ISEN for 1.2msUndervoltage ThresholdUVf8mVVSEN falling below setpoint for 1.2ms9-355-295mV-235mVFN7557.1March 18, 2010
ISL62883CElectrical SpecificationsPARAMETEROperating Conditions: VDD 5V, TA -40 C to 100 C, fSW 300kHz,unless otherwise noted. Boldface limits apply over the operating temperature range,-40 C to 100 C. (Continued)SYMBOLTEST CONDITIONSMIN(Note 6)TYPMAX(Note 6)UNITS0.3VLOGIC THRESHOLDSVR ON Input LowVILVR ON Input VID6, PSI#, andDPRSLPVR Input LowVILVID0-VID6, PSI#, and DPRSLPVRInput HighVIH0.30.7VVPWMPWM3 Output LowV0LSinking 5mAPWM3 Output HighV0HSourcing 5mAPWM Tri-State Leakage1.03.5PWM 2.5VVV2µATHERMAL MONITORNTC Source CurrentNTC 1.3VOver-Temperature ThresholdV (NTC) fallingRTTI 20mACLK EN# Low Output VoltageVOLI 4mACLK EN# Leakage CurrentIOHCLK EN# 3.3VVR TT# Low Output LK EN# OUTPUT LEVELS-1CURRENT MONITORIMON Output CurrentIIMONISUM- pin current 20µA114120126µAISUM- pin current 10µA546066µA3034.5µA1.11.15VISUM- pin current 5µAIMON Clamp Voltage25.5VIMONCLAMPCurrent Sinking Capability275µAINPUTSVR ON Leakage CurrentIVR ONVR ON 0V-1VR ON 1VVIDx Leakage CurrentIVIDxVIDx 0V0-1VIDx 1VPSI# Leakage CurrentIPSI#PSI# 0V-1IDPRSLPVRDPRSLPVR 0V-1µA1µA1µA1µA6.5mV/µsµA00.45DPRSLPVR 1VµA100.45PSI# 1VDPRSLPVR Leakage Current0µA00.45µASLEW RATESlew Rate (For VID Change)SR5NOTES:6. Parameters with MIN and/or MAX limits are 100% tested at 25 C, unless otherwise specified. Temperature limits establishedby characterization and are not production tested.7. Limits established by characterization and are not production tested.9FN7557.1March 18, 2010
ISL62883CGate Driver Timing Simplified Application CircuitsV 5V 5VinVDD VCCP CVinVCCUGATEFCCMPHASEISL6208RntcoV 5Rs3PGOODVR TT#CLK EN#VID 0:6 PSI#DPRSLPVRVR ONPGOODVR TT#CLK EN#VIDsPSI#DPRSLPVRVR ONVWUGATE2LGATE2VSSP2ISEN2ISL62883C E1VSSP1Rs1ISEN1RdroopVSENCs1Rsum3ISUM (Bottom Pad)VSSISUM-FIGURE 1. TYPICAL 3-PHASE APPLICATION CIRCUIT USING DCR SENSING10FN7557.1March 18, 2010
ISL62883CSimplified Application Circuits (Continued)V 5V 5VinV 5RbiasRBIASRsen3L2Rsen2L1Rsen1BOOTPWM VDD VCCP VINRs3PGOODVR TT#CLK EN#VIDsPSI#DPRSLPVRVR ONVWPGOODVR TT#CLK EN#VID 0:6 PSI#DPRSLPVRVR ONISEN3BOOT2Cs3UGATE2LGATE2VSSP2Rs2ISEN2ISL62883C Rs1ISEN1RdroopCs2VSENRsum3ISUM tom Pad)VSSISUM-FIGURE 2. TYPICAL 3-PHASE APPLICATION CIRCUIT USING RESISTOR SENSINGV 5V 5VinVDD VCCP VINRbiasRBIASPWM3RntcNTCoCPGOODVR TT#CLK EN#VIDsPSI#DPRSLPVRVR ONVWPGOODVR TT#CLK EN#VID 0:6 PSI#DPRSLPVRVR E1aVSSP1Rs1ISEN1Cs1VSENISUM (Bottom Pad)VSSISUM-FIGURE 3. TYPICAL 2-PGHASE APPLICATION CIRCUIT USING DCR SENSING11FN7557.1March 18, 2010
ISL62883CSimplified Application Circuits (Continued)V 5V 5VinVDD VCCP VINRbiasRBIASPWM3RntcNTCoCBOOT2PGOODVR TT#CLK EN#VIDsPSI#DPRSLPVRVR ONVWPGOODVR TT#CLK EN#VID 0:6 PSI#DPRSLPVRVR SENISUM m Pad)VSSISUM-FIGURE 4. TYPICAL 1-PHASE APPLICATION CIRCUIT USING DCR SENSING12FN7557.1March 18, 2010
ISL62883CTheory of OperationVWMultiphase R3 ModulatorMASTER CLOCK VE CIRCUIT 1VWClock1SRQPWM1 E CIRCUIT 2VWClock2SRQPWM2 Phase2L2Clock3PWM3IL2VWVcrs2gmCrs2SLAVE CIRCUIT 3VWClock3SRQPWM3 Phase3L3IL3Vcrs3Vcrs1Vcrs3Vcrs2FIGURE 7. R3 MODULATOROPERATIONPRINCIPLES IN LOAD INSERTIONRESPONSEgmCrs3FIGURE 5. R3 MODULATOR CIRCUITVWHystereticW indowVcrmCOMPMasterClockThe ISL62883C is a multiphase regulators implementingIntel IMVP-6.5 protocol. It can be programmed for1-, 2- or 3-phase operation. It uses Intersil patentedR3 (Robust Ripple Regulator ) modulator. The R3 modulator combines the best features of fixedfrequency PWM and hysteretic PWM while eliminatingmany of their shortcomings. Figure 5 conceptuallyshows the ISL62883C multiphase R3 modulatorcircuit, and Figure 6 shows the operation principles.A current source flows from the VW pin to the COMPpin, creating a voltage window set by the resistorbetween the two pins. This voltage window is calledVW window in the following discussion.Clock1PW M1Clock2PW M2Clock3PW M3VWVcrs2 Vcrs3Vcrs1FIGURE 6. R3 MODULATOR OPERATIONPRINCIPLES IN STEADY STATE13Inside the IC, the modulator uses the master clockcircuit to generate the clocks for the slave circuits. Themodulator discharges the ripple capacitor Crm with acurrent source equal to gmVo, where gm is a gainfactor. Crm voltage Vcrm is a sawtooth waveformtraversing between the VW and COMP voltages. Itresets to VW when it hits COMP, and generates aone-shot master clock signal. A phase sequencerdistributes the master clock signal to the slave circuits.If the ISL62883C is in 3-phase mode, the master clocksignal will be distributed to the three phases, and theClock1 3 signals will be 120 out-of-phase. If theISL62883C is in 2-phase mode, the master clock signalwill be distributed to Phases 1 and 2, and the Clock1and Clock2 signals will be 180 out-of-phase. If theFN7557.1March 18, 2010
ISL62883CISL62883C is in 1-phase mode, the master clock signalwill be distributed to Phases 1 only and be the Clock1signal.Each slave circuit has its own ripple capacitor Crs,whose voltage mimics the inductor ripple current. A gmamplifier converts the inductor voltage into a currentsource to charge and discharge Crs. The slave circuitturns on its PWM pulse upon receiving the clock signal,and the current source charges Crs. When Crs voltageVCrs hits VW, the slave circuit turns off the PWM pulse,and the current source discharges Crs.Since the ISL62883C works with Vcrs, which arelarge-amplitude and noise-free synthesized signals,the ISL62883C achieves lower phase jitter thanconventional hysteretic mode and fixed PWM modecontrollers. Unlike conventional hysteretic modeconverters, the ISL62883C has an error amplifier thatallows the controller to maintain a 0.5% output voltageaccuracy.Figure 7 shows the operation principles during loadinsertion response. The COMP voltage rises during loadinsertion, generating the master clock signal morequickly, so the PWM pulses turn on earlier, increasingthe effective switching frequency, which allows forhigher control loop bandwidth than conventional fixedfrequency PWM controllers. The VW voltage rises asthe COMP voltage rises, making the PWM pulses wider.During load release response, the COMP voltage falls.It takes the master clock circuit longer to generate thenext master clock signal so the PWM pulse is held offuntil needed. The VW voltage falls as the VW voltagefalls, reducing the current PWM pulse width. This kindof behavior gives the ISL62883C excellent responsespeed.The fact that all the phases share the same VWwindow voltage also ensures excellent dynamic currentbalance among phases.ISL62883C can operate in diode emulation (DE) modeto improve light load efficiency. In DE mode, the lowside MOSFET conducts when the current is flowing fromsource to drain and doesn’t not allow reverse current,emulating a diode. As Figure 8 shows, when LGATE ison, the low-side MOSFET carries current, creatingnegative voltage on the phase node due to the voltagedrop across the ON-resistance. The ISL62883Cmonitors the current through monitoring the phasenode voltage. It turns off LGATE when the phase nodevoltage reaches zero to prevent the inductor currentfrom reversing the direction and creating unnecessarypower loss.If the load current is light enough, as Figure 8 shows,the inductor current will reach and stay at zero beforethe next phase node pulse, and the regulator is indiscontinuous conduction mode (DCM). If the loadcurrent is heavy enough, the inductor current willnever reach 0A, and the regulator is in CCM althoughthe controller is in DE mode.Figure 9 shows the operation principle in diodeemulation mode at light load. The load getsincrementally lig
Multiphase PWM Regulator for IMVP-6.5 Mobile CPUs and GPUs ISL62883C The ISL62883C is a multiphase PWM buck regulator for miroprocessor or graphics processor core power supply. The multiphase buck converter uses interleaved phase to reduce the total output voltage ripple with each phas
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The PWM input wire (orange) and the feedback wire (white) for each servo will be attached to the Arduino pins as follows: Servo One - PWM - Digital 8, Feedback - Analog 1 Servo Two - PWM - Digital 9, Feedback - Analog 2 Servo Three - PWM - Digital 10, Feedback - Analog 3 Servo Four - PWM - Digital 11,
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Buck Converter Single Phase Multiphase Boost Converter Single Phase Multiphase Buck-Boost Single Phase Sinusoidal Excitation Circuits Design Study - Coupled Cyclic Cascade Multiphase Inductors The Design Studio is used to investigate the performance of two coupled structures for use in a multiphase
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