Nov. DesignandRealization A Multiphase- Interleaved VRM .
The 33rd Annual Conference of the IEEE Industrial Electronics Society (IECON)Nov. 5-8, 2007, Taipei, TaiwanDesign and Realization of a Digital MultiphaseInterleaved VRM Controller Using FPGAYi-Chung Wang and Ying-Yu Tzou, Member, IEEEPower Electronics & Motion Control Lab.Advanced Power Electronics Center (APEC)National Chiao Tung Univ., Hsinchu, TaiwanAbstract - Voltage Regulator Modules (VRM) are used for lowvoltage, high-current dc-dc converters used for highperformance microprocessors and graphic processors. Thispaper describes the development of a digital PWM controllerarchitecture in applications to multiphase-interleaved VRM. Adigital current control technique with interleaved PWMgeneration and synchronous current sampling has beendeveloped to improve the transient response under large loaddisturbances. The proposed control scheme for the interleavedmultiphase buck converter employs feedback signals of outputvoltage, output current, and per-phase inductor current. Byusing a synchronous over-sampling technique for the detectionper-phase inductor current and double-edge PWMmodulation technique, the current response can reach a deadbeat performance for step current command. Current sharingcontrol is used to equalize the current of each phase converterunder possible parameters mismatch. A computer simulationstudy has been carried out to illustrate the feasibility andperformance of the proposed digital control technique.Index Terms- VRM, multiphase buck converter, interleaved,synchronous sampling, FPGA digital control, current sharingcontrol.I.INTRODUCTIONIn order to reduce the power consumption of advancedmicroprocessors, various technologies are being developedto solve this challenging power design issues. These includelow power VLSI design technique, asynchronous digitalcircuit design technique, dynamic power management,adaptive voltage scaling, and parallel processing technique.Modern microprocessors are designed with lower voltagepower supply to reduce power consumption in reachinghigher clock rate and higher chip density. Whenmicroprocessor suddenly turns on, it needs plenty of currentin short time. Low operating voltages and highly dynamicnature of the modern microprocessors require tightlyregulated supply voltage. The requirement of dynamic andsteady state become stricter and design process of powersupply become harder.The VRM is designed to provide scalable outputvoltage with low output voltage and high output current thatmeet the fast dynamic response requirements of advancedmicroprocessors [1]. In order to improve the power densityand efficiency of the VRM, the multiphase-interleavedsynchronous buck converter is a major choice in thisapplications [2]-[3]. The multiphase-interleaved convertersare used to solve the need of high power high current andbetter efficiency. Phase-shift interleaved PWM scheme caneffectively reduce the output ripple and distortion withlower switching frequency. The mismatch of device in each1-4244-0783-4/07/ 20.00 C 2007 IEEEV&Fig. 1. Block diagram of a four-phase interleaved VRM buck converterwith closed loop control.phase causes the phase current mismatch [4], and the costof VRM will be increased. As a result, some controlschemes are proposed to control the current sharingproblem [5]-[6].This paper proposes a digital realization technique of afour-phase interleaved PWM converter with digital closedloop regulation to reduce its output current ripple withlower PWM switching frequency. Digital current loopcontrol and DPWM control is adopted to solve the possiblecurrent mismatch problem. In Section II, the inductorcurrent and output voltage ripple between single-phase andn-phase VRM are analyzed and compared at their openloop steady-state. Section III describes the hardware designand implementation of the proposed digital control scheme.The developed digital VRM controller includes a phaseshift PWM generator, a digital compensator, and asynchronous ADC sampler. The simulations study of thedesigned digital controller is given in Section IV andSection V is the conclusion.II. DIGITAL CONTROLLER DESIGN FOR VRMFig. 1 shows the block diagram of the proposed digitalcontroller for the four-phase interleaved VRM buckconverter. The output load current is aloes used as feedbackto improve dynamic response under large step load change.The core of the digital VRM buck converter is a digitalmulti-phase PWM control with a synchronously controlledmultiplexed ADC converter. The ADC converter issynchronized with both the leading and trailing edges of thePWM output signals and timed to trigger in sampling themiddle points of both the rising and falling slopes of theper-phase triangular current. A current sharing controller isused to generate the desired current command of each phaseconverter within half of its switching period. A digitalphase-shift controller is used for generating four pairs ofphase-shifted PWM signals and a programmable dead-time1978
controller is designed to prevent shorted-circuit operation ofeach phase leg. A digital compensator is designed for theloop compensation of the switching amplifier. Theadvantages and design issues of the proposed digitalcontroller for multiphase dc-dc converters are addressed inthe following.A. Reduction of Total Inductor Current RippleAssume the system works in CCM, for single-phasebuck converter, the current ripple of total current could beexpress as:AI Alp inVO )vV j(vrn-vo)2. Vin toFig. 2. Block diagram of current loop of the four-phase VRM.(1)tsfwhere V0 is the output DC voltage, Vrn is the input DCvoltage, f, is the PWM switching frequency, and Lodenotes the output inductance for a single-phase buckconverter. The current ripple of n-phase interleaved VRM is:l VI(Vin -KV) AI1pnv 2 . Vi, . L, . n .n(2)and the output ripple current can be reduced by a factor n.The reduction of the totoal inductor current ripple meansthat we can choose a smaller output filter capacitor or tolower the switching frequency of each phase converter toachieve a same output voltage ripple.Fig. 3. Block diagram of digital controller.fiLdt B. Reduction of Output Voltage RippleThe output voltage ripple in a single-phase buckconverter could be derived asO-(iLoAVOIolp 16 VnC fswo(3)and the output ripple of n-phase interleaved VRM is:\VAVJ1PVO (Vin -VO)(n fSw)2 n2o 16. Vin LO C(4)Therefore, the value of the output voltage ripple can bereduced by a factor of n2. In practical applications, the ESRof the output filter can significantly increase the outputvoltage ripples due to its voltage drops. A set of parallelconnected capacitors can be used to minimize this effect.However, variations of the filter inductance and RDs(on) ofthe power MOSFET of per-phase converter will unbalancethe current sharing for each phase converter and properfeedback control technique is needed to be developed tosolve this problem.Fig. 2 shows the block diagram of current loop of thefour-phase VRM. The voltage applied to the inductor andcurrent injected into the output capacitor can be expressedasLanddiLi iLirLidtVd, -vo(5)iLrc v(6)where iLi denotes the current of each phase and iL is the totalcurrent. The key for the current sharing control of aninterleaved multi-phase converter is to fast and robustcurrent response under specified parameter variations. Aninner current loop controller is applied to each per-phaseconverter to achieve fast dynamic rsponse and an integratedvoltage loop controller is applied for the regulation of theoutput voltage. A dgital current command is generated atevery synchronous sampling frequency to achieve a dedbeatcurrent response control.In order to avoid the switching noises and get theaccurate averaged value of the inductor current, thesampling of the phase inductor current is triggered by itsPWM signal on both leading and trailing edge to get themid-point value on rising and falling slopes. The FPGAcircuit realization has been used for both simulation andexperimental verification of the proposed digital controlscheme for multi-phase interleaved dc-dc converters. Fig. 3shows the functional block diagram for the realization ofthe proposed digital multiphase interleaved PWM controller.III. DIGITAL CONTROLLER REALIZATION ISSUESIn the realization of digital controller, some keyspecifications should be defined to determine the designparameters, such as the system operating frequency, digitalsampling frequencies, and the computational format of eachcontrol parameters. The proposed VRM control scheme isrealized by using a single-chip FPGA EP2C35 from Altera1979
lFI ', 1 . . I 31 2zi 1FtiSTABLE IPIN DEFINITION OF THE DPWM GENERATORRaligeCLKW0 J1SYMSw0/1i-A/4096*BY409D es lipt-ioiiEtelual clock, miiax 200IMHzSylimi11etiic selectioii0synInietfic waveasy lunieiic wvaveReset output0 disable outputI eniable outputPIase sluift0 disableI eliable1RSTW0 1PHSHW01 1PHAM[2 0]W0-7FSW[1 1 0]W0 4095 Switch frequieiicy FSW/CLKDT[6 O]W0-127VC MD[ 11 0 ]W0 4095 PWMhmput sigiialPH1C-PH4CR0 14Fig. 5. Block diagram of compensator.Fig. 4. Block diagram of digital PWM generator.Stat-tis.7 7Fig. 6. Hardware circuit schematic of compensator.out put phase niunbeer PHN -1Dead-time DT/CLKPWM outpit signalCyclone II device family. The CycloneTM J devices offer upto 150 18-bit x 18-bit embedded multipliers capable ofimplementing common digital signal processing (DSP)functions such as finite impulse response (FIR) filters, fastFourier transforms (FFTs), correlators, encoders/decoders,and numerically controlled oscillators (NCOs). Theembedded multipliers provide higher performance and logicefficiency compared to logic element (LE) basedmultipliers. The embedded multipliers in Cyclone IIdevices are ideal for low-cost DSP and high-performancedigital control applications. The design and realization foreach control block of the proposed VRM controller isdescribed in the following.A. Interleaved DPWM GeneratorThe increasing of PWM frequency and resolution willrequire a very high clock frequency and imposes a designconstraint both for high-frequency digital circuit design andcost. Various realization schemes, such as countercomparator, delay-line, and hybrid one, etc., have beendeveloped for the generation of digital PWM signals inorder to reduce the clock rate for an acceptable PWMresolution.Higher switching frequency also companies with higherswitching losses and electromagnetic interference.Therefore, it becomes a design trade-off between therequired PWM switching frequency, control resolution,control scheme, and circuit topology. Interleaved PWMtechnique with phase-shift control has been developed forhigh-density DC-DC converter to enhance its current outputcapability in VRM applications. Phase-shift interleavedPWM scheme can effectively reduce the output ripple anddistortion with lower switching frequency.Fig. 4 shows the functional block diagram of theproposed DPWM and the pin definition of the digital PWMgenerator is listed in Table I. In the proposed approach, thetiming clocks for the digital controller and the digital PWMgenerator are interlaced with each other to achieve aminimum delay at a same sampling and switchingfrequency. The DPWM is designed to apply flexibility todifferent power applications. The interleaved phases, deadtime setting, symmetric or asymmetric reference carrieralternating, and PWM switching frequency, is designed asprogrammable. The maximum speed of DPWM can beclocked to 200MHz.The PWM reference carrier generators are set into twosources which can both produce symmetric and asymmetricreference carrier waveforms. Setting the "SYMIASYM" pin,we can decide which one to pass on to the comparator. Thewaveform of SYM is triangular and ASYM is sawtoothwave. This carrier signal is compared with the modulationsignal to generate a timing triggered PWM signal.By the shape of the modulation sawtooth wave, thereare leading-edge modulation and trailing-edge modulation.Both of them belong to asymmetric wave, while the dualedge modulation is the symmetric reference. The leadingedge modulation scheme is good for the transient of load-1980
I ,tTriangular waveformactive-selectsamplingselectD QI/DQ1/\1\i\/i,Fig. 7. Circuit realization of the synchronous current sampling scheme.2MIDS.'K )atMD,.{ y(n) Ko (w(n) - AOw(n -1))w(n) x(n)- Bo w(n-1).I 2M IN02-.g.:4E Io3o(a)Fig. 5 shows the block diagram of the designed digitalcompensator. A scheduling strategy for realizing the PIcontroller by using finite-state-machine (FSM) is presented.Fig. 5 shows the hardware circuit architecture of thecompensator. The whole computing process takes oneadder, one unit delay register, and one multiplier.Furthermore, each control parameters can be programmed.The compensator can be separated into two parts. One isthe PI controller, the other is lead controller. The limiter inthe integrator of PI controller is designed programmableboundary. The lead controller is implemented with directform II, and the difference equation of lead controller couldbe derived as: B0z't26.PB. Digital CompensatorKI0 1 D-Ao1Signal\Fig. 8. Timing diagram of the synchronous sampling process.adding event. In the other hand, the trailing-edgemodulation is good for load-releasing transient event. Tosuit different kinds of application, sometimes we have tochange the modulation carrier. That's why the block offersthe different modulation reference.In order to prevent the two switches of each phase inVRM system from conducting in the same time, dead-timeis required to design into the PWM signal. The dead-time isprogrammable for the symmetric carrier wave. The phaseshifter can offer up to 4 pairs PWM signal that determinethe switches on/off in VRM. Divider and multiplier areapplied to generate different number of phase. The phasesof each output will be shifted with 2fz ! n degree. /I, ,II/l WPWto ADCclockD(z) Y(Z)x(z)/\KU)M MO. . '.'.'--'.''''.'9.'.'.''.'.'-'Vsbo1' 0 i2Pl8M--,. ,-.b ,. , , ,.(b)(5)Fig. 9. Output voltage and phase currents for load current step up (a)without feedback control, and (b) with feedback control. C. Synchronous SamplingThe current control loop of a DC/DC converter plays animportant role for robust performance and current sharingcontrol for multiphase synchronous buck converter,however, the switching of power transistors will inducevoltage spikes in the current sensing circuit due to thecommon-mode noises. These coupling noises not onlycorrupt the dynamic response of the current loop they mayalso cause result system unstable. This phenomenon isespecially severe in a digital current control loop when thesampling frequency is asynchronous with the switchingfrequency.The low-pass filters within the feedback loop can reducehigh frequency noises, however, they also impose timedelay and slow down the dynamic response. Therefore, theuse of low-pass filters for feedback signal detection shouldbe avoided in VRM applications. Because the switchingnoise is synchronized with its PWM switching, we cansample the current signal in the middle of the two switchingto obtain a maximum signal-to-noise ratio. Fig. 7 shows thesynchronous sampling circuit. The sampling mode can bechosen as rising or falling, while the active mode can be setas active low or active high.In order to sample the phase current and prevent thecurrent spike or disturbance, the synchronous sampling1981
TABLE IIPARAMETERS OF THE DESIGNED FOUR-PHASE VRM.Vrefreference voltage1.2VVininput voltage5Vkn.umber of phase4.:.switching frequencylOOkHzLiphase inductors4.8uHCO1 OnFrLoutput capacitanceinductor ESRrccapacitor ESRVI ef.reference voltage(a).mQImQ.1.2Vcircuit offers the sampling signal by the PWM carrier wave.The load current is sampled in each synchronous digitalcurrent control loop and is used as the current feedback forload current sharing control.Fig. 8 shows the illustrated timing diagram of thesynchronous sampling process. The rising and falling edgeof the PWM switching signal is used to trigger a timer witha preset value of half of its switching intervals during bothon and off periods. The average value of two samples isused as the instantaneous averaged value of the currentsampling period and is used for the current regulation andcurrent sharing control of the digital current controller.IV. SIMULATION VERIFICATIONFig. 9 shows the simulation results of output voltage andphase currents for load current step down without and withfeedback control. By using the interleaved PWM scheme,the inductor current ripple could be reduced. Table II showsthe typical parameters of a designed four-phase VRMconverter. The load current is changed from a light load of0.95A to a heavy load of 25A. It can be observed that thecurrent response is about four sampling periods of thedigital current controller. Fig. 10 shows simulation resultsof phase current response in steady state with unmatchedconverter parameters. It can be observed that the currentderivation due to unmatched parameters can be reduced byusing a designed digital current sharing control scheme.(b)Fig. 10. Simulation results of phase current response in steady state withunmatched converter parameters under (a) open-loop control, and (b)closed-loop control.regulator module]," IEEE ISPED Conf Rec., pp. 51-54, 2004.[2] H. N. Nagaraja, A. Patra, and D. Kastha, "Design and analysis of fourphase synchronous buck converter for VRM applications," IEEE IndiaAnnual Conf:, pp. 575-580, Dec. 2004.[3] S. K Mazumder, and S. L. Kamisetty, "Design and experimentalvalidation of a multiphase VRM controller," IEE Electric PowerAppli., vol. 152, pp. 1076-1084, Sept., 2005.[4] A. V. Peterchev, J. Xiao, and S. R. Sanders, "Architecture and ICimplementation of a digital VRM controller," IEEE Trans. PowerElectronics, vol. 18, pp. 356-364, Jan., 2003.[5] J. Abu-Qahouq, M. Hong, and I. Batarseh, "Multiphase voltage-modehysteretic controlled DC-DC converter with novel current sharing,"IEEE Trans. Power Electronics, vol. 19, pp. 1397-1407, Nov., 2004.[6] J. Agrawal, D. Kastha, A. Patra, and B. Culpepper, "An improvedcontrol scheme for multiphase buck converter circuits used in voltageregulator modules", IEEE Power Electronics and Drives System Confvol. 1, pp. 418-423, Nov., 2005.[7] A. Syed, E. Ahmed, D. Maksimovic, and E. Alarcon, "Digital pulsewidth modulator architectures," Power Specialists Conf 2004 IEEE35th Annual, vol. 6, pp. 4689-4695, June 2004.V. CONCLUSIONThis paper presents the design and realization of adigital current control technique for digital VRM controllerused for high-performance microprocessors. A digital oversampling with double-edge modulation technique has beendeveloped to improve the current response of a multi-phaseinterleaved synchronous buck converter. The proposeddigital current control scheme has been verified by usingco-simulation with MATLAB and Modelsim with FPGAbased fully-digital circuit realization. The experimentalverification of the proposed digital control technique willbe carried out in future research works.REFERENCE[1] Z. Xin and A. Q. Huang, "Investigation of VRM controllers [voltage1982
and efficiency of the VRM, the multiphase-interleaved synchronous buck converter is a major choice in this applications [2]-[3]. The multiphase-interleaved converters are used to solve the need ofhigh powerhigh current and better efficiency. Phase-shift interleaved PWMscheme can effective
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The diagram above shows a Single stage Boost Converter and Interleaved Boost Converter. We can see clearly that in the Interleaved topology, between the input and output stages, there are 2 stages of the power converter in parallel, thereby having 2 inductors, 2 switches and 2 diodes. [6] In the single-phase design, applying a gate voltage to
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