EGO BALLOON DATA PROCESSOR - NASA

The output of each temporary memory can be monitored by an oscilloscope connected to theappropriate DMA OUTPUT pin jack on the rear of the front panel. The duration of each temporary memory (DMA), with the exception of the index bit, is s e t f o r 0.6 millisecond by adjustinga potentiometer on the appropriate module.4 The maximum duty cycle of these modules is 67percent. For a maximum data-repetition rate of 1 kc, the maximum delay can be set for 0.67millisecond, but the normal setting is 0.6 msec. The delay of the index bit is set for one-half ofthe data-bit temporary memory delay, o r 0.3 msec. The trailing edge of this pulse is used tostrobe the information into a storage register. Placing the strobe in the center of the temporarymemory-storage cycle allows f o r maximum skew. 55See Section V-D f e r &sassio of aetrirg the index bit for optimum data recovery.10

V. THEORY OF OPERATIONA. GENERALThe EGO balloon experiment data processor is designed to operate on 16 parallel signals from a16-track magnetic-tape reproducer. The signals of each channel carry information in binaryform, a "one" being represented by one half-wave rectified sinewave pulse having a period of 1millisecond and a peak amplitude of -5 millivolts a t the reproduce heads. A zero is representedby the absence of any signal excursion when an index pulse is present. Before entering theprocessor, each channel is amplified by 60 db so that a "one" pulse is a -5v peak half-waverectified sinewave pulse.The block diagram' or the EGO balloon shcws that each experiment data precessor ampbiiedchannel is applied to a threshold detector. The threshold detectors a r e employed to recognizethe leading edge of the negative excursion of a "one" pulse. The detectors are normally set torecognize only those signals which exceed a negative 2 volts. In tandem with each detector is atemporary memory which serves the purpose of storing the occurrence of a "one" pulse for afinite length of time. This technique is employed to compensate for tape skew.The output of the detector on the index channel (the signal which indicates to the processor thepresence of a parallel word) is applied to the strobe delay, initiating a delayed read pulse throughthe control portion to the temporary memories. The read pulse stores the complement of thestate of each bit memory into the appropriate binary register by way of the patch panel. Theassembly of the experiment words (in one's complement form) is generated by two parallelinput words for Mark IV and a single parallel input word for Mark I1 and Mark III. To distinguish between the initial word and the delayed word for Mark N ,the identification channel carpulse for the delayed word. The control sectionries an ID pulse for the initial word and anrecognizes the presence of the index and the ID to assemble word I, and the presence of theindex andto assemble word 11.With the appropriate assembly of experiment words in one's complement form in registers A,B, and C, and the storage of the sensitivity bit in the decimal counter, the control section provides a s e r i a l count pulse to each of the three experiment word binary registers3 converting theone's complement representation to two's complement representation. Following this is a serialreadout of each of the binary registers into modified commercial decimal counter . The numbersstored in the decimal counter will then be the decimal equivalent of the binary experiment word.5The sensitivity bit is stored in the decimal counter also. Storage of each word and the sensitivitybit are kept independent from each other through modification of the decimal counters.The magnitude of the word stored in register A before serial readout determines whether thedata point (the information contained in all registers) will be accepted. If the magnitude of thecount stored in register A is greater than a patched preset number, the information will beaccepted and serial readout will proceed; if the count is less than the patched preset number,then the processing of information f o r that data point will be stopped and cleared so that the nextevent o r parallel input word will be accepted.After the experiment words are stored in decimal form in the decimal counters, a print-commandpulse is generated to a commercial printer which prints the information stored in the counters.The print cycle requires 200 milliseconds. During the time of printing, the control section'See Figure 16 in section containing schematic diagrams.2See discussion on tape skew, part D of this section.3For Mark 11 and Mark Ill, only two experiment words ( A and 8 ) are employed.*Hewlett-Packard Model 5532A.'See discussion in Section V-B on conversion of binary to decimal form.'See discussion in Section V-C on recognition of a data point that exceeds a preselected number.'Hewlett-Packard Model 562A.11

generates a lockout pulse that inhibits the generation of new data strobes, thereby preventingthe entrance o r processing of any new data until the termination of printing.Incorporated in the EGO balloon experiment data processor is a simulation mode in which thedata-line inputs are switched out and simulated data are applied to the threshold detectors. Byobservation of front panel indicator lights and operator control of simulated data words, the unitcan be checked for proper operation.B. BINARY-TO-DECIMAL CONVERSIONA translation can be made from the binary to the decimal system by first placing the 2's complement of the bi-nary .n.urr.ber isto 2 register which aiso can operate as a binary counter, then applying a serial train of pulses simultaneously to both the binary counter and a decimal counter. Theconversion is obtained by counting the number of counts in the decimal counter required to clearo r recycle the binary register.An algorithm* f o r determining the complement of a number N is:N r'sComplement r n - Nwhere:Transposing:n number of digits in the number NN the numberr the radix o r basetN r"Since a counter can count to r n - 1 , the counter h a s to pass through a z e r o count o r recycle if theoriginal number is serially added to the complement previously stored in the register; i.e., ifN counts are added to a binary counter storing (the two's complement of N in this case), thenthe counter will end in a "0" state.For ease of implementation, the 1's Complement is entered into the binary register and thisnumber is converted to 2's complement by adding a count to the counter.An algorithm for relating 2's complement (radix complement) t o 1's complement (diminishedradix complement) is:N r"-N-r-"'-where:N diminished radix complementF o r the 1's complement, m 0, so thatNrn-N-1*Reference 1 .12

The translation to decimal form by serial readout begins after the 1's complement has been converted to the 2's complement. A s an illustration, consider the conversion of the binary number0011101 (29,,) that is stored in a seven-stage binary register t o a decimal number:FormulasCarry-N r"-N-110000000(rn 2')-11111111(rn-1)-0011101(-N)11oO0105 111oO011 0011101( N 29,,)C. RECOGNITION OF A DATA POINT THAT EXCEEDS A PRESELECTED NUMBERThe limited speed of the digital printer makes it necessary to obtain printouts of only good datapoints, because these printouts represent only 0.5 percent of the maximum data rate. In theMark 11, Mark 111, and Mark IV experiments there are certain conditions under which low countscan be discarded before the time-consuming conversion begins. When accepting data, the dataprocessor will determine whether or not a data point exceeds a predetermined level. When theprocessor decides to accept a data point for processing, a lockout or inhibit mode is generatedwhich prevents the processor from accepting any additional data points until the digital printcycle is completed.The decision process is illustrated by the truth table on the following page.The 1's complement of the data point is stored in the binary register. The set side of the mostsignificant bits of the register are connected to a gate that generates a "stop" condition when allof the inputs a r e true ( l ) , and a "go" condition if any one of the inputs is false (0). The logic isillustrated in Figure 3.For example, consider a situation in which any d&a point w i t h c o u n t less than 8 can be discarded. The set side of the register from bit 4 (23) to bit n(2" - ') is programmed to the gate.When all the inputs are true (l),which corresponds to a digital number of less than 8, a stopcondition is generated. When any stage of the set side of the register programmed t o the gatebecomes false (0), the number equals or exceeds 8 and a go condition is generated.13

Table 5Truth Table f o r Word A Greater Than 1118110190-- -ABM - (2").M A B .M(Sheffer Stroke)Figure3-TheN A N D FunctionThe processor can be programmed to recognize any data point that has a count exceeding 2"where n equals zero o r any integer. There is also a provision which enables the processor toprocess all data, regardless of the count.D. COMPENSATION FOR TAPE SKEWTo recover the maximum amount of data when skew problems are present, the incoming databits are stored in temporary memories at a fixed time interval after occurrence of the INDEXbit, and the information is simultaneously strobed f r o m all the bit memories into binary registersf o r further processing.A delay multivibrator with a 67-percent duty cycle is used as a temporary memory device. F o ra maximum repetition rate of 1 kc, the maximum memory duration that can be obtained is 0.67ms. As a margin of safety, all the data memories are preset to provide a storage time of 0.60ms, and the data-strobe delay generator is preset 'to provide a delay equal to half the memoryduration, or 0.3 ms. This is the optimum setting f o r recovering data with the greatest symmetrical skew.14

If the recorded tape has static skew o r if the playback head stack is misaligned, the strobe pulsecan be elongated o r shortened, depending on the time bias introduced by the skew.The following examples illustrate data recovery with dynamic skew.Example 1:In Figure 4, the data-information pulse is in phase with the index pulse that generates the datasampling strobe. The data could, therefore, be strobed at the center of the data memory-storagecycle as shown. This would be the setting of the data strobe delay for an ideal situation whereno skew o r misaligned data pulses are present.Data channelIII/-----Detection- - -level-Strobe channel-L e t st iznData memoryhvd60.6MSII--IIII0.3MSDelay time for strobeI- qIIData strobeIStrobe samples data in the center of its memory cycle.and index track displaced by 0'.Figure 4-BitNo skew- data tracksDetection with 0" SkewE x a m d e 2:In Figure 5, the information pulse from the data channel was delayed by 108" (0.3 msec) withreference to the pulse that produces the generated strobe. The sampling strobe, which isgenerated from the trailing edge of the delayed strobe pulse, will sample the data pulse at theleading edge of the data memory pulse.15

Data channelIII-Detection- - - - - level- -1IIIIIIIStrobe channelIIIIIIIiIIData strobeIUStrobe samples data on the leading edge of the memory cycle.Data track displaced from index track by -loa0.Figure 5-Bit Detection with -108" SkewExample 3:In Figure 6, the information pulse from the data channel precedes the pulse that generates thestrobe by 108" (0.3 msec). The sample strobe now samples the data pulse at its trailing edge.I-Under actual operating conditions, all three of the examples can happen simultavously; Le., fora given word the data pulses in the various tracks can lead, lag, and be in phase with the indexpulse that generates the strobe. When the memories and strobe delay are set for the valuespreviously mentioned, the system will accurately process data that vary within 1108" withreference to the index bit that produces the sampling strobe.16

Data channelDetection level-- ----IIIIIIIIIIStrobe channelIlevel-Detection- - - I------IIIData memoryIIIIIIIIIIDelay time for strobeData strobeUStrobe samples data on the trailing edge of the memory cycle.track displaced from index track by 108O.Figure 6-Bit Detection with17 log0 SkewData

VI. DESCRIPTION OF LOGICA. Control UnitMark IV Control Logic'The incoming data signals, after being detected by the Schmitt triggers, are stored in a temporary memory (delay multivibrator) until the complement of the data word is strobed into abinary register. The index and the ID pulses are detected by their respective Schmitt triggers(1-8-27 and 1-9-10). When they a r e in coincidence, an initial strobe (1-23-13) is generated fromthe trailing edge of the index pulse (TLN-7).*The initial strobe (I.S.) generates a gating pulse approximately 2 msec long (1-22-17). Whenanother index pulse appears within this interval and no ID pulse is present, a delayed strobe(DS) pulse is produced (TLN-10).The initial strobe (IS) samples the incoming data lines and enters the complement of the data inthe appropriate binary registers. A comparison is made between the data word entered in the "A"register and a preprogrammed word;j if the incoming data word is equal to o r greater than theprogrammed word, a gate is enabled that allows the delayed strobe (DS), with a 10-ps delay(11-21-16), to add an extra count to the three binary registers, reset the commercial decimalcounters, and (after a 100-ps delay) gate a multivibrator's output to the input of the three registers.The data are then passed through level-matching circuits to the inputs of the decimal counter . The sensitivity bit is gated with the delayed strobe (1-20-16) to set a flipflop (I-18-27), whoseoutput is gated with the extra count pulse through a level-matching circuit directly to the splitinput of the decimal counter. The sensitivity word has only two states, true (-6 volts) and false(0 volts). The true condition in the printout is represented by a decimal "l", the false conditionby a "0".The s a m e pulse that gated the multivibrator's output to the registers also initiates a 10-msecdelay pulse (1-21-11) that turns off the multivibrator after the conversion.The pulse that generated the extra count (TLN-11) initiates a 200-msec inhibit (II-21-34) thatdisables the controlinput (1-23-13) so that new data will not be accepted f o r processing whilethe printer is operating.If the data word entered in the "A" register is less than the preset number, the delayed strobe,with an additional 20-psec delay, is used to generate a 200-psec pulse (1-22-31) that resets thebinary registers and allows the system to accept new data.Mark 11-111 Control Logic5 (Refer to diagram GD-EGO-111-4531)The index pulse is detected by the Schmitt trigger and the leading edge of the pulse is delayedby approximately 0.3 msec and this edge is used to generate a lO-/,sec strobe pulse (1-22-10).The strobe pulse is gated with the 5 bit (1-23-9) in the ABC mode of operation. When in theABC mode of operation and with the absence of the C bitthe 10-psec pulse is used to strobethe complement of the data into the appropriate binary registers. If the C bit is present, thee),'See Figures 18 and 19 in the section containing diagrams.*The notation TLN- will be used to refer the reader to the timing line numbers on Figure 22 in the section containing diagrams.3Refer tn Figure 23 for appropriate programming.4The six-stage decimal counters are split internally into two three-stage counter circuits, so that each counter can accept two different inputs and can convert binary numbers to an equivalent decimal count of 999.'See Figure 18 in the section containing diagrams.'The control switch A B c - A B i s located on the front panel.18

10-psec pulse is inhibited and no further processing occurs. When in the AB mode, all data areprocessed regardless of the condition of the c bit.After entry of the complement of the data word into A register, the processing is the same as inthe Mark IV mode of operation.B. REGISTERS A, B, AND C(Diagrams GD-EGO-1114-532, 533, 534)'Register A (Diagram GD-EGO- 1114-532)The output of the Schmitt trigger data detection circuit is connected to a gate whose output, whenstrobed, sets the dc-set side of a binary register. When no data pulse is present at the occurrence of an input word, the gate is enabled and the initial data strobe2 s e t s each binary registerof the counter to the complement of the input. When a data pulse is present, the gate is inhibitedand the register is left in the reset o r the false condition; i.e., the register is s e t to true (-6volts) when the input data line is false, o r to false (0 volts)

EGO BALLOON EXPERIMENT DATA PROCESSOR I. INTRODUCTION The EGG 'balloon experiment data processor (Figure I) is designed to operate on prelaunch data for the EGO series satellites: specifically, experiments Mark 11, Mark 111, and Mark IV.These experiments, carried by balloon fli