ECE520 VLSI Design
ECE520 – VLSI DesignLecture 0: Introduction to VLSI TechnologyPayman Zarkesh-HaOffice: ECE Bldg. 230BOffice hours: Wednesday 2:00-3:00PM or by appointmentE-mail: pzarkesh@unm.eduECE520 - Lecture 1University of New MexicoSlide: 1
Course Objectives We will focus mainly on CMOS integrated circuits There will be a design project assigned including: Schematic design using S-EditSpice simulations and design verificationLayout design using L-Edit (including LVS and DRC)Circuit extract and spice simulation (again) Project will be done by groups of 3 students Project grade will be based on: Quality of reportPerformance (speed/delay)Power dissipationLayout area There will be a 10% extra credit for any design that beats certaincriteria for layout area, performance, or power consumptionECE520 - Lecture 1University of New MexicoSlide: 2
Textbook and References Main textbook: “Digital Integrated Circuits” by J. M. Rabaey et al. (2nd edition) Other reference books: “Physical Design of CMOS Integrated Circuits Using L-Edit” by J. Uyemura “Design of High-Performance Microprocessor Circuits”, by A. Chandrakasan Lecture Notes: combination of slides and discussions Slides will be posted on the class webpage Class webpage: www.unm.edu/ pzarkesh/ECE520 Reference papers posted on the class webpageECE520 - Lecture 1University of New MexicoSlide: 3
Grading Policy Your grade in the course will be comprised of: HomeworkProjectMidterm ExamFinal Exam(25%)(25%)(25%)(25%) Final letter grade will be based on curve and class performance No makeup examECE520 - Lecture 1University of New MexicoSlide: 4
Homework Policy Homework will be on weekly basis and is setup for the project Learn CAD tools and basic circuits Require lab work Solutions will be posted on the class website as soon as I can Late homework and projects have 20% per day credit penaltyECE520 - Lecture 1University of New MexicoSlide: 5
Class Project & Tools Use of CAD tools will be required for most assignments. Getyourself familiarized with the tools from today! This is a project oriented course. Be prepared for extensive labwork! We will be using L-Edit for our VLSI project all Tanner tools including L-Edit, S-Edit, T-SPICE, LVS, and W-Edit areinstalled on all machines in ECE 211 Lab The tools can also be installed on your own computer for the project use for more information about these tools, please visit class website We will be using ON Semiconductor 0.5um for our project Selected projects will be submitted for manufacturing by MOSIS for more information about this process please ductor/c5ECE520 - Lecture 1University of New MexicoSlide: 6
Projects Manufactured by MOSIS in 2009Test Chip 1ECE520 - Lecture 1University of New MexicoTest Chip 2Slide: 7
Projects Manufactured by MOSIS in 2010Die Photograph of the Test ChipECE520 - Lecture 1University of New MexicoSlide: 8
Projects Manufactured by MOSIS in 2011Die Photograph of the Test Chip 2ECE520 - Lecture 1University of New MexicoSlide: 9
Projects Manufactured by MOSIS in 2012ECE520 - Lecture 1University of New MexicoSlide: 10
Projects Manufactured by MOSIS in 2019ECE520 - Lecture 1University of New MexicoSlide: 11
Class ScheduleECE520 - Lecture 1University of New MexicoSlide: 12
Reading Assignment Today we will review Chapter 1 and some more Introduction and history Our next class will be on Chapter 3 (MOS Physics) Skim through Diodes but focus on Section 3.2.3 (diode transient behavior) Study Section 3.3 (MOS transistor) thoroughly We will get back to Chapter 2 (Manufacturing Process) laterECE520 - Lecture 1University of New MexicoSlide: 13
VLSI Design Flow The goal of VLSI designers is to design a circuit block thatmeets the following objectives: Maximize speed or performanceMinimize power consumptionMinimize areaMaximized robustness Methods that they use are: Circuit design, transistor sizingUse of new architectures, clock gating, etcChoice of circuit style, efficient layout designInterconnect design and optimizationECE520 - Lecture 1University of New MexicoSlide: 14
VLSI Design Approaches Gate Arrays (Old technology, but still attractive) Pre-fabricated chips containing transistors and local wiring Upper level wires added to implement design Rapid design, but very sub-optimal, slow, and usually high powerconsumption Standard Cells (Used for ASIC design) Cells in a library with fixed sizesCells pre-characterized for delay and powerDesign is fast and layout is done automaticallyBetter performance, in the range of several 100’s MHz Custom Design (Used for Microprocessor design) Optimal circuit design and sizesExtensive design verification requiredSlowest, but densest layout designBest performance, in the range of 1-5 GHzECE520 - Lecture 1University of New MexicoSlide: 15
VLSI Design Tools Synthesis Logic, micro-architecture, automatic physical generation Static Analysis Design rule checking (DRC)Circuit extractionTiming analysisTest generation (ATPG) Dynamic Analysis Architectural simulationLogic simulationCircuit simulation (SPICE)Test verificationECE520 - Lecture 1University of New MexicoSlide: 16
High Level VLSI Design StepsSystem RequirementsLogic Design & SynthesisVLSI Design & LayoutDesign VerificationPassMask GenerationSilicon Manufacturing ProcessWafer Test (sort)PackageFinal TestECE520 - Lecture 1University of New MexicoSlide: 17
IntroductionBeginning of the Computer: ENIAC, the first electronic computer (1946) 333 integermultiplication/second A six-week run wasequivalent to 100person-years ofmanual computation Program resides in thewired connectionsECE520 - Lecture 1University of New MexicoSlide: 18
Intel 4004 Microprocessor 1971 10 um NMOS-only 2300 transistors 1 MHzECE520 - Lecture 1University of New MexicoSlide: 19
Intel Technology AdvancementECE520 - Lecture 1University of New MexicoSlide: 20
Moore’s Law In 1965, Gordon Moore (founder of Intel) had a very interestingobservation. He noticed that the number of transistors on a chipdoubled every 18 to 24 months. He made a prediction that semiconductor technology woulddouble its effectiveness every 18 months.ECE520 - Lecture 1University of New MexicoSlide: 21
Moore’s Law for Intel MicroprocessorsSource: www.intel.comECE520 - Lecture 1University of New MexicoSlide: 22
Projected Wafer in 2000, circa 1975Moore was not always accurateECE520 - Lecture 1University of New MexicoSlide: 23
Die Size GrowthDie size (mm)1001080808008400480868085286386P6Pentium proc486 7% growth per year 2X growth in 10 years1197019801990Year20002010Die size has grown by 14% to satisfy Moor’s law, BUT the growthis almost stopped because of manufacturing and cost issuesECE520 - Lecture 1University of New MexicoSlide: 24
Clock FrequencyFrequency (Mhz)10000Doubles every2 years100010048610808510.119708086 286P6Pentium proc38680808008400419801990Year20002010Lead microprocessors frequency doubles every 2 year, BUT thegrowth is slower because of power dissipation issueECE520 - Lecture 1University of New MexicoSlide: 25
CMOS Scaling ScenarioECE520 - Lecture 1University of New MexicoSlide: 26
CMOS Scaling Calculation14 - 10 - 72002 2004 2006 2008 2010 2012 2014 2016 2018ECE520 - Lecture 1University of New MexicoSlide: 27
The Evolution of Foundry MarketECE520 - Lecture 1University of New MexicoSlide: 28
Cost of Design versus Technology NodeECE520 - Lecture 1University of New MexicoSlide: 29
ECE520 - Lecture 1 University of New Mexico Slide: 14 VLSI Design Flow The goal of VLSI designers is to design a circuit block that meets the following objectives: Maximize speed or performance Minimize power consumption Minimize area Maximized robustness Methods that they use are: Circuit design, transistor sizing Use of new architectures, clock gating, etc
VL2114 RF VLSI Design 3 0 0 3 VL2115 High Speed VLSI 3 0 0 3 VL2116 Magneto-electronics 3 0 0 3 VL2117 VLSI interconnects and its design techniques 3 0 0 3 VL2118 Digital HDL Design and Verification 3 0 0 3 VL2119* Computational Aspects of VLSI 3 0 0 3 VL2120* Computational Intelligence 3 0 0 3
VLSI Design 2 Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device.
VLSI IC would imply digital VLSI ICs only and whenever we want to discuss about analog or mixed signal ICs it will be mentioned explicitly. Also, in this course the terms ICs and chips would mean VLSI ICs and chips. This course is concerned with algorithms required to automate the three steps “DESIGN-VERIFICATION-TEST” for Digital VLSI ICs.
Dr. Ahmed H. Madian-VLSI 3 What is VLSI? VLSI stands for (Very Large Scale Integrated circuits) Craver Mead of Caltech pioneered the filed of VLSI in the 1970’s. Digital electronic integrated circuits could be viewed as a set
15A04604 VLSI DESIGN Course Objectives: To understand VLSI circuit design processes. To understand basic circuit concepts and designing Arithmetic Building Blocks. To have an overview of Low power VLSI. Course Outcomes: Complete Knowledge about Fabrication process of ICs Able to design VLSIcircuits as per specifications given.
55:131 Introduction to VLSI Design 10 . Simplified Sea of Gates Floorplan 55:131 Introduction to VLSI Design 11 . SoG and Gate Array Cell Layouts 55:131 Introduction to VLSI Design 12 . SoG and Gate Array 3-in NAND 55:131 Introdu
Principles of VLSI Design Introduction CMPE 315 Principles of VLSI Design Instructor Chintan Patel (Contact using email: cpatel2@cs.umbc.edu). Text CMOS VLSI Design: A Circuits and Systems Perspective, Third Edition. by Neil H.E. Weste and David Harris. ISBN: 0-321-14901-7, Addison Wesl
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