Chapter 5: Register-Transfer Level (RTL) Design Transzfer .

Laser-Based Distance Measurer—Step 2A: Create aDatapathDistanceMeasurerInputs: B (bit), S (bit) Outputs: L (bit), D (16 bits)Local storage: Dreg, Dctr (16 bits)B'S'S0S1L : '0'Dreg : 0Dctr : 0BS2L : '1'S3SS4L : '0'Dreg : Dctr/2Dctr : Dctr 1 // calculate D1a HLSM data I/O DP I/OHLSM local storage regHLSM state action andtransition condition datacomputation Datapathcomponents and connectionsDreg clrDreg ldDctr clrDctr ldDatapath16ABAdd1: add(16)S1616IShr1: shiftR1(16)Q16Iclrld Dctr: reg(16)QclrldIDreg: reg(16)Q16DDigital Design 2eCopyright 2010Frank Vahid23

Laser-Based Distance Measurer—Step 2B: Connectingthe Datapath to a Controllerfrom buttonLBto laserControllerfrom sensorSDreg clrDreg ldDctr clrDatapathDctr ldDto display16300 MHz ClockDigital Design 2eCopyright 2010Frank Vahida24

Laser-Based Distance Measurer—Step 2C: Derive theController FSMHLSM1DistanceMeasurerInputs: B (bit), S (bit) Outputs: L (bit), D (16 bits)Local storage: Dreg, Dctr (16 bits)B'Dreg clrDreg ldS'S0S1L : '0'Dreg : 0Dctr : 0B FSM has samestates,transitions, andcontrol I/O Achieve eachHLSM dataoperation usingdatapath controlsignals in FSMDigital Design 2eCopyright 2010Frank VahidS2Dctr clrDctr ldS3L : '1'SABAdd1: add(16)S1616Iclrld Dctr: reg(16)S4IShr1: shiftR1(16)Q16clrldQIDreg: reg(16)Q16DL : '0'Dreg : Dctr/2Dctr : Dctr 1 // calculate DInputs: B, SControllerDatapath16Outputs: L, Dreg clr, Dreg ld, Dctr clr, Dctr ldB S aS0S1L 0Dreg clr 1Dreg ld 0Dctr clr 0Dctr ld 0(laser off)(clear Dreg)L 0Dreg clr 0Dreg ld 0Dctr clr 1Dctr ld 0(clear count)BSS2S3L 1Dreg clr 0Dreg ld 0Dctr clr 0Dctr ld 0(laser on)L 0Dreg clr 0Dreg ld 0Dctr clr 0Dctr ld 1(laser off)(count up)S4L 0Dreg clr 0Dreg ld 1Dctr clr 0Dctr ld 0(load Dreg with Dctr/2)(stop counting)25

Laser-Based Distance Measurer—Step 2C: Derive theController FSMControllerInputs: B, SOutputs: L, Dreg clr, Dreg ld, Dctr clr, Dctr ldB S0S1L 0Dreg clr 1(laser off)(clear Dreg)Dctr clr 1(clear count) Same FSM, usingconvention ofunassignedoutputs implicitlyassigned 0Digital Design 2eCopyright 2010Frank VahidS BS2S3L 1(laser on)L 0Dctr ld 1(laser off)(count up)SS4Dreg ld 1Dctr ld 0(load Dreg with Dctr/2)(stop counting)Some assignments to 0 still shown, due totheir importance in understandingdesired controller behavior26

5.4More RTL Design Additional datapath components(signed)ABsubSS A-B(signed)Digital Design 2eCopyright 2010Frank VahidABmulPAabsQP A*BQ A (unsigned) (unsigned)clrinc upcntQclk and clr 1: Q 0clk and inc 1: Q Q 1else Q stays sameW dW aclk and W e 1:W eRF[W a] W dRF R e 1:R aR eR d RF[R a]R d27

RTL Design Involving Register File or Memory HLSM array: Ordered list of items– Ex: Local storage: A[4](8-bit) – 4 8-bit items– Accessed using notation "A[i]", i is index– A[0] : 9; A[1] : 8; A[2] : 7; A[3] : 22 Array contents now: 9, 8, 7, 22 X : A[1] will set X to 8 Note: First element's index is 0 Array can be mapped to instantiated register file or memoryDigital Design 2eCopyright 2010Frank Vahid28

ArrayEx Inputs: (none)Outputs: P (11 bits)Local storage: A[4](11 bits)Preg (11 bits)Init1 Preg : 0A[0] : 9Simple Array Examplea(A[0] 8)'Init2 A[1] : 121211A[0] 8A sOut1 Preg : A[1](a)A Wa0A Wa1A WeA Ra0A Ra1A ReArrayEx Inputs: A eq 8Outputs: A s, A Wa0, .Init1Preg clr 1A s 0A Wa1 0, A Wa1 0A We 1Init2A eq 811I1 I0Amuxs0 QW dW aW eARF[4](11)R aR eR d8ABAcmplt eq gtA eq 8(A eq 8)'Preg clrA s 1A Wa1 0, A Wa0 1A We 1A Ra1 0, A Ra0 0A Re 19Preg ldDP(b)clr Ild PregQP11Out1 Preg ld 1Digital Design 2eCopyright 2010Frank VahidController(c)a29

RTL Example: Video Compression – Sum of AbsoluteOnly difference: ball movingDifferencesFrame 1Frame 2Frame 1Frame 2DigitizedDigitizedDigitizedDifference offrame 1frame 2frame 12 from 11 Mbyte1 Mbyte1 Mbyte0.01 Mbyte(a)(b ) Video is a series of frames (e.g., 30 per second) Most frames similar to previous frameaJust senddifference– Compression idea: just send difference from previous frameDigital Design 2eCopyright 2010Frank Vahid30

RTL Example: Video Compression – Sum of AbsoluteDifferencescompareFrame 1Frame 2Each is a pixel, assumerepresented as 1 byte(actually, a color picturemight have 3 bytes perpixel, for intensity ofred, green, and bluecomponents of pixel) Need to quickly determine whether two frames are similarenough to just send difference for second frame– Compare corresponding 16x16 “blocks” Treat 16x16 block as 256-byte array– Compute the absolute value of the difference of each array item– Sum those differences – if above a threshold, send complete framefor second frame; if below, can use difference method (usinganother technique, not described)Digital Design 2eCopyright 2010Frank Vahid31

Array Example: Video ](8)BRF[256](8)Inputs: A, B [256](8 bits); go (bit)Outputs: sad (32 bits)Local storage: sum, sadreg (32 bits); i (9 bits)sad!goS0gogoS1sum : 0i : 0a S0: wait for goS1: initialize sum and indexS2: check if done ( (i 256)’ )S3: add difference to sum,increment index S4: done, write to output sad regDigital Design 2eCopyright 2010Frank Vahid(i 256)’S2i 256sum: sum abs(A[i]-B[i])S3i : i 1S4sadreg : sum(b)32

Inputs: A, B [256](8 bits); go (bit)Outputs: sad (32 bits)Local storage: sum, sadreg (32 bits); i (9 bits)S0!gogoS1sum : 0i : 0Array Example: VideoCompression—Sum-ofAbsolute Differences!(i 256)S2i 256sum: sum abs(A[i]-B[i])S3i : i 1S4sadreg : sumgoS0go(i 256)’ (i lt 256)S1i lt 256go sum 0 sum clr 1i 0 i clr 1Acmp Bi clrsum ldi 256 i lt 256sum sum abs(A[i]-B[i])S3sum ld 1; AB rd 1i i 1 i inc 1sum clrsad reg sumsadreg ld 1256A data B data898aAiB–8S2S4lti incControllerDigital Design 2eCopyright 2010Frank VahidAB addrAB rdsum32abs832 32sadreg ldsadreg clrDatapathsadreg 32sad33

Circuit vs. Microprocessor Circuit: Two states (S2 & S3) for each i, 256 i’s 512 clock cycles Microprocessor: Loop (for i 1 to 256), but for each i, must movememory to local registers, subtract, compute absolute value, add tosum, increment i – say 6 cycles per array item 256*6 1536 cycles Circuit is about 3 times (300%) faster (assuming equal cycle lengths) Later, we’ll see how to build SAD circuit that is much faster(i 256)’S2i 256sum: sum abs(A[i]-B[i])S3i: i 1Digital Design 2eCopyright 2010Frank Vahid34

Common RTL Design Pitfall Involving Storage Updates QuestionsLocal storage: R, Q (8 bits)– Value of Q after state A?– Final state is C or D?R 100ABR: 99Q: RR: R 1 Answers– Q is NOT 99 after state A– Q is 99 in state B, so final state is C– Storage update actions in stateoccur simultaneously on next clockedge Thus, order actions are written isirrelevant A's actions same if:– Q: R R: 99– R: 99 Q: RDigital Design 2eCopyright 2010Frank VahidC(R 100)'DR 100AB99100R?99100Q?clkCaor35

Common RTL Design Pitfall Involving Storage Updates New HLSMusing extrastate so read ofR occurs afterwrite of RLocal storage : R, Q (8 bits)R 100ABR: 99Q: RR: R 1Q: RB2C(R 100)'DR 100 (R 100)'Digital Design 2eCopyright 2010Frank VahidclkABB2DR99?10099100100Q?999936

RTL Design Involving a Timer Commonly need explicit time intervalsL– Ex: Repeatedly blink LED on 1 second, off 1 second Pre-instantiate timer that HLSM can then useBlinkLedBlinkLedT MT ldT enloadenableOutputs: L (bit)32T Q'M32-bit1-microsecQ timer TT QLTimer: TT Q'T QT QInitOffOnL: '0'T: 1000000T en: '0'L: '0'T en: '1'L: '1'T en: '1'(a)(b)Pre-instantiated timerHLSM making use of timeraDigital Design 2eCopyright 2010Frank Vahida37

Button Debouncing Press button– Ideally, output changes to 1– Actually, output bouncesbuttonB Due to mechanical reasons Like ball bouncing when dropped tofloor01Ideal: B Digital circuit can convert actualsignal closer to ideal signalActual: BbounceInputs: Bin (bit) Outputs: Bout (bit)Timer: TButtonDebouncerBin'T Q'BinDigital Design 2eCopyright 2010Frank VahidBBinBin'T QInitWaitBinWait20Bout : '0'T: 20000T en: '0'Bout: '0'T en: '0'Bout: '1'T en: '1'WhileBinBout: '1'T en: '0'38a

Data Dominated RTL Design Example Data dominated design: Extensive DP,simple controller Control dominated design: Complexcontroller, simple DP Example: Filter– Converts digital input stream to newdigital output stream– Ex: Remove noiseYX12digital filter12clk 180, 180, 181, 180, 240, 180, 181 240 is probably noise, filter might replaceby 181– Simple filter: Output average of last Nvalues Small N: less filtering Large N: more filtering, but less sharpoutputDigital Design 2eCopyright 2010Frank Vahid39

Data Dominated RTL Design Example: FIR Filter FIR filter– “Finite Impulse Response”– Simply a configurable weightedsum of past input values– y(t) c0*x(t) c1*x(t-1) c2*x(t-2) Above known as “3 tap” Tens of taps more common Very general filter – User setsthe constants (c0, c1, c2) todefine specific filterYX1212clky(t) c0*x(t) c1*x(t-1) c2*x(t-2)Inputs: X (12 bits) Outputs: Y (12 bits)Local storage: xt0, xt1, xt2, c0, c1, c2 (12 bits);Yreg (12 bits)Init RTL design– Step 1: Create HLSM Very simple states/transitionsFIR filterDigital Design 2eCopyright 2010Frank Vahiddigital filterYreg : 0xt0 : 0xt1 : 0xt2 : 0c0 : 3c1 : 2c2 : 2FCYreg : c0*xt0 c1*xt1 c2*xt2xt0 : Xxt1 : xt0xt2 : xt1Assume constants set to 3, 2, and 240

FIRFilterInputs: X (12 bits) Outputs: Y (12 bits)Local storage: xt0, xt1, xt2, c0, c1, c2 (12 bits);Yreg (12 bits)InitFIR filterFCYreg : 0xt0 : 0xt1 : 0xt2 : 0c0 : 3c1 : 2c2 : 2Yreg : c0*xt0 c1*xt1 c2*xt2xt0 : Xxt1 : xt0xt2 : xt13xt0 clrc0xt0c2 ldc1xt1c2.X2c1 ld.xt0 ld– Set clr and ld lines appropriately2c0 ld Step 2A: Create datapath Step 2B: Connect Ctrlr/DP (asearlier examples) Step 2C: Derive FSMxt212clkx(t)*x(t-1) *x(t-2) *Yreg clrYreg ldYYregDatapath for 3-tap FIR filterDigital Design 2eCopyright 2010Frank Vahid1241

Circuit vs. Microprocessory(t) c0*x(t) c1*x(t-1) c2*x(t-2) Comparing the FIR circuit to microprocessor instructions– Microprocessor 100-tap filter: 100 multiplications, 100 additions. Say 2 instructionsper multiplication, 2 per addition. Say 10 ns per instruction. (100*2 100*2)*10 4000 ns– Circuit Assume adder has 2 ns delay, multiplier has 20 ns delay Longest path goes through one multiplier and two adders– 20 2 2 24 ns delay 100-tap filter, following design on previous slide, would have about a34 ns delay: 1 multiplier and 7 adders on longest path– Circuit is more than 100 times faster (4000/34). Wow.Digital Design 2eCopyright 2010Frank Vahid42

5.5Determining Clock Frequency Designers of digital circuitsoften want fastestperformanceclkab– Means want high clockfrequency Frequency limited by longestregister-to-register delay– Known as critical path– If clock is any faster, incorrectdata may be stored into register– Longest path on right is 2 ns2 nsdelay c Ignoring wire delays, andregister setup and hold times,for simplicityDigital Design 2eCopyright 2010Frank Vahid43

Critical Path Example shows four pathsDigital Design 2eCopyright 2010Frank Vahid *c5 nsdelay2 ns– 1 / 7 ns 142 MHzMax(2,7,7,5) 7 nsb7 ns Longest path is thus 7 ns Fastest frequency2 nsdelaya7 nsa to c through : 2 nsa to d through and *: 7 nsb to d through and *: 7 nsb to d through *: 5 ns2 ns––––da44

Critical Path Considering Wire Delays Real wires have delay too– Must include in critical path Example shows two pathsclkab– Each is 0.5 2 0.5 3 ns Wire delays may even be greater thanlogic delays!0.5 ns 2 nsa0.5 nsc3 ns– 1980s/1990s: Wire delays were tinycompared to logic delays– But wire delays not shrinking as fast aslogic delays0.5 ns3 ns Trend Must also consider register setup andhold times, also add to path Then add some time to the computedpath, just to be safe– e.g., if path is 3 ns, say 4 ns insteadDigital Design 2eCopyright 2010Frank Vahid45

A Circuit May Have Numerous Paths Paths can exist– In the datapath– In the controller– Between thecontroller anddatapath– May behundreds orthousands ofpaths Timing analysistools that evaluateall possible pathsautomatically veryhelpfulDigital Design 2eCopyright 2010Frank VahidsCombinational logica88dtot ldldtott ot clrcclr8(c )tot lt sn18-bit n08-bitadder8tot lt saDatapaths1clks0(b )(a)State register46

Behavioral Level Design: C to GatesInputs : A, B [256](8 bits); go (bit)Outputs : sad (32 bits)Local storage : sum, sadreg (32 bits); i (9 bits)S0goS1!gosum : 0i : 0(i 256)’S2i 256S3 sum: sum abs(A[i]-B[i])i : i 1S4sadreg : suma5.6C codeint SAD (byte A[256], byte B[256]) // not quite C syntax{uint sum; short uint I;sum 0;i 0;while (i 256) {sum sum abs(A[i] – B[i]);i i 1;}return sum;} Earlier sum-of-absolute-differences example– Started with high-level state machine– C code is an even better starting point -- easier to understandDigital Design 2eCopyright 2010Frank Vahid47

Converting from C to High-Level State Machine Convert each C construct toequivalent states andtransitions Assignment statement– Becomes one state withassignmenttarget : expressiontarget expression;a If-then statement– Becomes state with conditioncheck, transitioning to “then”statements if condition true,otherwise to ending state “then” statements would alsobe converted to statesDigital Design 2eCopyright 2010Frank Vahidcond’if (cond) {// then stmts}conda(then stmts)(end)48

Converting from C to High-Level State Machine If-then-else– Becomes state with conditioncheck, transitioning to “then”statements if condition true, orto “else” statements if conditionfalsecond’if (cond) {// then stmts}else {// else stmts}cond(then stmts) (else stmts)a(end) While loop statement– Becomes state with conditioncheck, transitioning to whileloop’s statements if true, thentransitioning back to conditioncheckDigital Design 2eCopyright 2010Frank Vahidcond’while (cond) {// while stmts}cond(while stmts)a(end)49

Simple Example of Converting from C to HighLevel State MachineInputs: uint X, YOutputs: uint Max(X Y)’(X Y)’X YX Yif (X Y) {Max X;(then stmts)(else stmts)Max: XMax: Y}else {Max Y;(end)(end)}aa(a)(b)(c) Simple example: Computing the maximum of two numbers– Convert if-then-else statement to states (b)– Then convert assignment statements to states (c)Digital Design 2eCopyright 2010Frank Vahid50

Example: SAD Ccode to HLSM Convert each constructto statesInputs: byte A[256],B[256]bit go;Output: int sadmain(){uint sum; short uint i;while (1) {– Actually, subset of C(not all C constructseasily convertible)– Can use languageother than Cgo'go'}go'gosum: 0i: 0i 0sum 0;i 0;}gosum: 0while (!go);– Simplify, e.g., mergestates RTL design process toconvert to circuit Can thus convert C tocircuit usingstraightforward process(go')'(c)(b)while (i 256) {sum sum abs(A[i] – B[i]);i i 1;}sad sum;go'(d)gogo'go(a)sum: 0i: 0go'sum: 0i: 0go(i 256)'sum: 0i: 0i 256(i 256)'sum: sum abs.i : i 1i 256while stmts(i 256)'i 256sum: sum abs.i : i 1sadreg : sum(g)Digital Design 2eCopyright 2010Frank Vahidasadreg : sum(e)(f)51

5.7Memory Components– Some components are usedoutside the controller and DP MxN memoryM words RTL design instantiatesdatapath components tocreate datapath, controlledby a controller– M words, N bits wide each Several varieties of memory,which we now introduceN-bitswide eachM N memoryDigital Design 2eCopyright 2010Frank Vahid52

Random Access Memory (RAM) RAM – Readable and writable memory– “Random access memory” Strange name—Created several decades ago tocontrast with sequentially-accessed storage liketape drives– Logically same as register file—Memory withaddress inputs, data inputs/outputs, and control32432W dataR dataW addrR addrW en16 32register file4R enRegister file from Chpt. 4 RAM usually one port; RF usually two or more– RAM vs. RF RAM typically larger than about 512 or 1024 words RAM typically stores bits using a bit storageapproach that is more efficient than a flip-flop RAM typically implemented on a chip in a squarerather than rectangular shape—keeps longestwires (hence delay) short32data10addrrw1024 32RAMenRAM block symbolDigital Design 2eCopyright 2010Frank Vahid53

RAM Internal Structure3210wdata(N-1) wdata(N-2) wdata0Let A log2Mdataaddrrw1024x32RAMd0ena0a1 AxMd1decodera(A-1)addr0addr1addr(A-1)clkenrww orddata cellword wordenable enablerw datad(M-1)to all cellswdata0wdata(N-1)rdata(N-1)ebit storageblock(aka “cell”)rdata0Combining rd and wrdata lineswordenabledata0 Similar internal structure as register filerdata(N-1) rdata(N-2) rdata0RAM cellrwdata(N-1)Digital Design 2eCopyright 2010Frank Vahid––––Decoder enables appropriate word based on address inputsrw controls whether cell is written or readrd and wr data lines typically combined54Let’s see what’s inside each RAM cell

Static RAM (SRAM)3210SRAM rdenableSRAM celldata’0data1 “Static” RAM cell– 6 transistors (recall inverter is 2 transistors)– Writing this cell word enable input comes from decoder When 0, value d loops around inverters– That loop is where a bit stays storedda101wordenable When 1, the data bit value enters the loop– data is the bit to be stored in this cell– data’ enters on other side– Example shows a “1” being written into cellDigital Design 2eCopyright 2010Frank Vahiddata1wordenableddata’celld’a0055

Static RAM (SRAM)3210dataaddrrw1024x32RAMen “Static” RAM cellSRAM cell Somewhat trickier When rw set to read, the RAM logic setsboth data and data’ to 1 The stored bit d will pull either the left line orthe right bit down slightly below 1 “Sense amplifiers” detect which side isslightly pulled downdata’1data1– Reading this celld10awordenable11 1To sense amplifiers– The electrical description of SRAM is reallybeyond our scope – just general idea here,mainly to contrast with DRAM.Digital Design 2eCopyright 2010Frank Vahid56

Dynamic RAM (DRAM)3210dataadd

Frank Vahid 1 Digital Design Chapter 5: Register-Transfer Level (RTL) Design Regiszter-Transzfer Szintű Tervezés Slides to accompany the textbook Digital Design, with RTL Design, VHDL, and Verilog, 2nd Edition, by Frank