VHDL Operator Operation - Gatech.edu

Table 6.1 VHDL Operators.VHDL OperatorOperation odulus*REMRemainder*&Concatenation – used to combine bitsSLL**logical shift leftSRL**logical shift rightSLA**arithmetic shift leftSRA**arithmetic shift rightROL**rotate leftROR**rotate right equality/ Inequality less than less that or equal greater than greater than or equalNOTlogical NOTANDlogical ANDORlogical ORNANDlogical NANDNORlogical NORXORlogical XORXNOR*logical XNOR*Not supported in many VHDL synthesis tools. In the Quartus II tools, onlymultiply and divide by powers of two (shifts) are supported. Mod and Remare not supported in Quartus II. Efficient design of multiply or dividehardware typically requires the user to specify the arithmetic algorithm anddesign in VHDL.** Supported only in 1076-1993 VHDL.

Table 6.2 STD LOGIC conversion functions.FunctionExample:CONV STD LOGIC VECTOR( integer, bits )Converts an integer to a standard logicvector. Useful to enter constants.CONV SIGNED and CONV UNSIGNEDwork in a similar way to produce signedand unsigned values.CONV STD LOGIC VECTOR( 7, 4 )Produces a standard logic vector of"0111".CONV INTEGER( std logic vector )Converts a standard logic vector to aninteger. Useful for array indexing whenusing a std logic vector signal for the arrayindex.CONV INTEGER( "0111" )Produces an integer value of 7.

ABCAXBCD(1)D(1)D(2)D(2)Y

LIBRARY IEEE;-- Include Libraries for standard logic data typesUSE IEEE.STD LOGIC 1164.ALL;-- Entity name normally the same as file nameENTITY gate network IS-- Ports: Declares module inputs and outputsPORT( A, B, C: IN STD LOGIC;-- Standard Logic Vector ( Array of 4 Bits )D : IN STD LOGIC VECTOR( 3 DOWNTO 0 );-- Output SignalsX, Y: OUT STD LOGIC );END gate network;-- Defines internal module architectureARCHITECTURE behavior OF gate network ISBEGIN-- Concurrent assignment statements operate in parallel-- D(1) selects bit 1 of standard logic vector DX A AND NOT( B OR C ) AND ( D( 1 ) XOR D( 2 ) );-- Process must declare a sensitivity list,-- In this case it is ( A, B, C, D )-- List includes all signals that can change the outputsPROCESS ( A, B, C, D )BEGIN-- Statements inside process execute sequentiallyY A AND NOT( B OR C) AND ( D( 1) XOR D( 2 ) );END PROCESS;END behavior;

LED MSD DISPLAY:-- BCD to 7 Segment Decoder for LED DisplaysPROCESS (MSD)-- Case statement implements a logic truth tableBEGINCASE MSD ISWHEN "0000" MSD 7SEG "1111110";WHEN "0001" MSD 7SEG "0110000";WHEN "0010" MSD 7SEG "1101101";aWHEN "0011" MSD 7SEG "1111001";fbWHEN "0100" gMSD 7SEG "0110011";WHEN "0101" ecMSD 7SEG "1011011";WHEN "0110" dpMSD 7SEG "1011111";dWHEN "0111" MSD 7SEG "1110000";WHEN "1000" MSD 7SEG "1111111";WHEN "1001" MSD 7SEG "1111011";WHEN OTHERS MSD 7SEG "0111110";END CASE;END PROCESS LED MSD DISPLAY;

LIBRARY IEEE;USE IEEE.STD LOGIC 1164.ALL;-- Input Signals and Mux ControlENTITY multiplexer IS: INPORT( A, B, Mux ControlSTD LOGIC;Mux ControlMux Out1, Mux Out2,Mux Out3, Mux Out4 : OUT STD LOGIC );A0END multiplexer;ARCHITECTURE behavior OF multiplexer ISBEGINB1Mux Outx-- selected signal assignment statement Mux Out1 A WHEN Mux Control '0' ELSE B;-- with Select StatementWITH mux control SELECTMux Out2 A WHEN '0',B WHEN '1',A WHEN OTHERS;PROCESS ( A, B, Mux Contro l)BEGINIF Mux Control '0' THENMux Out3 A;ELSEMux out3 B;END IF;-- OTHERS case required since STD LOGIC-has values other than "0" or "1"-- Statements inside a process-execute sequentially.CASE Mux Control ISWHEN '0' Mux Out4 A;WHEN '1' Mux Out4 B;WHEN OTHERS Mux Out4 A;END CASE;END PROCESS;END behavior;

ControlLIBRARY IEEE;USE IEEE.STD LOGIC 1164.ALL;ENTITY tristate ISPORT(A, Control : INTri out: INOUTATri OutSTD LOGIC;STD LOGIC); -- Use Inout for bi-directional tri-state-signals or out for output onlyEND tristate;ARCHITECTURE behavior OF tristate ISBEGINTri out A WHEN Control '0' ELSE 'Z';END behavior;-- defines internal module architecture-- Assignment of 'Z' value generates-- tri-state output

LIBRARY IEEE;USE IEEE.STD LOGIC 1164.ALL;ENTITY DFFs ISPORT( D, Clock, Reset, EnableQ1, Q2, Q3, Q4END DFFs;: INSTD LOGIC;: OUT STD LOGIC );ARCHITECTURE behavior OF DFFs ISBEGIN-- Positive edge triggered D flip-flopPROCESS-- If WAIT is used no sensitivity list is usedBEGINWAIT UNTIL ( Clock 'EVENT AND Clock '1' );Q1 D;DD QEND PROCESS;ClockQ1

-- Positive edge triggered D flip-flopPROCESS-with synchronous resetBEGINWAIT UNTIL ( Clock 'EVENT AND Clock '1' );IF reset '1' THENQ2 '0';ResetELSED0Q2 D;01END IF;END PROCESS;DQQ2Clock-- Positive edge triggered D flip-flopPROCESS (Reset,Clock)-with asynchronous resetBEGINreset '1'IFTHENQ3 '0';ELSIF ( clock 'EVENT AND clock '1' ) THENDQ3 D;END IF;END PROCESS;ResetDQQ3ClockPROCESS (Reset,Clock)BEGIN-- Positive edge triggered D flip-flop-with asynchronous reset and-enableIF reset '1' THENQ4 '0';ELSIF ( clock 'EVENT AND clock '1' ) THENIF Enable '1' THENQ4 D;END IF;END IF;END PROCESS;END behavior;ResetEnableQ40D1DQClockQ4

LIBRARY IEEE;USE IEEE.STD LOGIC 1164.ALL;ENTITY ilatch ISPORT( A, BOutput1, Output2END ilatch;: IN: OUTSTD LOGIC;STD LOGIC );ARCHITECTURE behavior OF ilatch ISBEGINPROCESS ( A, B )BEGIND QIF A '0' THENOutput2Output1 '0';Output2 '0';ELSEClockIF B '1' THENOutput1 '1';Output2 '1';-- Latch inferred since no value is assignedELSEOutput1 '0';-- to output2 in the else clause!END IF;END IF;END PROCESS;END behavior;

LIBRARY IEEE;USE IEEE.STD LOGIC 1164.ALL;USE IEEE.STD LOGIC ARITH.ALL;USE IEEE.STD LOGIC UNSIGNED.ALL;ENTITY Counter ISPORT( Clock, ResetMax countCountEND Counter;: IN STD LOGIC;: IN STD LOGIC VECTOR( 7 DOWNTO 0 );: OUT STD LOGIC VECTOR( 7 DOWNTO 0 ) );-- Declare signal(s) internal to moduleARCHITECTURE behavior OF Counter ISSIGNAL internal count :STD LOGIC VECTOR( 7 DOWNTO 0 );BEGINcount internal count;PROCESS ( Reset,Clock )-- Reset counterBEGINIF reset '1' THENinternal count "00000000";ELSIF ( clock 'EVENT AND clock '1' ) THEN-- Check for maximum countIF internal count Max count THENinternal count internal count 1; -- Increment Counter-- Count Max CountELSE-reset Counterinternal count "00000000";END IF;END IF;END PROCESS;END behavior;

ResetA1X0XX1BOutput 1CX0Figure 6.1 State Diagram for st mach example

LIBRARY IEEE;USE IEEE.STD LOGIC 1164.ALL;ENTITY st mach ISPORT( clk, resetInput1, Input2Output1END st mach;: IN: IN: OUTSTD LOGIC;STD LOGIC;STD LOGIC);ARCHITECTURE A OF st mach IS-- Enumerated Data Type for StateTYPE STATE TYPE IS ( state A, state B, state C );SIGNAL state: STATE TYPE;BEGINPROCESS ( reset, clk )BEGIN-- Reset StateIF reset '1' THENstate state A;ELSIF clk 'EVENT AND clk '1' THEN

CASE state IS-- Define Next State Transitions using a Case-Statement based on the Current StateWHEN state A IF Input1 '0' THENstate state B;ELSEstate state C;END IF;WHEN state B state state C;WHEN state C IF Input2 '1' THENstate state A;END IF;WHEN OTHERS state state A;END CASE;END IF;END PROCESS;-- Define State Machine OutputsWITH state SELECTOutput1 '0' WHEN state A,'1' WHEN state B,'0' WHEN state C;END a;

LIBRARY IEEE;USE IEEE.STD LOGIC 1164.ALL;USE IEEE.STD LOGIC ARITH.ALL;USE IEEE.STD LOGIC UNSIGNED.ALL;ENTITY ALU ISPORT( Op codeA input, B inputALU outputEND ALU;: INSTD LOGIC VECTOR( 2 DOWNTO 0 );: INSTD LOGIC VECTOR( 7 DOWNTO 0 );: OUT STD LOGIC VECTOR( 7 DOWNTO 0 ) );ARCHITECTURE behavior OF ALU ISSIGNAL temp outputBEGIN:PROCESS ( Op code, A input, B input )BEGIN-- Declare signal(s) internal to module hereSTD LOGIC VECTOR( 7 DOWNTO 0 );

-- Select Arithmetic/Logical OperationCASE Op Code ( 2 DOWNTO 1 ) ISWHEN "00" A inputB inputtemp output A input B input;88WHEN "01" temp output A input B input;WHEN "10" temp output A input AND B input;Op codeALU(2 downto 1)WHEN "11" , -, AND, ORtemp output A input OR B input;WHEN OTHERS Temp outputtemp output "00000000";ShiftOp code (0)END CASE;8-- Select Shift Operation: Shift bits left with zero fill using concatenation operatorALU output-- Can also use VHDL 1076-1993 shift operator such as SLLIF Op Code( 0 ) '1' THENAlu output temp output( 6 DOWNTO 0 ) & '0';ELSEAlu output temp output;END IF;END PROCESS;END behavior;

LIBRARY IEEE;USE IEEE.STD LOGIC 1164.ALL;USE IEEE.STD LOGIC ARITH.ALL;USE IEEE.STD LOGIC UNSIGNED.ALL;LIBRARY lpm;USE lpm.lpm components.ALL;ENTITY mult ISPORT( A, BProductEND mult;: IN STD LOGIC VECTOR( 7 DOWNTO 0 );: OUT STD LOGIC VECTOR( 15 DOWNTO 0 ) );ARCHITECTURE a OF mult IS-- LPM 8x8 multiply function P A * BBEGINmultiply: lpm mult 8,GENERIC MAP( LPM WIDTHALPM WIDTHB 8,LPM WIDTHS 16,LPM WIDTHP 16,LPM REPRESENTATION "UNSIGNED" )PORT MAP (END a;data A,datab B,result Product );

LIBRARY IEEE;USE IEEE.STD LOGIC 1164.ALL;ENTITY memory ISPORT( read dataread addresswrite datawrite addressMemwriteClockEND memory;::::::OUTINININININSTD LOGIC VECTOR( 7 DOWNTO 0 );STD LOGIC VECTOR( 2 DOWNTO 0 );STD LOGIC VECTOR( 7 DOWNTO 0 );STD LOGIC VECTOR( 2 DOWNTO 0 );STD LOGIC;STD LOGIC );ARCHITECTURE behavior OF memory IS-- define new data type for memory arrayTYPE memory type IS ARRAY ( 0 TO 7 ) OF STD LOGIC VECTOR( 7 DOWNTO 0 );: memory type;SIGNAL memoryBEGIN-- Read Memory and convert array index to an integer with CONV INTEGERread data memory( CONV INTEGER( read address( 2 DOWNTO 0 ) ) );-- Write Memory?PROCESSBEGINWAIT UNTIL clock 'EVENT AND clock '1';IF ( memwrite '1' ) THEN-- convert array index to an integer with CONV INTEGERmemory( CONV INTEGER( write address( 2 DOWNTO 0 ) ) ) write data;END IF;END PROCESS;END behavior;

LIBRARY IEEE;USE IEEE.STD LOGIC 1164.ALL;ENTITY memory ISPORT( read dataread addresswrite datawrite addressMemwriteclock,resetEND memory;::::::OUTINININININSTD LOGIC VECTOR( 7 DOWNTO 0 );STD LOGIC VECTOR( 2 DOWNTO 0 );STD LOGIC VECTOR( 7 DOWNTO 0 );STD LOGIC VECTOR( 2 DOWNTO 0 );STD LOGIC;STD LOGIC );ARCHITECTURE behavior OF memory ISSIGNAL mem0, mem1 :STD LOGIC VECTOR( 7 DOWNTO 0 );BEGINPROCESS (read address, mem0, mem1) -- Process for memory read operationBEGINCASE read address ISWHEN "000" read data mem0;WHEN "001" read data mem1;WHEN OTHERS -- Unimplemented memory locationsread data X"FF";END CASE;END PROCESS;

PROCESSBEGINWAIT UNTIL clock 'EVENT AND clock '1';IF ( reset '1' ) THENmem0 X"55" ; -- Initial values for memory (optional)mem1 X"AA" ;ELSEIF memwrite '1' THEN-- Write to memory?CASE write address IS-- Use a flip-flop withWHEN "000" -an enable for memorymem0 write data;WHEN "001" mem1 write data;WHEN OTHERS -- unimplemented memory locationsNULL;END CASE;END IF;END IF;END PROCESS;END behavior;

LIBRARY IEEE;USE IEEE.STD LOGIC 1164.ALL;LIBRARY Altera mf;USE altera mf.altera mf components.all;ENTITY amemory ISPORT( read data:OUT STD LOGIC VECTOR( 7 DOWNTO 0 );memory address : IN STD LOGIC VECTOR( 2 DOWNTO 0 );write data: INSTD LOGIC VECTOR( 7 DOWNTO 0 );Memwrite: INSTD LOGIC;clock,reset: INSTD LOGIC );END amemory;ARCHITECTURE behavior OF amemory ISBEGINdata memory: altsyncram-- Altsyncram memory functionGENERIC MAP ( operation mode “SINGLE PORT”,width a 8,widthad a 3,lpm type “altsyncram”,outdata reg a "UNREGISTERED",-- Reads in mif file for initial data values (optional)init file "memory.mif",intended device family “Cyclone”)PORT MAP (wren a Memwrite, clock0 clock,address a memory address( 2 DOWNTO 0 ),data a write data, q a read data );END behavior;

onepulsedebouncePB1PB1 DebouncedPB1 Single PulsePB debouncedpb debouncedpbPB single pulseclockclock 100HzClock 1Mhzinst1inst2Clock 100Hzclk divClock 48Mhzclock 48Mhzclock 1MHzclock 100KHzclock 10KHzclock 1KHzclock 100Hzclock 10Hzclock 1HzinstFigure 6.2 Schematic of Hierarchical Design