Circuit Design With VHDL
Circuit Design with VHDLVolnei A. PedroniMIT PressCambridge, MassachusettsLondon, England
ContentsPrefaceICIRCUIT DESIGN1Introduction1.1 About VHDL1.2 Design Flow1.3 EDA Tools1.4 Translation of VHDL Code into a Circuit1.5 Design Examples2Code Structure2.1 Fundamental VHDL Units2.2 LIBRARY Declarations2.3 ENTITY2.4 ARCHITECTURE2.5 Introductory Examples2.6 Problems3Data Types3.1 Pre-Defined Data Types3.2 User-Defined Data Types3.3 Subtypes3.4 Arrays3.5 Port Array3.6 Records3.7 Signed and Unsigned Data Types3.8 Data Conversion3.9 Summary3.10 Additional Examples3.1 1 Problems4Operators and Attributes4.1 Operators4.2 Attributes4.3 User-Defined Attributes4.4 Operator Overloading
ent Code5.1 Concurrent versus Sequential5.2 Using Operators5.3 WHEN (Simple and Selected)5.4 GENERATE5.5 BLOCK5.6 Problems6Sequential Code6.1 PROCESS6.2 Signals and Variables6.3 I F6.4 WAIT6.5 CASE6.6 LOOP6.7 CASE versus I F6.8 CASE versus WHEN6.9 Bad Clocking6.10 Using Sequential Code to Design Combinational Circuits6.1 1 Problems7Signals and Variables7.1 CONSTANT7.2 SIGNAL7.3 VARIABLE7.4 SIGNAL versus VARIABLE7.5 Number of Registers7.6 Problems8State Machines8.1 Introduction8.2 Design Style #I8.3 Design Style #2 (Stored Output)
-'!!Contents8.48.5Encoding Style: From Binary to OneHotProblems9Additional Circuit Designs9.1 Barrel Shifter9.2 Signed and Unsigned Comparators9.3 Carry Ripple and Carry Look Ahead Adders9.4 Fixed-Point Division9.5 Vending-Machine Controller9.6 Serial Data Receiver9.7 Parallel-to-Serial Converter9.8 Playing with a Seven-Segment Display9.9 Signal Generators9.10 Memory Design9.1 1 Problems11SYSTEM DESIGN10 Packages and Components10.1 Introduction10.2 PACKAGE10.3 COMPONENT10.4 PORT MAP10.5 GENERIC MAP10.6 Problems11 Functions and Procedures11.1 FUNCTION11.2 Function Location11.3 PROCEDURE11.4 Procedure Location11.5 FUNCTION versus PROCEDURE Summary11.6 ASSERT11.7 Problems12 Additional System Designs12.1 Serial-Parallel Multiplier12.2 Parallel Multiplier
Contents12.312.412.512.6Multiply-Accumulate CircuitsDigital FiltersNeural NetworksProblemsAppendix A: Programmable Logic DevicesAppendix B: Xilinx ISE ModelSim TutorialAppendix C: Altera MaxPlus I1 Advanced Synthesis SoftwareTutorialAppendix D: Altera Quartus 11TutorialAppendix E: VHDL Reserved WordsBibliographyIndex
Index Addition operator, 49, 54, 60, 195 Assi-ment operator for OTHERS, 47, 60 Assignment operator for SIGNAL, 47, 60Assignment operator for VARIABLE,CONSTANT, or GENERIC, 47, 60/ Division operator, 49, 60 Equal-to operator, 49, 60** Exponentiation operator, 49, 60 Greater-than operator, 49, 60 Greater-than-or-equal-to operator, 49, 60 Less-,than operator, 49, 60 Less-than-or-equal-to operator, 49, 60* Multiplication operator, 49, 60/ Not-equal-to operator, 49, 60- Subtraction operator, 49, 60: ABS operator, 49, 60Absolute value operator, 49, 60Accumulate (multiply-and-), 285-288, 290, 292,295,299Actel FPGAs, 315ACTIVE attribute, 52, 61Adder circuits, 5-7, 42-43, 106-109, 194-198Basic adder, 42-43Carry-look-ahead adder, 196-198Carry-ripple adder, 106-109,194-196Full-adder, 5-7, 279, 282-283MAC (multiply-and-accumulate),285-288, 290,292,295,299Overflow, 286Addition operator, 49, 54, 60, 195Advanced Synthesis Software, 329, 336-338AFTER clause, 28AlteraAdvanced Synthesis Software, 329, 336-338CPLDs, 312MaxPlus I1 software, 5,20, 329-342Quartus I1 software, 4-5,20,343-353ALU, 75-78, 247-251AND operator, 36-37,41-42,48, 60Antifuse, 306, 313, 315Application Specific Integrated Circuit. See ASICARCHITECTUREDescription, 17Introductory examples, 6, 17-22Usage, 13-14Arithmetic logic unit. See ALUArithmetic operators, 48-49, 60ARRAY, 30-33,39Array indexes, 51ASIC, 3,4, 6, 211,293ASSERT statement, 270-271Assi,ment operators, 47-48, 60ATTRIBUTE statement, 52-53Attributes, 50-53, 61Data attributes, 51, 61Signal attributes, 52, 61Summary, 61User-defined attributes, 52-53Barrellvector shifter circuits, 80-81, 109-1 11,187-190Base type, 29-30BEGIN keywordwith ARCHITECTURE, 17with BLOCK, 81-83with FUNCTION, 253with PROCEDURE, 265with PROCESS, 91Behavioral description, 91Binary versus one-hot and two-hot encoding,181-182Binary-to-Gray-code converter, 87BIT. See Data typesBIT-VECTOR. See Data typesBIT versus BIT-VECTOR, 41-42BLOCK statementGuarded, 83-84Simple, 81-83BODY. See PACKAGE BODYBOOLEAN. See Data typesBuffer circuit, 73BUFFER mode, 16, 37-138, 140, 143, 145, 152,154, 157Carry-look-ahead adder circuit. See Adder circuitsCarry-ripple adder circuits. See Adder circuitsCASE statement, 91, 100-104CASE versus IF, 112-1 13CASE versus WHEN, 113-114Combinational versus sequential circuits, 65-66Comparator circuits, 191-194Comparison operators, 49, 60Complex programmable logic devices. See CPLDsCOMPONENT, 234,236-244Concatenation operators, 50, 60Concurrent code, 65-84Concurrent statementsBLOCK, 65,81-84GENERATE, 65, 78-81, 195, 197-198WHEN, 65,69-78WHEN versus CASE, 113-1 14Concurrent versus sequential code, 65-67CONFIGURATION statement, 72CONSTANT, 31, 47, 129-131, 174-176, 220-221,234-235, 270Controller circuit for tra%c light, 174-178, 186Controller circuit for vending machine, 202-208,226-227Conv-integer function, 25, 37, 43, 255, 258-259
IndexConv-signed function, 25, 37Conv std logic vectorfunction, 25, 38Conv-unsigned function, 25,37Conversion functions. See Data conversionfunctionsCount ones circuits, 130-133Counter circuits, 94-96, 99-100, 102-104, 144146, 155, 164-166,272CPLDS, 3-4, 305-306,311-313,317,338-340Data attributes, 51, 61Data conversion functions, 25, 37-38Data objects. See ObjectsData types, 25-43ARRAY, 30-33,39BIT, 16-17,21-22,25-26,39,48-49,54-55BIT-VECTOR, 25-26,28-30,39,48-49,5455BIT versus BIT-VECTOR, 41-42BOOLEAN, 25, 27-28,30, 39,204,235-237,254-257Enumerated data types, 28-29, 39, 51, 53, 61, 70,101, 160, 162, 164,204INTEGER, 25,27-28, 30,35,37-39,48-49NATURAL, 27,29-30,34-35,262,300Physical data types, 27Port array, 33-34REAL, 25,27, 39RECORD, 35,39SIGNED, 25,27, 30, 35-39,42-43,48, 191,285,291,297STD LOGIC, 25-27.39STD LOGIC VECT'OR,25-27,39STD-ULOGIC, 25-27, 39STD-ULOGIC-VECTOR, 26,39SUBTYPE, 29-30, 39,80,226UNSIGNED, 25,27, 30, 35-39,48, 191,263265User-defined, 28-29, 34, 39,299Decoder circuits, 55-57, 62-63, 156Delay circuit, 152DFF, 18-22,83-84,92-93,99, 101-102, 125-127,137-138, 142-143, 152-155, 157-158,254-255Digital filter circuit, 289-294, 303Divider circuit, fixed-point, 198-202Division operator, 49, 60Don't care, 26D-type fip-flop. See D F FEDIF, 329, 336, 337EEPROM, 306, 309, 312-313ELSEwith WHEN, 69with IF, 94ELSIF, 94Encoder circuit, 73-75END keywordwith ARCHITECTURE, 17with BLOCK, 81-83with CASE, 100with FUNCTION, 253with GENERATE, 78-79with IF, 94with LOOP, 105with PROCEDURE, 265with PROCESS, 91ENTITYDescription, 15-17Introductory examples, 6, 17-22Usage, 13-14Enum-encoding attribute, 53Enumerated data types. See Data typesEPROM, 308-309Equal-to operator, 49, 60Error message. See ASSERT statementEVENT attribute, 52, 61Event counter circuit, 121Exclusive-NOR operator, 48, 60Exclusive-OR operator, 48, 60EXIT statement, 105-106, 111-112Exponentiation operator, 49, 60Field r o r a m m a bGatel e Arrays. See FPGAsFinite State Machine. See FSMFIR filter. See Digital filter circuitFlip-flop. See D F FFOR statementwith GENERATE, 78-81with LOOP, 105-1 12with WAIT, 98-99FPGAs, 34,305-306,311-315,317,338-339Frequency divider circuit, 122, 138-140FSM, 159-182,202-208,213-218Full-adder. See Adder circuitsFUNCTION, 253-265.Arithmetic shift function, 261-262Convert-to-integer function, 37,43,255,258-259Delinition and syntax, 253-254Function location, 256-258Multiplication function, 263-265Multiplier function, 263-265Overloaded " " operator function, 260-261Positive-edge function, 254-258FUNCTION versus PROCEDURE, 270GAL devices, 305-306, 309-312GENERATE statement, 65, 78-81, 195, 197-198GENERIC MAP, 244-247
IndexGENERIC statement, 54-60, 97, 108-109, 117,191-195,201, 221,223, 225Gray code, 87Greater-than operator, 49, 60Greater-than-or-equal-to operator, 49, 60GUARDED BLOCK, 83-84Hexadecimal, 28,43HIGH attribute, 51, 61High-impedance, 26, 73IEEE library, 13-15,25-27,35-38IEEE standards for VHDL, 25IF statement, 91, 94-97IF versus CASE, 112-1 13IF-GENERATE, 78-79IN mode, 16-17Inferred registers, number of, 140-151INOUT mode, 16,225INTEGER. See Data typesIntensity encoder circuit, 124IS keywordwith ARCHITECTURE, 17with ATTRIBUTE, 53with CASE, 100with COMPONENT, 237with ENTITY, 16with FUNCTION, 253with PACKAGE, 234with PACKAGE BODY, 234with PROCEDURE, 265with SUBTYPE, 29-30with TYPE, 28-29ISE software, 4-5, 20, 317-327Keypad debouncerlencodercircuit, 184-1 86LAST-ACTIVE attribute, 52LAST-EVENT attribute, 52LAST-VALUE attribute, 52Latch, 83-84, 119, 121 (see also DFF)Leading zeros counter circuit, 111-1 12LEFT attribute, 51, 61LEFTOF attribute, 51, 61LENGTH attribute, 51, 61Less-than operator, 49, 60Less-than-or-equal-to operator, 49, 60LibraryDeclaration, 13-15IEEE library, 13, 15,25-27,35-38Introductory examples, 18-22Standard library, 13, 15, 25Std-logic-1164 package, 13, 15,25-27Std-ulogic-1164 package, 25-27Std-logic-arith package, 15,25,27, 35-38,4243, 191,263,285,287,291, 296,299Std-logic-signed package, 15,25, 27, 36, 38,48Std-logic-unsigned package, 15,25,27, 36, 38,48Work library, 13, 15Logic systemsBinary (std library), 25STDLOGIC, 25-27STD-ULOGIC, 25-27Logical operators, 48, 60LOOP statement, 91, 105-1 12LOW attribute, 51, 61MAC circuits, 285-288, 290, 292, 295, 299MAPGENERIC MAP, 244-247PORT MAP, 237,241,244-245, 251,277-279,281-284MaxPlus I1 software, 5, 20, 329-342Min-max procedure, 267-270MOD operator, 49, 60ModeBUFFER, 16, 137-138, 140, 143, 145, 152, 154,157IN, 16-22INOUT, 16, 225,266OUT, 16-22ModelSim software, 5, 20, 317, 325-326Modulus operator, 49, 60Multiplexer circuits, 68, 70-72, 85, 134-137Multiplication operator, 49, 60Multiplier circuits, 263-265, 275-285Multiply-and-accumulate circuit. See MACcircuitsMultivalued logic systemsSTD-LOGIC, 25-27STD-ULOGIC, 25-27MUX. See Multiplexer circuitsNAND operator, 48, 60NATURAL. See Data typesNeural networks, 294-301, 303NEXT statement, 105-106NOR operator, 48, 60NOT operator, 48, 60Not-equal-to operator, 49, 60NULL statement, 101-102, 104, 113-1 14Number of registers inferred, 140-151Numeric data types. See Data typesObjectsCONSTANT, 31,47, 129-131, 174-176,220221,234-235,270
IndexObjects (cont.)SIGNAL, 19, 21-22, 129-132SIGNAL versus VARIABLE, 133-140VARIABLE, 129-133ON keyword, 98-99One-hot encoding, 181-182Operator overloading, 53-54, 260-261OperatorsArithmetic, 48-49, 60Assi-ment, 47-48, 60Comparison, 49,60Concatenation, 50, 60Logical, 48, 60Shift, 49-50, 60Summary, 60OR operator, 48, 60OTHERS clause, 40,47-48, 69-73, 94, 101-102,112-114OUT mode, 16-22Overloading, 53-54,260-261PACKAGEDescription, 13-14,93,133,233-236,256,266-270Examples, 75-284,287,299PACKAGE BODY, 234-236,256-260,269-270,287PAL devices, 305-308, 339PALCE devices, 305Parity detector circuit, 57-59, 123Parity generator circuit, 59-60Physical data types, 27PLA devices, 305-306, 308-309, 312Playing with a seven-se-ment display, 212-216,228PLDsCPLD, 3-4,305-306,311-313,317,338-340FPGA, 34,305-306,311-315, 317, 338-339GAL, 305-306, 309-312PAL, 305-308, 339PLA, 305-306, 308-309, 312PORTIntroductory examples, 5-6, 18-22Modes. See ModePort array, 33-35PORT MAP, 237,241,244,251,277-279,281-284Pre-defined data attributes, 51, 61Pre-defined data types, 25-28, 39Pre-defined operators, 47-50, 60Pre-defined signal attributes, 52, 61Priority encoder circuit, 85, 121-122PROCEDURE, 13-14,91,94, 105, 113, 130-133,233-235,265-270PROCEDURE versus FUNCTION, 270PROCESSDescription, 91-94Introductory examples, 18-22, 56-60, 92-120Programmable array logic. See PALProgrammable logic array. See PLAProgrammable logic devices. See PLDsQuartus I1 software, 4-5,20,343-353QUIET attribute, 52RAM circuits, 116-1 18, 221-225Random access memory. See RAM circuitsRANGE attribute, 28-30, 34-35, 37, 51, 61Read-only memory. See ROM circuitsREAL. See Data typesRECORD, 35,39Registers. See DFFRegisters inferred, number of, 140-151Relational operators. See OperatorsREM operator, 49, 60Remainder operator, 49, 60'REPORT statement, 271Reserved words, 355ResoIved data type, 26-27, 39REVERSE-RANGE attribute, 51, 61RIGHT attribute, 51, 61, 262ROL operator, 50, 60ROM circuits, 44, 220-221ROR operator, 50, 60Rotate left logic operator, 50, 60Rotate right logic operator, 50, 60RTL, 4SELECT statement, 67, 69-73, 113Sequential code, 65,91-121Sequential statementsCASE, 91, 100-104, 112-1 14IF, 91, 94-97, 112-113LOOP, 91, 105-112WAIT, 91, 97-100Serial data receiver circuit, 208-21 1, 227Seven-segment display, 212-216, 228Shift left arithmetic operator, 50, 60Shift left logic operator, 49-50, 60Shift operators, 49-50, 60Shift register circuits, 96-97, 121, 146-151Shift right arithmetic operator, 50, 60Shift right logic operator, 49-50, 60SIGNAL, 19,21-22, 129-132Simal attributes. 52. 61signal generatorciriuits, 178-181, 183-184, 186,217-220SIGNAL versus VARIABLE. 133-140SIGNED. See Data types
r1IndexSLA operator, 50, 60SLL operator, 49-50, 60Speed monitor circuit, 228-229SRA operator, 50, 60SRL operator, 49-50, 60STD-LOGIC, 25-27, 39STD-LOGIC-VECTOR, 25-27,39STD-ULOGIC, 25-27,39STD-ULOGIC-VECTOR, 26-27, 39Stop-watch circuit, 252String detector circuit, 172-174Subtype, 29-30, 39Timer circuits, 123Traffic light controller circuit, 174-178, 186Tri-state buffer circuit, 73Two-hot encoding, 181-182Types. See Data typesUNAFFECTED statement, 69-70, 101, 113-1 14Unresolved data type, 27, 39UNSIGNED. sei b a t a typesUNTIL, 52,98-100USE clause, 13, 15User-dehed attributes, 52-53User-dehed data types, 28-29, 34, 39, 299VARIABLE, 129-133VARIABLE versus SIGNAL, 133-140Vending machine controller circuit, 202-208,226-227VHDL acronym, 3VHDL reserved words, 355WAIT statement, 91, 97-100WHEN statement, 65, 69-78WHEN versus CASE, 113-1 14WHILE statement, 105-106WITH, 67,69-73, 113Work library, 13, 15XilinxCPLDs, 312FPGAs, 314ISE software, 4-5, 20, 317-327XNOR operator, 48, 60XOR operator, 48, 60" Z logic state, 26-27, 39, 73
I CIRCUIT DESIGN 1 Introduction 1.1 About VHDL 1.2 Design Flow 1.3 EDA Tools 1.4 Translation of VHDL Code into a Circuit 1.5 Design Examples 2 Code Structure 2.1 Fundamental VHDL Units 2.2 LIBRARY Declarations 2.3 ENTITY 2.4 ARCHITECTURE 2.5 Introductory Examples 2.6 Problems 3 Data Types 3.1 Pre-Defined Data Types
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circuit path that leads from a gate output back to an input of the same gate). Every VHDL assignment corresponds to a combinational circuit, and any combinational circuit can be implemented using one or more VHDL assignments. The specific circuit shown above is only one possible implementation of the given signal assignment. Any logically .
VHDL is a description language for digital electronic circuits that is used in di erent levels of abstraction. The VHDL acronym stands for VHSIC (Very High Spdee Integrated Circuits) Hardware Description Language . This means that VHDL can be used to accelerate the design process.
exposed to VHDL modeling of digital circuits, they learn the concepts and non-VHDL design of the digital circuits. Additionally, they spend two hours (or more) per week in the lab to go over the lab assignments and do the lab assignments in which VHDL and FPGAs are used from week 3 through week 10.
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ANSI A300 Purpose: To provide performance standards for developing written specifications for tree management. Currently nine individual parts . ANSI Z60 American Nurseryman and Landscape Association began developing this standard back in 1929 Became an ANSI document in 1949 Current version is 2004 . ANSI A300 The Tree Care Industry Association convened a consensus body .
