LOW PHASE NOISE T1/E1 CLOCK GENERATOR MK1581-01
DATASHEETMK1581-01LOW PHASE NOISE T1/E1 CLOCK GENERATORDescriptionFeaturesThe MK1581-01 provides synchronization and timingcontrol for T1 and E1 based network access or multitrunktelecommunication systems. The device accepts an 8 kHzframe clock input and uses an on-chip VCXO to produce asynchronized low phase noise clock output. Generates a T1 (1.544 MHz) or E1 (2.048 MHz) outputThis monolithic IC, combined with an external inexpensivequartz crystal, can be used to replace a more costly hybridVCXO retiming module. Through selection of external loopfilter components values, the device can be tailored to meetthe system’s clock jitter attenuation requirements. Low-passjitter attenuation characteristics in the Hz range arepossible. clock from an 8kHz frame clock inputConfigurable jitter attenuation characteristics, excellentfor use as a Stratum source de-jitter circuitVCXO-based clock generation ensures very low jitter andphase noise generationOutput clock is phase and frequency locked to the inputreference clock 115ppm minimum crystal frequency pullability range,using recommended crystalIndustrial temperature rangeLow power CMOS technology16 pin TSSOP packageSingle 3.3 V power supplyNOTE: EOL for non-green parts to occur on 5/13/10per PDN U-09-01Block DiagramRSETISETPullable Hz INCLKChargePumpFeedbackDividerSELCHGPRSCSIDT LOW PHASE NOISE T1/E1 CLOCK GENERATORVINGND5CP1MK1581-01REV E 121809
MK1581-01LOW PHASE NOISE T1/E1 CLOCK GENERATORVCXO AND SYNTHESIZERPin AssignmentOutput Clock Selection TableVDD116X1VDD215X2VDD3148kHz putClockSELOutputClock(MHz)CrystalUsed (MHz)8 kHz01.54424.7048 kHz12.04824.57616 pin 4.40 mil body, 0.65 mm pitch TSSOPPin DescriptionsPinNumberPinNamePinType1VDDPowerPower Supply. Connect to 3.3 V.2VDDPowerPower Supply. Connect to 3.3 V.3VDDPowerPower Supply. Connect to 3.3 V.4VINInputVCXO Control Voltage Input. Connect this pin to CHGP pin and the external loopfilter as shown in this data sheet.5GNDPowerConnect to ground.6GNDPowerConnect to ground.7GNDPowerConnect to ground.8CHGPOutputCharge Pump Output. Connect this pin to the external loop filter and to pin VIN.9ISET–10GNDPowerConnect to ground.11GNDPowerConnect to ground.12CLKOutputClock Output.13SELInputOutput Frequency Selection. Determines output frequency as per table above.Internal pull-up.148kHz INInput8 kHz reference clock input.15X2–Crystal Output. Connect this pin to the specified crystal.16X1–Crystal Input. Connect this pin to the specified crystal.Pin DescriptionCharge pump current setting node, connection for setting resistor.IDT LOW PHASE NOISE T1/E1 CLOCK GENERATOR2MK1581-01REV E 121809
MK1581-01LOW PHASE NOISE T1/E1 CLOCK GENERATORVCXO AND SYNTHESIZERFunctional DescriptionThe frequency of oscillation of a quartz crystal is determinedby its cut and by the external load capacitance. TheMK1581-01 incorporates variable load capacitors on-chipwhich “pull”, or change, the frequency of the crystal. Thecrystals specified for use with the MK1581-01 are designedto have zero frequency error when the total of on-chip stray capacitance is 14 pF. To achieve this, the layout shoulduse short traces between the MK1581-01 and the crystal.The MK1581-01 is a clock generator IC that generates a T1or E1 reference clock directly from an internal VCXO circuitthat works in conjunction with an external quartz crystal.The VCXO output frequency and phase is controlled by aninternal PLL (Phase Locked Loop) circuit, enabling thedevice to perform clock regeneration from an 8 kHz inputreference clock.A complete description of the recommended crystalparameters is in application note MAN05.Most typical PLL clock devices use an internal VCO (VoltageControlled Oscillator) for output clock generation. By usinga VCXO with an external crystal, the MK1581-01 is able togenerate a low jitter, low phase-noise output clock. The lowbandwidth capability of the PLL circuit serves to provideinput clock jitter attenuation and enables stable operationwith the low frequency input reference clock.A list of approved crystals is located on the IDT web site(www.idt.com).PLL Loop Filter ComponentsA phased-locked loop (PLL) is a control system that keepsthe VCO frequency and phase locked with the inputreference clock. Like all control systems, analog PLL circuitsuse a loop filter to establish operating stability. TheMK1581-01 uses external loop filter components for thefollowing reasons:The internal VCXO circuit requires an external pullablecrystal for operation. External loop filter components enablea PLL configuration with low loop bandwidth.1) Larger loop filter capacitor values can be used, allowinga lower loop bandwidth. This enables the use of lower inputclock reference frequencies and also input clock jitterattenuation capabilities. Larger loop filter capacitors alsoallow higher loop damping factors when less passbandpeaking is desired.Application InformationOutput Frequency ConfigurationThe MK1581-01 is configured to generate either a 1.544MHz T1 clock or a 2.048 MHz E1 clock from an 8 kHz inputclock. Please refer to the Output Clock Selection Table onPage 2. Input bit SEL is set according to this table, as is theexternal crystal frequency. Please refer to the QuartzCrystal section on this page regarding external crystalrequirements.2) The loop filter values can be user selected to optimizeloop response characteristics for a given application.Referencing the External Component Schematic on thispage, the external loop filter is made up of components RS,CS and CP. RSET establishes PLL charge pump current andtherefore influences loop filter characteristics.Quartz CrystalIt is important that the correct type of quartz crystal is usedwith the MK1581-01. Failure to do so may result in reducedfrequency pullability range, inability of the loop to lock, orexcessive output phase jitter.Design aid tools for configuring the loop filter can be foundat www.idt.com, including on-line and PC-based calculators.The MK1581-01 operates by phase-locking the VCXOcircuit to the input signal of the selected ICLK input. TheVCXO consists of the external crystal and the integratedVCXO oscillator circuit. To achieve the best performanceand reliability, a crystal device with the recommendedparameters (shown below) must be used, and the layoutguidelines discussed in the PCB Layout Recommendationssection must be followed.IDT LOW PHASE NOISE T1/E1 CLOCK GENERATOR3MK1581-01REV E 121809
MK1581-01LOW PHASE NOISE T1/E1 CLOCK GENERATORVCXO AND SYNTHESIZERExternal Component SchematicRefer to Crystal Tuning sectionCLVDDVDDVDDVINGNDRS GNDGNDCS CHGPCPCLPullableCrystal12345678X1X28kHz INSELCLKGNDGNDISET161514131211109RSETRecommended Loop Filter Values Vs. Output Frequency SelectionCrystalSEL Output Freq Multiplier(N)RSETRSCSCPLoopBandwidth(-3dB point)DampingFactor01.544 MHz3088120 kΩ1.0 MΩ0.1 µF4.7 nF18 Hz1.412.048 MHz3072120 kΩ1.0 MΩ0.1 µF4.7 nF19 Hz1.4IDT LOW PHASE NOISE T1/E1 CLOCK GENERATOR4MK1581-01REV E 121809
MK1581-01LOW PHASE NOISE T1/E1 CLOCK GENERATORVCXO AND SYNTHESIZERA “normalized” PLL loop bandwidth may be calculated asfollows:Charge Pump Current TableR S I CP 575NBW ----------------------------------------NRSET1.4 MΩ680 kΩ540 kΩ120 kΩThe “normalized” bandwidth (NBW) equation above doesnot take into account the effects of damping factor or thesecond pole. NBW is approximately equal to the actual -3dBbandwidth of the loop when the damping factor is about 5and C2 is very small. In most applications, NBW is about75% of the actual -3dB bandwidth. However, NBW doesprovide a useful approximation of filter performance.Charge Pump Current(ICP)10 µA20 µA25 µA100 µASpecial considerations must be made in choosing loopcomponents CS and CP.These recommendations can be found in the design aidtools section of www.icst.com.The loop damping factor is calculated as follows:Series Termination ResistorDamping Factor R S 625 I CP C S------------------------------------------NClock output traces over one inch should use seriestermination. To series terminate a 50Ω trace (a commonlyused trace impedance), place a 33Ω resistor in series withthe clock line, as close to the clock output pin as possible.The nominal impedance of the clock output is 20Ω. (Theoptional series termination resistor is not shown in theExternal Component Schematic.)Where:RS Value of resistor in loop filter (Ohms)ICP Charge pump current (amps)(refer to Charge Pump Current Table, below)N Crystal multiplier shown in the above tableCS Value of capacitor CS in loop filter (Farads)Decoupling CapacitorsAs with any high performance mixed-signal IC, theMK1581-01 must be isolated from system power supplynoise to perform optimally.Decoupling capacitors of 0.01µF must be connectedbetween each VDD and the PCB ground plane. To furtherguard against interfering system supply noise, theMK1581-01 should use one common connection to the PCBpower plane as shown in the diagram on the next page. Theferrite bead and bulk capacitor help reduce lower frequencynoise in the supply that can lead to output clock phasemodulation.As a general rule, the following relationship should bemaintained between components CS and CP in the loopfilter:CCP -----S20IDT LOW PHASE NOISE T1/E1 CLOCK GENERATOR5MK1581-01REV E 121809
MK1581-01LOW PHASE NOISE T1/E1 CLOCK GENERATORVCXO AND SYNTHESIZERRecommended Power Supply Connection forOptimal Device Performancefrom the device is less critical.2) The loop filter components must also be placed close tothe CHGP and VIN pins. CP should be closest to the device.Coupling of noise from other system signal traces should beminimized by keeping traces short and away from activesignal traces. Use of vias should be avoided.V D D P inC onnection to 3.3VP ow er P laneFerriteBeadB ulk D ecoupling C apacitor(such as 1 F Tantalum )0.01V D D P in3) The external crystal should be mounted just next to thedevice with short traces. The X1 and X2 traces should notbe routed next to each other with minimum spaces, insteadthey should be separated and away from other traces.V D D P inF D ecoupling C apacitors4) To minimize EMI the 33Ω series termination resistor, ifneeded, should be placed close to the clock output.5) An optimum layout is one with all components on thesame side of the board, minimizing vias through other signallayers (the ferrite bead and bulk decoupling capacitor can bemounted on the back). Other signal traces should be routedaway from the MK1581-01. This includes signal traces justunderneath the device, or on layers adjacent to the groundplane layer used by the device.Crystal Load CapacitorsThe device crystal connections should include pads forsmall capacitors from X1 to ground and from X2 to ground,shown as CL in the External Component Schematic. Thesecapacitors are used to adjust the stray capacitance of theboard to match the nominally required crystal loadcapacitance. Because load capacitance can only beincreased in this trimming process, it is important to keepstray capacitance to a minimum by using very short PCBtraces (and no vias) been the crystal and device.The IDT Applications Note MAN05 may also be referencedfor additional suggestions on layout of the crystal section.In most cases the load capacitors will not be required. Theyshould not be stuffed on the prototype evaluation board asthe indiscriminate use of these trim capacitors will typicallycause more crystal centering error than their absence. If theneed for the load capacitors is later determined, the valueswill fall within the 1-4 pF range. The need for, and value of,these trim capacitors can only be determined at prototypeevaluation. Refer to MAN05 for the centering capacitorselection procedure.PCB Layout RecommendationsFor optimum device performance and lowest output phasenoise, the following guidelines should be observed. Pleasealso refer to the Recommended PCB Layout drawing onPage 7.1) Each 0.01µF decoupling capacitor should be mounted onthe component side of the board as close to the VDD pin aspossible. No via’s should be used between decouplingcapacitor and VDD pin. The PCB trace to VDD pin shouldbe kept as short as possible, as should the PCB trace to theground via. Distance of the ferrite bead and bulk decouplingIDT LOW PHASE NOISE T1/E1 CLOCK GENERATOR6MK1581-01REV E 121809
MK1581-01LOW PHASE NOISE T1/E1 CLOCK GENERATORVCXO AND SYNTHESIZERRecommended PCB LayoutFor m inim um output clock jitter,device V D D connections shouldbe m ade to com m on bulkdecoupling device (see text).For m inim um output clock jitter,rem ove ground and pow er planew ithin this entire area. A lso routeall other traces aw ay from this area.GGG1162153144G513G612G78G11G10G9Legend:GG G roundC onnectionAbsolute Maximum RatingsStresses above the ratings listed below can cause permanent damage to the MK1581-01. These ratings, which arestandard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at theseor any other conditions above those indicated in the operational sections of the specifications is not implied.Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electricalparameters are guaranteed only over the recommended operating temperature range.ItemRatingSupply Voltage, VDD7VAll Inputs and Outputs-0.5 V to VDD 0.5 VAmbient Operating Temperature-40 to 85 CStorage Temperature-65 to 150 CJunction Temperature125 CSoldering Temperature260 CIDT LOW PHASE NOISE T1/E1 CLOCK GENERATOR7MK1581-01REV E 121809
MK1581-01LOW PHASE NOISE T1/E1 CLOCK GENERATORVCXO AND SYNTHESIZERRecommended Operation ConditionsParameterMin.Ambient Operating TemperatureTyp.Max.Units 85 C 3.45V-40Power Supply Voltage (measured in respect to GND) 3.15 3.3DC Electrical CharacteristicsUnless stated otherwise, VDD 3.3 V 5%, Ambient Temperature -40 to 85 CParameterSymbolOperating VoltageVDDSupply CurrentIDDInput High Voltage, AClock outputs unloaded,VDD 3.3 V2VInput Low Voltage, SELVILInput High Voltage, 8kHz INVIHInput Low Voltage, 8kHz INVILInput High CurrentIIHVIH VDDInput Low CurrentIILVIL 0Input Capacitance, except X1CINOutput High Voltage (CMOS Level)VOHIOH -4 mAVDD-0.4VOutput High VoltageVOHIOH -8 mA2.4VOutput Low VoltageVOLIOL 8 mAShort Circuit CurrentIOSVIN, VCXO Control VoltageVXCNominal Output ImpedanceZOUT0.8VVVDD/2 1VDD/2-1V-10 10µA-10 10µA7pF0.4V 500mAVDDVΩ20AC Electrical CharacteristicsUnless stated otherwise, VDD 3.3V 5%, Ambient Temperature -40 to 85 CParameterSymbolVCXO Crystal Pull RangefXPVCXO Crystal NominalFrequencyfXInput Jitter TolerancetjiInput pulse width (1)tpiOutput Frequency ErrorOutput Duty Cycle (% hightime)IDT LOW PHASE NOISE T1/E1 CLOCK GENERATORConditionsUsing RecommendedCrystalMin.Typ.Max.Units-115 115ppm24.70424.576MHz0.4UIIn reference to inputclock period10FOUTICLK 0 ppm error0tODMeasured at VDD/2,CL 15 pF408ns00ppm60%MK1581-01REV E 121809
MK1581-01LOW PHASE NOISE T1/E1 CLOCK GENERATORParameterVCXO AND SYNTHESIZERSymbolConditionsMin.Typ.Max.UnitsOutput Rise TimetOR0.8 to 2.0V, CL 15 pF1.5nsOutput Fall TimetOF2.0 to 0.8V, CL 15 pF1.5nsSkew, Input to Output ClocktIONote 2Cycle Jitter (short term jitter)tjaPeak to Peak150ps p-pNote 1: Minimum high or low time of input clock.Note 2: The input to output clock skew is not controlled nor predictable and will change between power up cycles.Because it is dependent on the phase relationship between the output and feedback divider states following powerup, the input to output clock skew will remain stable during a given power up cycle. If controlled input to output skewis desired for this output clock frequency please refer to the MK2049 or MK2069 products.Thermal CharacteristicsParameterThermal Resistance Junction toAmbientThermal Resistance Junction to CaseIDT LOW PHASE NOISE T1/E1 CLOCK GENERATORSymbolConditionsMin.Typ.Max. UnitsθJAStill air78 C/WθJA1 m/s air flow70 C/WθJA3 m/s air flow68 C/W37 C/WθJC9MK1581-01REV E 121809
MK1581-01LOW PHASE NOISE T1/E1 CLOCK GENERATORVCXO AND SYNTHESIZERPackage Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)Package dimensions are kept current with JEDEC Publication No. 95, MO-153Millimeters16SymbolE1AA1A2bCDEE1eLαaaaEIN D EXAR 090.204.905.16.40 BASIC4.304.500.65 Basic0.450.750 8 035 0.0080.1930.2010.252 BASIC0.1690.1770.0256 Basic0.0180.0300 8 -0.004AA1c-C ebS E A TIN GP LA N ELaaa COrdering InformationPart / Order NumberMarkingShipping Tubes16-pin TSSOP-40 to 85 CMK1581-01GITR*MK1581-01GITape and Reel16-pin TSSOP-40 to 85 CMK1581-01GILF15810GILTubes16-pin TSSOP-40 to 85 CMK1581-01GILFTR15810GILTape and Reel16-pin TSSOP-40 to 85 C*NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumesno responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. Noother circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applicationssuch as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are notrecommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDTdoes not authorize or warrant any IDT product for use in life support devices or critical medical instruments.IDT LOW PHASE NOISE T1/E1 CLOCK GENERATOR10MK1581-01REV E 121809
MK1581-01LOW PHASE NOISE T1/E1 CLOCK GENERATORVCXO AND SYNTHESIZERInnovate with IDT and accelerate your future networks. Contact:www.IDT.comFor SalesFor Tech Support800-345-7015408-284-8200Fax: 408-284-2775www.idt.com/go/clockhelpCorporate HeadquartersIntegrated Device Technology, Inc.www.idt.com 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated DeviceTechnology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registeredtrademarks used to identify products or services of their respective owners.Printed in USA
LOW PHASE NOISE T1/E1 CLOCK GENERATOR VCXO AND SYNTHESIZER IDT LOW PHASE NOISE T1/E1 CLOCK GENERATOR 3 MK1581-01 REV E 121809 Functional Description The MK1581-01 is a clock generator IC that generates a T1 or E1 reference clock directly from an internal VCXO circuit t
to the problem we have observed in the ADS phase noise simulation where the pnmx phase noise goes flat below some small offset frequency.) The plot to the right shows the phase noise for πf 2 c π 10 -3 osc. Note if we were to extrapolate from the phase noise at 100 kHz, we would get a phase noise of 30 dBc/Hz at an offset frequency of 1 Hz.
Note: * The phase detector PLL loop filter calculator and phase noise estimator spreadsheet can be downloaded at www.psemi.com. Figure 3. Simulated Phase Noise Performance of the PE97420 at 100 MHz -180-170-160-150-140-130-120-110-100 0.1 1 10 100 1000 10000 Phase Noise (dBc/Hz) Frequency Offset (kHz) PE97240 PLL Phase Noise at VCO Output
01.03 Rohde & Schwarz Mastering Phase Noise Measurements (Part 3) 3 2 Introduction Phase noise is unintentional phase modulation on a signal that spreads the spectrum and degrades performance in many RF applications. Whether you are new to phase noise or have been measuring phase noise for years it is important to get a good
Noise Figure Overview of Noise Measurement Methods 4 White Paper Noise Measurements The noise contribution from circuit elements is usually defined in terms of noise figure, noise factor or noise temperature. These are terms that quantify the amount of noise that a circuit element adds to a signal.
Jan 26, 2018 · Adjusting the delay line or the phase shifter will determine the phase quadrature of the two inputs to the mixer (phase detector). Then, the phase detector converts phase fluctuations to voltage fluctuations, which can then be read on the baseband spectrum analyzer as frequency noise. The frequency noise is then converted for phase noise
phase noise separator are derived. A function scheme and a circuit structure for three-phase noise separators are proposed based on the theory developed. The technique to design a high-performance three-phase noise separator is explored. A three-phase noise sepa-rator pro
The Noise Element of a General Plan is a tool for including noise control in the planning process in order to maintain compatible land use with environmental noise levels. This Noise Element identifies noise sensitive land uses and noise sources, and defines areas of noise impact for the purpose of
7 LNA Metrics: Noise Figure Noise factor is defined by the ratio of output SNR and input SNR. Noise figure is the dB form of noise factor. Noise figure shows the degradation of signal's SNR due to the circuits that the signal passes. Noise factor of cascaded system: LNA's noise factor directly appears in the total noise factor of the system.
