I.MX 8M Nano Hardware Developer’s Guide
NXP SemiconductorsUser's GuideDocument identifier: IMX8MNHDGRev. 1, 11/2020i.MX 8M Nano Hardware Developer’s Guide
NXP SemiconductorsContentsChapter 1 Overview. 41.1 Device supported.41.2 Essential references. 41.3 Supplementary references. 41.4 Related documentation.51.5 Conventions.51.6 Acronyms and abbreviations. 5Chapter 2 i.MX 8M Nano design checklist. 82.1 Design checklist table.82.2 JTAG signal termination. 172.3 Signal termination for Boundary-scan. 17Chapter 3 i.MX 8M Nano layout/routing recommendations. 183.1 Introduction.183.2 Basic design recommendations.183.3 Stack-up and manufacturing recommendations. 183.4 DDR design recommendations.213.5 Trace impedance recommendations. 533.6 Power connectivity/routing.543.7 USB connectivity. 573.8 Unused input/output terminations.57Chapter 4 Avoiding board bring-up problems. 594.1 Introduction.594.2 Avoiding power pitfalls -Current.594.3 Avoiding power pitfalls -Voltage. 594.4 Checking for clock pitfalls. 614.5 Avoiding reset pitfalls.614.6 Sample board bring-up checklist. 61Chapter 5 Using BSDL for Board-level Testing. 645.1 BSDL overview. 645.2 How BSDL functions.645.3 Downloading the BSDL file.645.4 Pin coverage of BSDL. 645.5 Boundary scan operation.645.6 DDR4 connectivity test in Boundary-Scan.675.7 I/O pin power considerations. 68Chapter 6 Thermal Considerations. 696.1 Introduction.696.2 PCB Dimensions. 696.3 Copper Volume.696.4 Thermal Resistance.706.5 Power Net Design.70i.MX 8M Nano Hardware Developer’s Guide, Rev. 1, 11/2020User's Guide2 / 74
NXP SemiconductorsContents6.6 Component Placement. 706.7 PCB Surroundings.716.8 Thermal Simulations.716.9 Software optimization. 716.10 The Thermal Checklist.72Chapter 7 Revision history.73i.MX 8M Nano Hardware Developer’s Guide, Rev. 1, 11/2020User's Guide3 / 74
NXP SemiconductorsChapter 1OverviewThis document aims to help hardware engineers design and test the i.MX 8M Nano series processors. It provides examples onboard layout and design checklists to ensure first-pass success, and solutions to avoid board bring-up problems.Engineers should understand board layouts and board hardware terminology.This guide is released with relevant device-specific hardware documentation, such as datasheets, reference manuals, andapplication notes. All these documents are available on i.MX 8M NANO.1.1 Device supportedThis document supports the i.MX 8M Nano (14 14 mm package).1.2 Essential referencesThis guide is supplementary to the i.MX 8M Nano series chip reference manuals and data sheets. For reflow profile and thermallimits during soldering, see General Soldering Temperature Process Guidelines (document AN3300). These documents areavailable on i.MX 8M NANO.1.3 Supplementary references1.3.1 General informationThe following documents introduce the Arm processor architecture and computer architecture. For information about the Arm Cortex-A53 processor, see Cortex-A53 For information about the Arm Cortex-M4F processor, see Cortex-M7 Computer Architecture: A Quantitative Approach (Fourth Edition), by John L. Hennessy and David A. Patterson Computer Organization and Design: The Hardware/Software Interface (Second Edition), by David A. Patterson and JohnL. HennessyThe following documentation introduces the high-speed board design: Right the First Time- A Practical Handbook on High Speed PCB and System Design - Volumes I & II, by Lee W. Ritchey(Speeding Edge) - ISBN 0-9741936- 0-72 Signal and Power Integrity Simplified (2nd Edition), by Eric Bogatin (Prentice Hall)- ISBN 0-13- 703502-0 High Speed Digital Design- A Handbook of Black Magic, by Howard W. Johnson & Martin Graham (Prentice Hall) - ISBN0-13-395724-1 High Speed Signal Propagation- Advanced Black Magic, by Howard W. Johnson & Martin Graham - (Prentice Hall) - ISBN0-13-084408-X High Speed Digital System Design- A handbook of Interconnect Theory and Practice, by Hall, Hall and McCall (WileyInterscience 2000) - ISBN 0-36090-2 Signal Integrity Issues and Printed Circuit Design, by Doug Brooks (Prentice Hall) ISBN 0-13- 141884-X PCB Design for Real-World EMI Control, by Bruce R. Archambeault (Kluwer Academic Publishers Group) - ISBN1-4020-7130-2 Digital Design for Interference Specifications - A Practical Handbook for EMI Suppression, by David L. Terrell & R.Kenneth Keenan (Newnes Publishing) - ISBN 0-7506-7282-X Electromagnetic Compatibility Engineering, by Henry Ott (1st Edition - John Wiley and Sons) - ISBN 0-471-85068-3i.MX 8M Nano Hardware Developer’s Guide, Rev. 1, 11/2020User's Guide4 / 74
NXP SemiconductorsOverview Introduction to Electromagnetic Compatibility, by Clayton R. Paul (John Wiley and Sons) - ISBN 978-0-470-18930-6 Grounding & Shielding Techniques, by Ralph Morrison (5th Edition - John Wiley & Sons) - ISBN 0- 471-24518-6 EMC for Product Engineers, by Tim Williams (Newnes Publishing) - ISBN 0-7506- 2466-31.4 Related documentationAdditional literature will be published when new NXP products become available.For the list of current documents, see i.MX 8M NANO.1.5 ConventionsTable 1 lists the notational conventions used in this document.Table 1. Conventions used in the documentConventionsDescriptionCourierUsed to indicate commands, command parameters, code examples, and file and directory names.ItalicsUsed to indicates command or function parameters.BoldFunction names are written in bold.cleared/setWhen a bit takes the value zero, it means to be cleared; when it takes a value of one, it means to be set.mnemonicsInstruction mnemonics are shown in lowercase bold. Book titles in text are set in italics.sig nameInternal signals are written in all lowercase.nnnn nnnnhDenotes hexadecimal number0bDenotes binary numberrA, rBInstruction syntax used to identify a source GPRrDInstruction syntax used to identify a destination GPRREG[FIELD]Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges appear in brackets. Forexample, MSR[LE] refers to the little-endian mode enable bit in the machine state register.xAn italicized x indicates an alphanumeric variable.n, mAn italicized n indicates a numeric variable.In this guide, notation for all logical, bit-wise, arithmetic, comparison, and assignment operations follow C Language conventions.1.6 Acronyms and abbreviationsTable 2 defines the acronyms and abbreviations used in this document.i.MX 8M Nano Hardware Developer’s Guide, Rev. 1, 11/2020User's Guide5 / 74
NXP SemiconductorsOverviewTable 2. Definitions and acronymsAcronymDefinitionARMTMAdvanced RISC Machines processor architectureBGABall Grid Array packageBOMBill of MaterialsBSDLBoundary Scan Description LanguageCANFlexible Controller Area Network peripheralCCMClock Controller ModuleCSIMIPI Camera Serial InterfaceDDRDual Data Rate DRAMDDR3LLow voltage DDR3 DRAMDDR4DDR4 DRAMDDRCDDR ControllerDFPDownstream Facing Port (USB Type-C)DRPDual Role Port (USB Type-C)ECSPIEnhanced Configurable SPI peripheralEIMExternal Interface ModuleENET10/100/1000 Mbps Ethernet MAC peripheralEPITEnhanced Periodic Interrupt Timer peripheralESREquivalent Series ResistanceGNDGroundGPCGeneral Power ControllerGPIOGeneral Purpose Input/OutputHDCPHigh-bandwidth Digital Content ProtectionI2CInter-integrated Circuit interfaceIBISInput output Buffer Information SpecificationIOMUXi.MX 8M Nano chip-level I/O multiplexingTable continues on the next page.i.MX 8M Nano Hardware Developer’s Guide, Rev. 1, 11/2020User's Guide6 / 74
NXP SemiconductorsOverviewTable 2. Definitions and acronyms (continued)AcronymDefinitionJTAGJoint Test Action GroupKPPKeypad Port PeripheralLDBLVDS Display BridgeLDOLow Drop-Out regulatorLPCGLow Power Clock GatingLPDDR4Low Power DDR4 DRAMLVDSLow-Voltage Differential SignalingMLBMedia Local BusODTOn-Die TerminationOTPOne-Time ProgrammablePCBPrinted Circuit BoardPCIePCI ExpressPCISigPeripheral Component Interconnect Special Interest GroupPDNPower Distribution NetworkPMICPower Management Integrated CircuitPORPower-On ResetPTHPlated Through Hole PCB (i.e. no microvias)RGMIIReduced Gigabit Media Independent Interface (Ethernet)RMIIReduced Media Independent Interface (Ethernet)ROMRead-Only Memoryi.MX 8M Nano Hardware Developer’s Guide, Rev. 1, 11/2020User's Guide7 / 74
NXP SemiconductorsChapter 2i.MX 8M Nano design checklistThis document provides a design checklist for the i.MX 8M Nano (14 x 14 mm package) processor. The design checklist tablesrecommend optimal design and provide explanations to help users understand better. All supplemental tables referenced by thechecklist appear in sections following the design checklist tables.2.1 Design checklist tableTable 3. LPDDR4 recommandations (i.MX 8M Nano)Check boxRecommendations1. Connect the DRAM ZN ball on the processor (ballP2) to a 240 Ω, 1% resistor to GND.Explanation/Supplemental recommendationsThis is a reference used during DRAM outputbuffer driver calibration.2. The ZQ0 and ZQ1 balls on the LPDDR4 deviceshould be connected through 240Ω, 1% resistors to the LPDDR4 VDD2 rail.3. Place a 10 kΩ, 5% resistor to ground on the DRAMreset signal.This will ensure adherence to the JEDECspecification until the control is configured andstarts driving the DDR.LPDDR4 ODT on the i.MX 8M Nano is4. The ODT CA balls on the LPDDR4 device should becommand-based, making processor ODT CAconnected directly to the LPDDR4 VDD2 rail.output balls unnecessary.5. The architecture for each chip inside the DRAMpackage must be x 16.The processor does not support byte modespecified in JESD209-4B.6. The processor ball MTEST (ball N2), should be leftunconnected.These are observability ports for manufacturingand are not used otherwise.7. The VREF pin on the processor (ball P1) can be leftunconnected.The VREF signal for LPDDR4 is generatedinternally by the processor.8. It is strongly suggested to use LPDDR4 if lowerpower consumption is required since DLL-off mode isnot supported.The LPDDR4 can operate at low frequencywithout DLL-off mode.9. VDD DRAM should be always on during DDRretention mode. Otherwise the data in DRAM might belost when exiting this mode.See Errata e50381 for detailed information.Table 4. DDR4/DDR3L recommendations (i.MX 8M Nano)Check boxRecommendations1. Connect the ZQ(DRAM ZN) ball on the processor(ball P2) to individual 240 Ω, 1% resistors to GND.Explanation/Supplemental recommendationsThis is a reference used during DRAM outputbuffer driver calibration.Table continues on the next page.i.MX 8M Nano Hardware Developer’s Guide, Rev. 1, 11/2020User's Guide8 / 74
NXP Semiconductorsi.MX 8M Nano design checklistTable 4. DDR4/DDR3L recommendations (i.MX 8M Nano) (continued)Check boxRecommendations2. The ZQ ball on each DDR4/DDR3L device shouldbe connected through individual 240 Ω, 1% resistors toGND.Explanation/Supplemental recommendations-3. Place a 10 kΩ, 5% resistor to ground on the DRAMreset signal.This will ensure adherence to the JEDECspecification until the control is configured andstarts driving the DDR.4. The processor ball MTEST (ball N2), should be leftunconnected.These are observability ports for manufacturingand are not used otherwise.5. Using x16 bit board to test the x8 bit DDR feature,only the controller setting is different, the PHY shouldtrain as x16 bit device.Using x8 bit setting for initial and train on a x16 bitboard, it may cause some issues, such as: BG issue PDA(Per DRAM Accessibility) based trainissue.6. DLL-off mode isn’t supported, which means DDR4/DDR3L can’t run in low frequency such as 100MTS.7. VDD DRAM should be always on during DDRretention mode. Otherwise the data in DRAM might belost when exiting this mode.The power consumption for low power mode inDDR4/DDR3L system will be higher comparedwith LPDDR4 system.See Errata e50381 for detailed information.Table 5. I2C recommendationsCheck boxRecommendationsExplanation/Supplemental recommendations1. Verify the target I2C interface clock ratesThe I2C bus can only be operated as fast as theslowest peripheral on the bus. If faster operationis required, move the slow devices to anotherI2C port.2. Verify that there are no I2C address conflicts on anyof the I2C buses utilizedThere are multiple I2C ports available onchip, so if a conflict exists, move one of theconflicting devices to a different I2C bus. If itis impossible, use a I2C bus switch (NXP partnumber PCA9646).3. Do not place more than one set of pull-up resistorson the I2C lines.This could result in excessive loading andpotential incorrect operation. Choose the pullup value commensurate with the bus speedbeing used.4. Ensure that the VCC rail powering the i.MX 8M NanoPrevent device damage or incorrect operation dueI2C interface balls matches the supply voltage used forto voltage mismatch.2the pull-up resistors and the slave I C devices.i.MX 8M Nano Hardware Developer’s Guide, Rev. 1, 11/2020User's Guide9 / 74
NXP Semiconductorsi.MX 8M Nano design checklistTable 6. JTAG recommendationsCheck boxRecommendations1. Do not use external pullup or pulldown resistors onJTAG TDO.Explanation/Supplemental recommendationsJTAG TDO is configured with an on-chipkeeper circuit and the floating condition isactively eliminated.2. Follow the recommendations for external pull-up and pull-down resistors given in Table 17.3. JTAG MOD should be connected to ground througha resistor.-4. JTAG TMS pin must be connected with a 50ohmseries resistor near the component if used or fanout.Otherwise, floating if not fanout.-Table 7. Reset and ON/OFF recommendationsCheck boxRecommendationsExplanation/Supplemental recommendations1. The POR B input must be asserted at powered upand remain asserted until the last power rail for devicesrequired for system boot are at their working voltage.This functionality is controlled by the PMIC on EVK.POR B is driven by the PMIC. If a reset buttonis used, it should be connected to the PWRON Bpin of the PMIC instead of directly connectedto POR B pin of the CPU. When POR B isasserted (low) on the i.MX 8M Nano, the outputPMIC ON REQ remains asserted (high).2. For portable applications, the ONOFF pin may beconnected to an ON/OFF SPST push-button switch toground. An external pull-up resistor is required on thispin.A brief connection to GND in OFF modecauses the internal power management statemachine to change state to ON. In ON mode,a brief connection to GND generates an interrupt(intended to initiate a software-controllable powerdown). The connection to GND for approximate 5seconds or more causes a forced OFF.3. Connect GPIO1 IO02( WDOG B, ball AG13) toexternal PMIC or reset IC to repower the systemexcept SNVS is strongly recommended.i.MX8M Nano can't be reset by internal resetsource in idle mode, repower is preferred. Someperipherals like SD3.0, QSPI also need repowerduring system reset.4. GPIO1 IO02( WDOG B, ball AG13) is used as ColdReset. If using PMIC BD71850MWV, external WDOGtimer buffer circuit is needed to support boundary-scanmode.During entering boundary scan mode, WDOG Bis always low. Without the WDOG timerbuffer circuit, WDOG B will repeatedly reset8MNANOD4- EVK when entering boundary-scanmode. See section 5.5. Boundary scan operationfor more details.i.MX 8M Nano Hardware Developer’s Guide, Rev. 1, 11/2020User's Guide10 / 74
NXP Semiconductorsi.MX 8M Nano design checklistTable 8. USB recommendationsCheck boxRecommendationsExplanation/Supplemental recommendations
In this guide, notation for all logical, bit-wise, arithmetic, comparison, and assignment operations follow C Language conventions. 1.6 Acronyms and abbreviations. Table 2 defines the acronyms and abbreviations used in this document. NXP Semiconductors Overview i.MX 8M Nano Hardware Developer’s Guide, Rev. 1, 11/2020 User's Guide 5 / 74. i.MX .
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2 Connect iPod nano to a USB 3.0 port or high-power USB 2.0 port on your Mac or PC, using the cable that came with iPod nano. 3 Follow the onscreen instructions in iTunes to register iPod nano and sync iPod nano with songs from your iTunes library. If you need help using the iPod nano Setup Assistant, see Setting up iTunes syncing on page 15.
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Koppel de iPod nano niet los als de melding 'Verbonden' of 'Synchroniseren' wordt weergegeven. U moet de iPod nano verwijderen voordat u de kabel loskoppelt als u een van deze meldingen ziet. Zo voorkomt u beschadiging van bestanden op de iPod nano. Zie op pagina 13 voor meer informatie over het veilig loskoppelen van de iPod nano.
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