Getting Started With FPGA Advantage Tutorial
Getting Started with FPGA AdvantageTutorialSoftware Version 5.17 August 2001Copyright Mentor Graphics Corporation 2000-2001.All rights reserved.This document contains information that is proprietary to Mentor Graphics Corporation. The originalrecipient of this document may duplicate this document in whole or in part for internal business purposesonly, provided that this entire notice appears in all copies. In duplicating any part of this document, therecipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of theproprietary information.End-User License Agreement
This document is for information and instruction purposes. Mentor Graphics reserves the right to makechanges in specifications and other information contained in this publication without prior notice, and thereader should, in all cases, consult Mentor Graphics to determine whether any changes have beenmade.The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth inwritten agreements between Mentor Graphics and its customers. No representation or other affirmationof fact contained in this publication shall be deemed to be a warranty or give rise to any liability of MentorGraphics whatsoever.MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIALINCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OR MERCHANTABILITY ANDFITNESS FOR A PARTICULAR PURPOSE.MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, ORCONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS)ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT,EVEN IF MENTOR GRAPHICS CORPORATION HAS BEEN ADVISED OF THE POSSIBILITY OFSUCH DAMAGES.RESTRICTED RIGHTS LEGEND 03/97U.S. Government Restricted Rights. The SOFTWARE and documentation have been developed entirelyat private expense and are commercial computer software provided with restricted rights. Use,duplication or disclosure by the U.S. Government or a U.S. Government subcontractor is subject to therestrictions set forth in the license agreement provided with the software pursuant to DFARS 227.72023(a) or as set forth in subparagraph (c)(1) and (2) of the Commercial Computer Software - RestrictedRights clause at FAR 52.227-19, as applicable.Contractor/manufacturer is:Mentor Graphics Corporation8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.Web site: http://www.fpga-advantage.comEmail: FPGA support@mentor.comThis is an unpublished work of Mentor Graphics Corporation.
Trademark InformationTrademark InformationThe following names which appear in this documentation set are trademarks,registered trademarks or service marks of Mentor Graphics Corporation:HDL Designer Series , HDL Designer , HDL Pilot , HDL Detective , HDL Author ,HDL2Graphics , FPGA Advantage , Interconnect Table , Interface-Based Design ,IBD , Inventra , LeonardoInsight , LeonardoSpectrum , Mentor , Mentor Graphics ,ModelSim , ModuleWare , Renoir , Seamless , Seamless CVE and SpeedGate .The following names which appear in this documentation set are trademarks,registered trademarks or service marks of other companies:Adobe, the Adobe logo, Acrobat, the Acrobat logo, Exchange, FrameMaker and PostScriptare registered trademarks of Adobe Systems Incorporated.Altera, APEX, MegaWizard and MAX PLUS are registered trademarks and Quartus atrademark of Altera Corporation.ClearCase Attache is a trademark and ClearCase is a registered trademark of RationalSoftware Corporation.DesignSync is a registered trademark of Synchronicity Incorporated.FLEXlm is a trademark of Globetrotter Software, Incorporated.Hewlett-Packard (HP), HP-UX and PA-RISC are registered trademarks of Hewlett-PackardCompany.Leapfrog, NC-Verilog, Verilog and Verilog-XL are trademarks and registered trademarks ofCadence Design Systems Incorporated.Netscape is a trademark of Netscape Communications Corporation.SPARC is a registered trademark and SPARCstation is a trademark of SPARC InternationalIncorporated.SpyGlass is a trademark of Interra Inc.Sun Microsystems and Sun Workstation are registered trademarks of Sun MicrosystemsIncorporated. Sun and SunOS are trademarks of Sun Microsystems Incorporated.Synopsys, Design Analyzer, Design Compiler, FPGA Express, VCS, VCSi and VSS aretrademarks of Synopsys Incorporated.Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 2001i
Trademark InformationSynplify is a registered trademark of Synplicity Incorporated.The Graphics Connection is a trademark of Square One.Visual SourceSafe and Windows are trademarks of Microsoft Corporation.UNIX is a registered trademark of UNIX System Laboratories, Incorporated.Xilinx is a registered trademark and Core Generator a trademark of Xilinx, Incorporated.Other brand or product names that appear in the documentation are trademarks orregistered trademarks of their respective holders.iiGetting Started with FPGA Advantage Tutorial, Software Version 5.17 August 2001
Table of ContentsTABLE OF CONTENTSAbout This Manual .ivGetting Started with FPGA Advantage.1Welcome to FPGA Advantage .1Invoking FPGA Advantage .2Exploring the Designs.3Set Default Language .4Import the Fibonacci Design .5Select Source HDL Files .6Convert the Fibonacci Design .7Browsing the Fibonacci Design.10Examine the State Machine Text View .11Generate HDL for the State Machine .12Correct the State Machine Errors .13Create Graphical Test Bench .14Save the Test Bench.15Simulate Your Design.16Add Probes to the Test Bench .17Add a Breakpoint .18Complete the Simulation .20Invoke LeonardoSpectrum.21View the RTL Schematic.24Further Information .25Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 2001iii
About This ManualThis manual is a printable Acrobat PDF version of the online HTML GettingStarted with FPGA Advantage Tutorial. It is provided for those users who preferto work from a printed document.The screen shots and path name convention (/) are the same as those used in theWindows environment. Some screen shots in the UNIX environment will lookdifferent from the ones shown in this tutorial. However, the design flow is thesame for any configuration on all platforms.Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 2001iv
Getting Started with FPGA AdvantageWelcome to FPGA AdvantageGetting Started with FPGAAdvantageWelcome to FPGA AdvantageThis simple tutorial presents the complete design flow for a sample design fromHDL text import using, HDL2Graphics, HDL generation, simulation through tosynthesis in approximately 30 minutes.You should have installed at least one configuration of FPGA Advantage andobtained your evaluation or permanent licenses before starting this tutorial.Temporary evaluation licences can be obtained for FPGA Advantage or FPGAAdvantage Personal from the FPGA Advantage website.iiThe Getting Started tutorial is based on HDL code recovered usingHDL2Graphics and can be completed for VHDL or Verilog using any ofthe FPGA Advantage Pro or FPGA Advantage Personal Proconfigurations.A number of HDL Designer Series tutorials can also be run. See the StartHere Guide for more information.Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 20011
Invoking FPGA AdvantageGetting Started with FPGA AdvantageInvoking FPGA AdvantageYou can invoke your installed configuration of FPGA Advantage on Windows byusing the shortcut which was created by the install program on your desktop.Alternatively, you can choose the shortcut of your choice from the FPGAAdvantage 5.1 or FPGA Advantage Personal 5.1 cascade of the Programsmenu. One or more of the following options can be accessed from the WindowsStart button if they are selected during installation.FPGAdv TextFPGAdv GraphicsFPGAdv Pro(for FPGA Advantage Text)(for FPGA Advantage Graphics)(for FPGA Advantage Pro)FPGAdv Personal TextFPGAdv Personal Simulation TextFPGAdv Personal Graphics FPGAdv Personal Simulation GraphicsFPGAdv Personal ProFPGAdv Personal Simulation ProiPlease refer to the FPGA Advantage Start Here Guide to see moreinformation about the above configurations.You can invoke FPGA Advantage on UNIX using one of the following scripts ifthey are selected during installation: install path /Fpgadv/bin/fpgadvtxt (FPGA Advantage Text) install path /Fpgadv/bin/fpgadvgfx (FPGA Advantage Graphics) install path /Fpgadv/bin/fpgadvpro (FPGA Advantage Pro)2Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 2001
Getting Started with FPGA AdvantageExploring the DesignsExploring the DesignsThe HDL Designer Series (HDS) design browser will be displayed when the toolis invoked:The design browser window is divided into four browsers: Source shows the graphical and textual source design data. HDL shows the generated code. Side Data displays an expandable indented list showing design and userdata associated with the design unit view selected in the source browser. Downstream is a tabbed window which shows the data files prepared forModelSim and LeonardoSpectrum.Three example libraries are displayed with their contents: a mixed language HDLtext design named UART TXT, a graphical VHDL design named UART and thecorresponding graphical Verilog design named UART V.Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 20013
Set Default LanguageGetting Started with FPGA AdvantageSet Default LanguageA set of default preferences are loaded when you invoke FPGA Advantage forthe first time. There are separate tabbed dialog boxes for the main settings, VHDLand Verilog options, compile settings, HDL Import options, version managementsettings and master preferences for each type of graphical diagram. Thepreference dialog boxes can be accessed from the Options menu.Choose Main from the Options menu to display the Main Settings dialog box,select the Diagrams tab and ensure that Verilog is set as the default language tobe used for new diagrams. Use thebutton to confirm your languagechoice.Choose VHDL if you would like to run this tutorial using the VHDL language.All other preferences can be left with their default values for this tutorial.4Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 2001
Getting Started with FPGA AdvantageImport the Fibonacci DesignImport the Fibonacci DesignThis tutorial uses a design which is supplied as VHDL or Verilog code and can beimported using the HDL Import Wizard. This will recover any VHDL or Verilogcode using HDL Import technology and convert it into HDS text views. You candisplay the imported design using the existing design browser.From the File menu choose Close All Libraries. All browsers in the designbrowser should now be empty.To import the Fibonacci Design, choose the pulldown on thebutton andselect theoption from the palette (or choose Text HDL Import from theHDL Import cascade of the HDL menu).Select Specify HDL files in the first page of the HDL Import wizard:iThis tutorial can be completed using either the VHDL or Verilog examplecode depending upon your language preference. The language will bedetermined automatically providing that the source code file extension isrecognized in the general preferences.Click the Next button to display the Specify HDL Source Files page of the HDLImport Wizard.Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 20015
Select Source HDL FilesGetting Started with FPGA AdvantageSelect Source HDL FilesUse the Browse button to locate the Fibonacci sequencer source code in theexamples sub-directory of your FPGA Advantage installation as shown in theentry box below. For example, if FPGA Advantage has been installed in thedirectory D:\Builds\FPGAdvPersonal51, the pathname to locate all source HDLfiles would l ref\ImportUse the Files of type pulldown to select either VHDL or Verilog files. Forexample, Verilog files are shown selected below:Select the Seq Generator and the Seq TestBench HDL files by usingmouse button. Clickto convert the files.6 Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 2001
Getting Started with FPGA AdvantageConvert the Fibonacci DesignClick the Next button. You will now see the Log Window showing the Verilogsource files for the Fibonacci design as they are read in:Convert the Fibonacci DesignEach design unit now appears in a separate window in the HDL Import Wizardready for conversion.Click the Next button.Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 20017
Convert the Fibonacci DesignGetting Started with FPGA AdvantageSelect the SCRATCH LIB library from the pulldown.Click the Next button. The Confirm HDL Import dialog appears. Click theFinish button to convert the design.8Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 2001
Getting Started with FPGA AdvantageConvert the Fibonacci DesignThe HDL Log tab in the Log Window will indicate that a hierarchy of designs isbeing automatically created for the Fibonacci design and end with the followingsummary report:1 top level design unit [ fibgen tb ]5 HDS design units saved,5 components5 HDL viewsGetting Started with FPGA Advantage Tutorial, Software Version 5.17 August 20019
Browsing the Fibonacci DesignGetting Started with FPGA AdvantageBrowsing the Fibonacci DesignSelect the SCRATCH LIB library in the source browser and choose Expand Allfrom the popup menu. The design units for the Fibonacci design should now bedisplayed in the source browser as shown below:i10The Source, HDL, Side Data and Downstream browsers can each beundocked from the HDS design browser and viewed as a sub-window.This is achieved by holding down the left mouse button on the blue titlebar and dragging the window completely away from the browser. Doubleclicking on the blue title bar when a browser is undocked will return thesub-window to the HDS design browser.Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 2001
Getting Started with FPGA AdvantageExamine the State Machine Text ViewExamine the State Machine Text ViewDouble-click on the icon representing the control component design unit in theHDS design browser to display the following state machine in text view.Use the scroll bar to view the code and notice that there are two deliberate errorswhich have been added.iThe Verilog version of the state machine is shown. The VHDL versionwill be similar.Close the text editor.Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 200111
Generate HDL for the State MachineGetting Started with FPGA AdvantageGenerate HDL for the State MachineSelect the component design unit icon for fibgen tb which is displayed with a"top of design" marker in the HDS design browser.Choose Hierarchy Through Components from the Generate cascade of theHDL menu in the design browser.Notice that the Log Window now displays two error messages which have beendeliberately added to the state machine text view.The signal clear has been incorrectly entered and needs replacing with clr.12Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 2001
Getting Started with FPGA AdvantageCorrect the State Machine ErrorsCorrect the State Machine ErrorsMake the Log Window active and double-click on the line containing the error inthe log window. You should now be able to edit the code using the ESView texteditor which appears by default.Replace clear with the word clr and delete all of the comment text after the semicolon. Save your changes and close the editor.Repeat this procedure for the second occurrence of the error. The modified codeshould look similar to the example shown below.Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 200113
Create Graphical Test BenchGetting Started with FPGA AdvantageCreate Graphical Test BenchChoose Block Diagram from the New cascade of the File menu in the designbrowser.Use thebutton to display the Add Instance dialog box. Select theSCRATCH LIB library and the fibgen component and click thebutton toadd the fibgen component to the block diagram. Press the right mouse button andplace the component on the diagram. Repeat the procedure and add thefibgen tester component.Position the mouse over the fibgen component and choose Add Signal Stubsfrom the popup menu. Two signals, clock and reset are added to the diagram plusa bus named fibout.Repeat this procedure a second time for the fibgen tester component. TheWARNING messages which appear can be ignored. This is because the net clockand reset already exist and the port and net declarations differ. Clicktoacknowledge the warning message.Note from the diagram that two further clock and reset signals have been addedplus a second bus named monitor.14Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 2001
Getting Started with FPGA AdvantageSave the Test BenchSelect and delete the signal fibout. Drag and connect the signal monitor to the portfibout. The finished block diagram should look like the one shown above.Save the Test BenchUse thebutton to save the test bench. The Save As Design Unit View dialogbox is displayed which allows you to save a design unit into any currently mappedlibrary. The columns allow you to specify the design unit name with its defaultview type.Select the SCRATCH-LIB library and save the design unit name as fibgen tb. TheSave As dialog box should look similar to the example shown:Click thebutton to save the test bench.Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 200115
Simulate Your DesignGetting Started with FPGA AdvantageSimulate Your DesignSelect struct.bd view below fibgen tb from the design browser and choose SetDefault View from the popup menu. This will define the graphical test benchview struct.bd as the default view before simulating the design. Notice that thegreen triangle now appears next to struct.bd indicating the default view.Select the fibgen tb component and select thebutton from the toolbar.Messages will now appear in the HDS Log Window confirming that the HDL hasbeen compiled for all the HDS design units.Click thebutton to confirm the Start ModelSim dialog box.This simulation flow button is set up to automatically generate and compile HDLfor the hierarchy below the selected design unit. If generation and compilation arecompleted successfully, the ModelSim simulator is invoked and the entirecompiled design is loaded.The progress of HDL generation and compilation are shown in the HDS LogWindow. Notice that most design units are generated but all design units arecompiled. If any compilation errors are detected when you compile a design, youcan cross-reference from the HDS Log Window to the source graphics orgenerated HDL in the same way as for HDL generation errors.16Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 2001
Getting Started with FPGA AdvantageAdd Probes to the Test BenchAdd Probes to the Test BenchOpen the fibgen tb block diagram from the HDS design browser. Use the viewarea buttonor zoom in until the diagram looks similar to the one shownbelow. You can select multiple signals by using mouse button or bydragging a box crossing the required signals.Select the three signals monitor, clock and reset as shown in the diagram.Notice that when the simulator is invoked there is an additional simulation toolbardisplayed at the bottom of the HDS block diagram. Click thebutton to addsimulation probes showing the current value of each signal.Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 200117
Add a BreakpointGetting Started with FPGA AdvantageAdd a BreakpointIn the fibgen tb block diagram view, choose Structure from the View cascade ofthe Simulation menu in the design browser. A window showing the fibgen tbhierarchy will appear. Expand the hierarchy underneath fibgen tb and select theFSM: control view.In the fibgen tb block diagram view, choose Source from the View cascade of theSimulation menu. The state machine source window appears as shown below.Navigate to line 78 in the code by using the scroll bar and add a breakpoint by theside of the number by pressing the left mouse button. A red dot will be shownindicating that a breakpoint is set.18Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 2001
Getting Started with FPGA AdvantageAdd a BreakpointRun the SimulatorMake the fibgen tb block diagram active and click thebutton to automaticallyopen the ModelSim Wave window. Select the fibgen tb/monitor signal as shown,and press the right mouse button and choose Unsigned for the Radix cascade ofthe popup menu.In the fibgen tb block diagram view click theto advance simulation by thedefault simulator timestep (100 nanoseconds). Notice that the signal values areinitialized in the simulation probes on the test bench block diagram.Click thebutton to run the simulator until the next breakpoint. Notice that thewaveform appears as the simulation advances. Notice that an arrow appears nextto the red dot in the control.v source window.Finally, make sure that the state machine source window is active and remove thebreakpoint. You can do this in the control.v source window. Pull down the Editmenu and select breakpoints. When the breakpoint dialog appears click on theDelete All BP button. Click the Close button and notice that the red dotdisappears indicating that the breakpoint is unset.Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 200119
Complete the SimulationGetting Started with FPGA AdvantageComplete the SimulationClick the button adjacent to thebutton on the toolbar and select Choosefrom the popup menu. Another dialog will appear prompting you to enter a timeinterval to run the simulator. Enter 3000 into the entry box and click OK to run thesimulator.iAlternatively, you can enter a time interval in the ModelSim window andthen run the simulator.Choose Zoom Full from the Zoom menu in the Wave window to display the fullsimulation waveforms which should look similar to the picture below for asuccessfully verified design.Simulation is now complete. Choose Quit from the ModelSim File menu to exitfrom the simulator. Click Yes to the exit message and close the HDS blockdiagram and state machine windows.20Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 2001
Getting Started with FPGA AdvantageInvoke LeonardoSpectrumInvoke LeonardoSpectrumSelect the fibgen component in the HDS design browser and then click on thebutton. The LeonardoSpectrum Invoke Settings dialog is displayed.iYou cannot synthesize a test bench, so you must select the top leveldesign unit for the actual design you want to synthesize.Select the technology of your choice in the Quick Setup tab. For example, chooseFPGA and Xilinx XC4000E by using the buttons to expand the list of FPGAtechnologies available.iIf you are using the FPGA Advantage Personal configuration with level2 synthesis, ASIC libraries are not available and you can choose theXilinx library directly.Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 200121
Invoke LeonardoSpectrumGetting Started with FPGA AdvantageWhen you select a technology, default values are automatically entered in theDevice, Speed Grade, and Wire Table fields (these may vary from the onesshown below). The remaining fields will be set by default. Enter the value 20 inthe Clock Frequency field and synthesize your design by clicking the OK button.You are prompted to confirm the LeonardoSpectrum license.i22You must choose a Level 2 license if you are using any of the FPGAAdvantage Personal configurations. If you are using any of the FPGAAdvantage configurations, select a Level 3 license. You can uncheck theRun license selection next time option if you want to run synthesiswithout prompting for the license level next time you invoke.Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 2001
Getting Started with FPGA AdvantageInvoke LeonardoSpectrumWhen you click the OK button LeonardoSpectrum is invoked on the entire designand the HDL files for your design are shown in the Quick Setup tab.LeonardoSpectrum will optimize the design. Progress and completion messageswill be displayed in the information window showing that the synthesis run hasfinished.Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 200123
View the RTL SchematicGetting Started with FPGA AdvantageView the RTL SchematicIf you are using the Level 3 license for LeonardoSpectrum, you can display anRTL Schematic for your design by clicking thebutton. You can move aroundthe schematic using the scroll bars and the diagram can be enlarged inside thebrowser by choosing Zoom In from the Zoom cascade of the Schematic Viewerpulldown menu.i24The Schematic Viewer is not available with a LeonardoSpectrum level 2license. However, a license can be added if you obtain an additionallicense feature for LeonardoInsight.Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 2001
Getting Started with FPGA AdvantageFurther InformationYou can cross-probe from the schematic to the corresponding object in a HDSsource diagram. This is achieved by selecting an instance on the schematic andclicking the right mouse button. To view the HDS source diagram choose Traceto HDL Designer from the popup menu. The relevant HDS design unit view isdisplayed.Close the text editor windows.Exit from LeonardoSpectrum by choosing Exit from the LeonardoSpectrum Filemenu, choosing No from the confirmation dialog box.Exit from HDS by choosing Exit from the File menu in the Design Browserwindow and choosing Yes from the confirmation dialog box.Further InformationYou have now completed the FPGA Advantage Getting Started Tutorial and seenthe complete design flow from importing HDL into HDS, through verificationusing the ModelSim simulator and used LeonardoSpectrum to synthesize a gatelevel netlist.Each of these tools support a large range of features which cannot be illustrated inthis simple tutorial. For more information, see the documentation which isavailable from the Help menu in each tool.You can also access documentation from the FPGA Advantage 5.1 Bookcasewhich can be opened on Windows from the Programs cascade of the Start menu.On UNIX, this document can be accessed by opening the Adobe Acrobatdocument DocIndex.pdf which can be found in the FPGA Advantage installationat: install dir /Doc/DocIndex.pdf.The FPGA Advantage Bookcase can also be accessed from the Help pulldownmenu in the design browser on both Windows and UNIX by selecting Help FPGA Advantage Bookcase.Getting Started with FPGA Advantage Tutorial, Software Version 5.17 August 200125
Getting Started with FPGA Advantage Tutorial, Software Version 5.1 1 7 August 2001 Getting Started with FPGA Advantage Welcome to FPGA Advantage This simple tutorial presents the comple te design flow for a sample design from HDL text import using, HDL2Graphics, HDL generation, simulation through to synthesis in approximately 30 minutes.
In this thesis, FPGA-based simulation and implementation of direct torque control (DTC) of induction motors are studied. DTC is simulated on an FPGA as well as a personal computer. Results prove the FPGA-based simulation to be 12 times faster. Also an experimental setup of DTC is implemented using both FPGA and dSPACE. The FPGA-based design .
FPGA ASIC Trend ASIC NRE Parameter FPGA ASIC Clock frequency Power consumption Form factor Reconfiguration Design security Redesign risk (weighted) Time to market NRE Total Cost FPGA vs. ASIC ü ü ü ü ü ü ü ü FPGA Domain ASIC Domain - 11 - 18.05.2012 The Case for FPGAs - FPGA vs. ASIC FPGAs can't beat ASICs when it comes to Low power
Step 1: Replace ASIC RAMs to FPGA RAMs (using CORE Gen. tool) Step 2: ASIC PLLs to FPGA DCM & PLLs (using architecture wizard), also use BUFG/IBUFG for global routing. Step 3: Convert SERDES (Using Chipsync wizard) Step 4: Convert DSP resources to FPGA DSP resources (using FPGA Core gen.)
10 www.xilinx.com Getting Started with the VC707 Evaluation Kit UG848 (v1.4.1) October 14, 2015 Chapter 1: Getting Started with the Virtex-7 FPGA VC707 Evaluation Kit Built-In Self Test The BIST tests several XC7VX485T FPGA and VC 707 board features. The BIST interface is a menu of tests displayed by a
14 2 FPGA Architectures: An Overview Fig. 2.5 Overview of mesh-based FPGA architecture [22] 2.4.1 Island-Style Routing Architecture Figure2.5 shows a traditional island-style FPGA architecture (also termed as mesh-based FPGA architecture). This is the most common
5.2 Inspection of Structural Adder Using Schematic and fpga editor 5.2.1 Schematics and FPGA layout Now let’s take a look at how the Verilog you wrote mapped to the primitive components on the FPGA. Three levels
FPGA Resource Small FPGA Large FPGA Logic PLBs per FPGA 256 25,920 LUTs and flip -flops per PLB 1 8 System-on-Chip Test ArchitecturesEE141 Ch. 12 - FPGA Testing - P. 15 15 Routing Wire segments per PLB 45 406 PIPs per PLB 139 3,462 Specialized Cores Bits per memory core 128 36,864 Memory cores per FP
automotive EMC requirements and detailed description of the design recommendations for meeting them. 3. Exploring the MPC5606E Reference board 6-layer design NOTE The main design considerations are described here using the example of the 6-layer Freescale automotive BroadR-Reach board. For best performance, it is critical to closely follow these design guidelines. NOTE Use this document in .
