The RISC-V Processor - Cornell University
2 bits15 1412 117 6rs1 funct3 rd5 bits3 bits0op5 bits 7 bitsopfunct3 mnemonic0010011000ADDI rd, rs1, imm R[rd] R[rs1] sign extend(imm)0010011111ANDI rd, rs1, imm R[rd] R[rs1] & sign extend(imm)0010011110ORI rd, rs1, immExample: x5 x5 5x5 5descriptionR[rd] R[rs1] sign extend(imm)# ADDI x5, x5, 549
Arithmetic w/ immediatesProg.MemALUReg.File emoryskipExample: x5 x5 5 # ADDI x5, x5, 5WB50
Arithmetic w/ immediatesADDI x5, x5, 5Prog.MemALUReg.Filex5 5 4555PCcontrolADDI x5 x5 mple: x5 x5 5 # ADDI x5, x5, 5WB51
iClicker Question To compile the code y z 1, assuming yis stored in X1 and z is stored in X2, you canuse the ADDI instruction. What is the largestnumber for which we can continue to useADDI?(a)12(b)212-1 4,095(c) 212-1 -1 2,047(d)216-1 65,535(e)232-1 4.3 billion52
iClicker Question To compile the code y z 1, assuming yis stored in X1 and x is stored in X2, you canuse the ADDI instruction. What is the largestnumber for which we can continue to useADDI?(a)12(b)212-1 2,047(c) 212-1 4,095(d)216-1 65,535(e)232-1 4.3 billion53
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“”U-Type (1): Load Upper Immediate000000000000000001010010101101113112 117 60immrdop20 bits5 bits7 bitsopmnemonicdescription0110111LUI rd, immR[rd] sign ext(imm) 1256
“”U-Type (1): Load Upper Immediate000000000000000001010010101101113112 117 60immrdop20 bits5 bits7 bitsopmnemonicdescription0110111LUI rd, immR[rd] sign ext(imm) 12Example: x5 0x5000# LUI x5, 5Example: LUI x5, 0xbeef1ADDI x5, x5 0x234What does x5 0xbeef1234?57
Load Upper ImmediateProg.MemALUReg.File xample: x5 0x5000MemoryskipWB# LUI x5, 558
Load Upper ImmediateLUI x5, 5Prog.MemALUReg.File0x5000 4PC555controlLUI x5 5imm2012extend32shamtFetchDecodeExecuteExample: x5 0x5000MemoryskipWB# LUI x5, 559
RISC-V Instruction Types Arithmetic/Logical Memory Access Control flow R-type: result and two source registers, shift amount I-type: result and source register, shift amount in 16-bitimmediate with sign/zero extension U-type: result register, 16-bit immediate with sign/zeroextension I-type for loads and S-type for stores load/store between registers and memory word, half-word and byte operations U-type: jump-and-link I-type: jump-and-link register SB-type: conditional branches: pc-relative addresses60
I-Type (2): Load Instructions000000000100001010100000100000113120 1915 14 12 117 60imm12 bitsrs1 funct3 rd5 bits3 bitsopbase offsetaddressing5 bits 7 bitsopfunct3 mnemonicDescription0000011000LB rd, rs1, immR[rd] Mem[imm R[rs1]]0000011001LH rd, rs1, immR[rd] Mem[imm R[rs1]]0000011010LW rd, rs1, immR[rd] Mem[imm R[rs1]]0000011011LD rd, rs1, immR[rd] Mem[imm R[rs1]]0000011100LBU rd, rs1, immR[rd] Mem[imm R[rs1]]0000011101LHU rd, rs1, immR[rd] Mem[imm R[rs1]]0000011110LWU rd, rs1, immR[rd] Mem[imm R[rs1]]signedoffsets61
I-Type (2): Load Instructions000000000100001010100000100000113120 1915 14 12 117 60imm12 bitsrs1 funct3 rd5 bits3 bitsopbase offsetaddressing5 bits 7 bitsopfunct3 mnemonicDescription0000011000LB rd, rs1, immR[rd] Mem[imm R[rs1]]0000011001LH rd, rs1, immR[rd] Mem[imm R[rs1]]0000011010LW rd, rs1, immR[rd] Mem[imm R[rs1]]0000011011LD rd, rs1, immR[rd] Mem[imm R[rs1]]0000011100LBU rd, rs1, immR[rd] Mem[imm R[rs1]]0000011101LHU rd, rs1, immR[rd] Mem[imm R[rs1]]0000011110LWU rd, rs1, immR[rd] Mem[imm R[rs1]]Example: x1 Mem[4 x5] # LW x1, x5, 4LW x1 4(x5)signedoffsets62
I-Type (2): Load Instructions000000000100001010100000100000113120 1915 14 12 117 60imm12 bitsrs1 funct3 rd5 bits3 bitsopbase offsetaddressing5 bits 7 bitsopfunct3 mnemonicDescription0000011000LB rd, rs1, immR[rd] sign ext(Mem[imm R[rs1]])0000011001LH rd, rs1, immR[rd] sign ext(Mem[imm R[rs1]])0000011010LW rd, rs1, immR[rd] Mem[imm R[rs1]]0000011011LD rd, rs1, immR[rd] Mem[imm R[rs1]]0000011100LBU rd, rs1, immR[rd] zero ext(Mem[imm R[rs1]])0000011101LHU rd, rs1, immR[rd] zero ext(Mem[imm R[rs1]])0000011110LWU rd, rs1, immR[rd] Mem[imm R[rs1]]Example: x1 Mem[4 x5] # LW x1, x5, 4LW x1 4(x5)signedoffsets63
Memory Operations: LoadProg.MemALUReg.Fileaddr 4555PCDataMemcontrolWrite Enableimm16extend12Example: x1 Mem[4 x5] # LW x1, x5, 4LW x1 4(x5)64
Memory Operations: LoadLW x1, x5, 4Prog.MemALU 4 x5Reg.Fileaddr 4PC555controlLW x1 x5 4imm12FetchDataMem[4 x5MemDecodeWrite Enableextend32ExecuteMemoryExample: x1 Mem[4 x5] # LW x1, x5, 4LW x1 4(x5)WB65
S-Type (1): Store Instructions0000100000000010101000000001001131op25 2420 19immrs27 bits5 bits 5 bits15 1412 1176rs1 funct3 imm3 bitsfunct3 mnemonic0Op5 bits 7 bitsbase offsetaddressingdescription0100011 000SB rs2, rs1, immMem[sign ext(imm) R[rs1]] R[rd]0100011 001SH rs2, rs1, imm Mem[sign ext(imm) R[rs1]] R[rd]0100011 010SW rs2, rs1, imm Mem[sign ext(imm) R[rs1]] R[rd]signedoffsets66
S-Type (1): Store Instructions0000100000000010101000000001001131op25 2420 19immrs27 bits5 bits 5 bits15 1412 1176rs1 funct3 imm3 bitsfunct3 mnemonic0Op5 bits 7 bitsbase offsetaddressingdescription0100011 000SB rs2, rs1, immMem[sign ext(imm) R[rs1]] R[rd]0100011 001SH rs2, rs1, imm Mem[sign ext(imm) R[rs1]] R[rd]0100011 010SW rs2, rs1, imm Mem[sign ext(imm) R[rs1]] R[rd]signedoffsetsExample: Mem[128 x5] x1# SW x1, x5, 128SW x1 128(x5)67
Memory Operations: LoadSW x1, x5, 128Prog.MemALU 128 x5Reg.Fileaddr 4PC555controlSW x1 x5 128imm12FetchDataMemDecodeWrite Enableextend32ExecuteMemoryExample: Mem[4 x5] x1 # SW x1, x5, 128SW x1 128(x5)WB68
Memory Layout Options # x5 contains 5(0x00000005)0x000fffff SB x5, x0, 0 SB x5, x0, 2 SW x5, x0, 80x0000000a Two ways to store a wordin memory.Endianness: ordering ofbytes within a memory 000010x0000000069
Little EndianEndianness: Ordering of bytes within a memory wordLittle Endian least significant part first (RISC-V, x86)1000100110021003as 4 bytesas 2 halfwords0x12345678as 1 wordClicker Question: What values go in the byte-sizedboxes with addresses 1000 and 1001?a) 0x8, 0x7d) 0x12, 0x34b) 0x78, 0x56e) 0x1, 0x2c) 0x87, 0x65THIS IS WHAT YOUR PROJECTS70WILL BE70
Little EndianEndianness: Ordering of bytes within a memory wordLittle Endian least significant part first (RISC-V, x86)1000100110021003as 4 bytesas 2 halfwords0x12345678as 1 wordClicker Question: What values go in the byte-sizedboxes with addresses 1000 and 1001?a) 0x8, 0x7d) 0x12, 0x34b) 0x78, 0x56e) 0x1, 0x2c) 0x87, 0x65THIS IS WHAT YOUR PROJECTS71WILL BE71
Little EndianEndianness: Ordering of bytes within a memory wordBig Endian most significant part first (MIPS, networks)1000100110021003as 4 bytesas 2 halfwords0x12345678as 1 wordClicker Question: What value goes in the half-wordsized box with address 1000?a) 0x1d) 0x4321b) 0x12e) 0x5678c) 0x1234THIS IS WHAT YOUR PROJECTS72WILL BE72
Little EndianEndianness: Ordering of bytes within a memory wordBig Endian most significant part first (MIPS, networks)1000100110021003as 4 bytesas 2 halfwords0x12345678as 1 wordClicker Question: What value goes in the half-wordsized box with address 1000?a) 0x1d) 0x4321b) 0x12e) 0x5678c) 0x1234THIS IS WHAT YOUR PROJECTS73WILL BE73
Little EndianLittle Endian least significantpart first (RISC-V, x86)WHAT WE USE IN 34100x000fffff.0x0000000bExample:r5 contains 5 (0x00000005)SW r5, 8(r0)Clicker Question: After executingthe store, which byte addresscontains the byte 0x05?a) 0x00000008b) 0x00000009c) 0x0000000ad) 0x0000000be) I don’t 00010x00000000 74
Little EndianLittle Endian least significantpart first (RISC-V, x86)WHAT WE USE IN 34100x000fffff.0x0000000bExample:r5 contains 5 (0x00000005)SW r5, 8(r0)Clicker Question: After executingthe store, which byte addresscontains the byte 0x05?a) 0x00000008b) 0x00000009c) 0x0000000ad) 0x0000000be) I don’t 00010x00000000 75
Big EndianBig Endian most significantpart first (some MIPS, networks)0x000fffff.0x0000000bExample:r5 contains 5 (0x00000005)SW r5, 8(r0)Clicker Question: After executingthe store, which byte addresscontains the byte 0x05?a) 0x00000008b) 0x00000009c) 0x0000000ad) 0x0000000be) I don’t 00010x00000000 76
Big EndianBig Endian most significantpart first (some MIPS, networks)0x000fffff.0x0000000bExample:r5 contains 5 (0x00000005)SW r5, 8(r0)Clicker Question: After executingthe store, which byte addresscontains the byte 0x05?a) 0x00000008b) 0x00000009c) 0x0000000ad) 0x0000000be) I don’t 00010x00000000 77
Big Endian Memory Layoutx00x000fffff.0x00000005 x50x00000005 x60x00000000 x70x00000005 x8 SB x5, x0, 2LB x6, x0, 2SW x5, x0, 8LB x7, x0, 8LB x8, x0, 000000030x050x000000020x000000010x00000000 78
RISC-V Instruction Types Arithmetic/Logical Memory Access Control flow R-type: result and two source registers, shift amount I-type: result and source register, shift amount in 16-bitimmediate with sign/zero extension U-type: result register, 16-bit immediate with sign/zeroextension I-type for loads and S-type for stores load/store between registers and memory word, half-word and byte operations U-type: jump-and-link I-type: jump-and-link register S-type: conditional branches: pc-relative addresses79
UJ-Type (2): Jump and Link000000000000000010000010111011113112 117 60immrdop20 bits5 bits7 bitsopMnemonicDescription1101111JAL rd, immR[rd] PC 4;PC PC sext(imm)Example: x5 PC 4# JAL x5, 16PC PC 16 (i.e. 16 8 1)Why?Function/procedure calls80
Jump and LinkProg.MemALUReg.Fileaddr 4555PCDataMemcontrolWrite Enableimm12extend32Example: x5 PC 4# JAL x5, 16PC PC 16 (i.e. 16 8 1)81
Jump and LinkJAL x5, 16Prog.MemALUReg.Fileaddr 4555PCDataMemcontrolWrite Enable immextendCould haveused ALU forJAL addExample: x5 PC 4# JAL x5, 16PC PC 16 (i.e. 16 8 1)82
I-Type (3): Jump and Link Register000000010000001000000010111001113120 19imm12 bits15 1412 117 6rs1 funct3 rd5 bits3 bits0op5 bits 7 bitsopfunct3MnemonicDescription1100111000JALR rd, rs1, immR[rd] PC 4;PC (R[rs1] sign ex(imm))&0xfffffffeExample: x5 PC 4PC x4 16# JALR x5, x4, 16Why?Function/procedure calls83
Jump and Link RegisterProg.MemALUReg.Fileaddr 4555PCDataMemcontrolWrite Enable immextendExample: x5 PC 4PC x4 16# JALR x5, x4, 1684
Jump and Link RegisterJALR x5, x4, 16Prog.MemALUReg.Fileaddr 4555PCDataMemcontrolWrite Enable immextendx4 16Example: x5 PC 4PC x4 16# JALR x5, x4, 1685
Moving Beyond Jumps Can use Jump and link (JAL) or Jump and LinkRegister (JALR) instruction to jump to 0xabcd1234What about a jump based on a condition? # assume 0 x3 1 if (x3 0) jump to 0xdecafe00else jump to 0xabcd123486
SB-Type (2): Branches0000010000000010100000000001001131op25 2420 19immrs27 bits5 bits 5 bitsmnemonic15 1412 1176rs1 funct3 imm3 bits0Op5 bits 7 bitssigneddescription1100011 BEQ rs1, rs2, imm PC (R[rs1] R[rs2] ? PC sext(imm) 1 : PC 4)1100011 BNE rs1, rs2, imm PC (R[rs1] ! R[rs2] ? PC sext(imm) 1 : PC 4)Example: BEQ x5, x1, 128if(R[x5] R[x1])PC PC 128 (i.e. 128 64 1)A word about all these ’s 87
Control Flow: BranchesProg.MemALUReg.Fileaddr 4555PCDataMemcontrolWrite Enable immextendExample: BEQ x5, x1, 12888
Control Flow: BranchesBEQ x5, x1, 128Prog.MemALUReg.Fileaddr 4555PC ?control BEQDataMemWrite Enable (PC 64 1immextendCould haveused ALU forbranch addExample: BEQ x5, x1, 128Could haveused ALU forbranch cmp89
SB-Type (3): Conditional Jumps000000000000001010001000000100113125 2420 19immrs27 bits5 bits 5 bits15 1412 1176rs1 funct3 imm3 bits0Op5 bits 7 bitsopfunct3mnemonicdescription1100011100BLT rs1, rs2, immPC (R[rs1] s R[rs2] ?PC sext(imm) 1 : PC 4)1100011101BGE rs1, rs2, immPC (R[rs1] s R[rs2] ?PC sext(imm) 1 : PC 4)1100011110BLTU rs1, rs2 immPC (R[rs1] u R[rs2] ?PC sext(imm) 1 : PC 4)1100011111BGEU rs1, rs2, imm PC (R[rs1] u R[rs2] ?PC sext(imm) 1 : PC 4)Example: BGE x5, x0, 32if(R[x5] s R[x0])PC PC 32 (i.e. 32 16 1)90
Control Flow: More BranchesBGE x5, x0, 32Prog.MemALUReg.Fileaddr 4PC555offset ?controlcmpBGE immextendPC 16 1DataMemWrite EnableCould haveused ALU forbranch cmpExample: BGE x5, x0, 3291
RISC-V Instruction Types Arithmetic/Logical Memory Access Control flow R-type: result and two source registers, shift amount I-type: result and source register, shift amount in 16-bitimmediate with sign/zero extension U-type: result register, 16-bit immediate with sign/zeroextension I-type for loads and S-type for stores load/store between registers and memory word, half-word and byte operations U-type: jump-and-link I-type: jump-and-link register S-type: conditional branches: pc-relative addresses92
iClicker QuestionWhat RISC-V instruction would you use for a:1. For loop?2. While loop?3. Function call?4. If statement?5. Return statement?(A)Jump and Link Register (JALR lr, x2,0x000FFFF)(B) Branch Equals (BEQ x1, x2, 0xAAAA)(C) Branch Less Than (BLT x1, x2, 0xAAAA)(D)Jump and Link (JAL lr, 0x000FFFF)93
iClicker Question What is the one topic you’re most uncertainabout at this point in the class?(A) Gates & Logic(B) Circuit Simplification(C) Finite State Machines(D) RISC-V Processor(E) RISC-V Assembly94
SummaryWe have all that it takes to build a processor! Arithmetic Logic Unit (ALU) Register File MemoryRISC-V processor and ISA is an example of aReduced Instruction Set Computers (RISC) Simplicity is key, thus enabling us to build it!We now know the data path for the MIPS ISA: register, memory and control instructions95
Leave, watch a movie such as Stranger Things, . Read opcode; determine instruction type, field lengths Read in data from register file (0, 1, or 2 reads for jump, addi, or add, respectively) . 7 bits 5 bits 5 bits 3 bits 5 bits 7 bits 31 12 11 76 0 imm rd op 20 bits 5
May 02, 2018 · D. Program Evaluation ͟The organization has provided a description of the framework for how each program will be evaluated. The framework should include all the elements below: ͟The evaluation methods are cost-effective for the organization ͟Quantitative and qualitative data is being collected (at Basics tier, data collection must have begun)
Silat is a combative art of self-defense and survival rooted from Matay archipelago. It was traced at thé early of Langkasuka Kingdom (2nd century CE) till thé reign of Melaka (Malaysia) Sultanate era (13th century). Silat has now evolved to become part of social culture and tradition with thé appearance of a fine physical and spiritual .
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Dr. Sunita Bharatwal** Dr. Pawan Garga*** Abstract Customer satisfaction is derived from thè functionalities and values, a product or Service can provide. The current study aims to segregate thè dimensions of ordine Service quality and gather insights on its impact on web shopping. The trends of purchases have
Epiphany-V: A 1024 processor 64-bit RISC System-On-Chip Epiphany-V: A 1024 processor 64-bit RISC System-On-Chip ByAndreasOlofsson AdaptevaInc,Lexington,MA,USA andreas@adapteva.com Abstract This paper describes the design of a 1024-core processor chip
Chính Văn.- Còn đức Thế tôn thì tuệ giác cực kỳ trong sạch 8: hiện hành bất nhị 9, đạt đến vô tướng 10, đứng vào chỗ đứng của các đức Thế tôn 11, thể hiện tính bình đẳng của các Ngài, đến chỗ không còn chướng ngại 12, giáo pháp không thể khuynh đảo, tâm thức không bị cản trở, cái được
Project Report Yi Li Cornell University yl2326@cornell.edu Rudhir Gupta Cornell University rg495@cornell.edu Yoshiyuki Nagasaki Cornell University yn253@cornell.edu Tianhe Zhang Cornell University tz249@cornell.edu Abstract—For our project, we decided to experiment, desig
