2.7 V To 5.5 V, 12-Bit, 8 S ADC In 8-Lead SOIC/PDIP AD7896
2.7 V to 5.5 V, 12-Bit, 8 sADC in 8-Lead SOIC/PDIPAD7896FEATURES100 kHz Throughput RateFast 12-Bit Sampling ADC with 8 s Conversion Time8-Lead PDIP and SOICSingle 2.7 V to 5.5 V Supply OperationHigh Speed, Easy-to-Use Serial InterfaceOn-Chip Track-and-Hold AmplifierAnalog Input Range Is 0 V to SupplyHigh Input ImpedanceLow Power: 9 mW TypFUNCTIONAL BLOCK DIAGRAMVDDAD7896TRACK-AND-HOLDV LKSDATAGENERAL DESCRIPTIONPRODUCT HIGHLIGHTSThe AD7896 is a fast, 12-bit ADC that operates from a single2.7 V to 5.5 V supply and is housed in small 8-lead PDIP and8-lead SOIC packages. The part contains an 8 µs successiveapproximation ADC, an on-chip track-and-hold amplifier, anon-chip clock, and a high speed serial interface.1. Complete, 12-bit ADC in an 8-Lead Package.The AD7896 contains an 8 µs ADC, a track-and-hold amplifier, control logic, and a high speed serial interface, all in an8-lead PDIP. The VDD input is used as the reference for thepart, so no external reference is needed. This offers considerable space saving over alternative solutions.Output data from the AD7896 is provided via a high speed,serial interface port. This 2-wire serial interface has a serialclock input and a serial data output with the external serialclock accessing the serial data from the part.In addition to the traditional dc accuracy specifications, such aslinearity, full-scale, and offset errors, the AD7896 is also specified for dynamic performance parameters, including harmonicdistortion and signal-to-noise ratio.The part accepts an analog input range of 0 V to VDD and operatesfrom a single 2.7 V to 5.5 V supply, consuming only 9 mWtypical. The VDD input is also used as the reference for the partso that no external reference is required.2. Low Power, Single-Supply Operation.The AD7896 operates from a single 2.7 V to 5.5 V supplyand consumes only 9 mW typical. The automatic powerdown mode, where the part goes into power down onceconversion is complete and “wakes up” before the next conversion cycle, makes the AD7896 ideal for battery-poweredor portable applications.3. High Speed Serial Interface.The part provides high speed serial data and serial clock linesallowing for an easy, 2-wire serial interface arrangement.The AD7896 features a high sampling rate mode and, for lowpower applications, a proprietary automatic power-down modewhere the part automatically goes into power-down once conversion is complete and “wakes up” before the next conversion cycle.The part is available in a small, 8-lead, 0.3'' wide, plastic orhermetic dual-in-line package (PDIP) and in an 8-lead, smalloutline IC (SOIC).Rev. DInformation furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third parties thatmay result from its use. No license is granted by implication or otherwiseunder any patent or patent rights of Analog Devices. Trademarks andregistered trademarks are the property of their respective companies.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700www.analog.com 1994–2011 Analog Device, Inc. All rights reserved.Fax: 781/461-3113
AD7896–SPECIFICATIONSParameterA Version1DYNAMIC PERFORMANCE 2Signal-to-(Noise Distortion) Ratio3@ 25 C70(VDD 2.7 V to 5.5 V, AGND DGND 0 V. All specifications TMIN to TMAX,unless otherwise noted.)B VersionJ Version S Version Unit7070 typ70dB min–77dB mindB maxTMIN to TMAXTotal Harmonic Distortion (THD)3–7770–77–80 typPeak Harmonic or Spurious Noise3–80–80–80 typ–77–80–77–80–80 typ–80 typ–77–80dB maxdB max12121212Bits12 1 1 3 4 412 1/2 1 1.5 4 312 1 1 3 5 512 1 1 3 4 4BitsLSB maxLSB maxLSB maxLSB maxLSB max0 to VDD 20 to VDD 20 to VDD 0 to VDD V 2 5µA max2.02.40.8 10102.02.40.8 10102.02.40.8 1010dB maxIntermodulation Distortion (IMD)3Second Order TermsThird Order TermsDC ACCURACYResolutionMinimum Resolution for Which NoMissing Codes Are GuaranteedRelative Accuracy3Differential Nonlinearity3Positive Full-Scale Error3Unipolar Offset ErrorANALOG INPUTInput Voltage RangeInput CurrentLOGIC INPUTSInput High Voltage, VINHInput Low Voltage, VINLInput Current, IINInput Capacitance, CIN4LOGIC OUTPUTSOutput High Voltage, VOHOutput Low Voltage, VOLOutput CodingCONVERSION RATEConversion TimeMode 1 OperationMode 2 Operation5Track-and-Hold Acquisition Time32.40.48141.52.42.40.40.4Straight (Natural) Binary8141.58141.5–2–Test Conditions/CommentsfIN 10 kHz Sine Wave,fSAMPLE 100 kHzfIN 10 kHz Sine Wave,fSAMPLE 100 kHzfIN 10 kHz Sine Wave,fSAMPLE 100 kHzfa 9 kHz, fb 9.5 kHz,fSAMPLE 100 kHzVDD 5 V 10%VDD 2.7 V to 3.6 V2.02.40.8 1010V minVDD 2.7 V to 3.6 VVDD 5 V 10%V maxµA maxpF maxVIN 0 V to VDD2.40.4V minV maxISOURCE 400 AISINK 1.6 mA8.514.51.5µs maxµs maxµs maxRev. D
AD7896ParameterA Version1B VersionJ VersionS Version UnitPOWER 555510.810.810.810.85155015013.55155015013.55 typ755050013.55755050013.5Power DissipationPower-Down ModeIDD @ 25 CTMIN to TMAXIDD @ 25 CTMIN to TMAXPower Dissipation @ 25 CTest Conditions/CommentsV min/maxmA maxDigital Input @ DGND,VDD 2.7 V to 3.6 VmA maxDigital Inputs @ DGND,VDD 5 V 10%mW max VDD 2.7 V, Typically 9 mWDigital Inputs @ DGNDµA maxVDD 2.7 V to 3.6 VµA maxVDD 2.7 V to 3.6 VµA maxVDD 5 V 10%µA maxVDD 5 V 10%µW maxVDD 2.7 VNOTES1Temperature ranges are as follows: A, B Versions: –40 C to 85 C; J Version: 0 C to 70 C; S Version: –55 C to 125 C.2Applies to Mode 1 operation. See the section on Operating Modes.3See Terminology.4Sample tested @ 25 C to ensure compliance.5This 14 µs includes the wake-up time from standby. This wake-up time is timed from the rising edge of CONVST, whereas conversion is timed from the falling edgeof CONVST, for narrow CONVST pulsewidth the conversion time is effectively the wake-up time plus conversion time, hence 14 µs. This can be seen from Figure 3.Note that if the CONVST pulsewidth is greater than 6 µs, the effective conversion time will increase beyond 14 µs.Specifications subject to change without notice.TIMING CHARACTERISTICS1 (VDD 2.7 V to 5.5 V, AGND DGND 0 V)ParameterA, B VersionsJ VersionS VersionUnitTest 2ns minns minns min603100310504603100310504703110310504ns maxns maxns minns maxCONVST PulsewidthSCLK High PulsewidthSCLK Low PulsewidthData Access Time after Falling Edge of SCLKVDD 5 V 10%VDD 2.7 V to 3.6 VData Hold Time after Falling Edge of SCLKBus Relinquish Time after Falling Edge of SCLKt5t6NOTES1Sample tested at 25 C to ensure compliance. All input signals are measured with tr tf 1 ns (10% to 90% of V DD) and timed from a voltage level of 1.4 V.2The SCLK maximum frequency is 10 MHz. Care must be taken when interfacing to account for the data access time, t 4, and the setup time required for the user’sprocessor. These two times will determine the maximum SCLK frequency that the user’s system can operate with. See Serial Interface section for more information.3Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2 V.4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated backto remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 6, quoted in the timing characteristics is the true bus relinquish timeof the part and as such is independent of external bus loading capacitances.1.6mATOOUTPUTPIN1.6V50pF400 AFigure 1. Load Circuit for Access Time and BusRelinquish TimeRev. D–3–
AD7896ABSOLUTE MAXIMUM RATINGS*(TA 25 C, unless otherwise noted.)VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 VVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 VAnalog Input Voltage to AGND . . . . . . –0.3 V to VDD 0.3 VDigital Input Voltage to DGND . . . . . . –0.3 V to VDD 0.3 VDigital Output Voltage to DGND . . . . . –0.3 V to VDD 0.3 VOperating Temperature RangeCommercial (J Version) . . . . . . . . . . . . . . . . . 0 C to 70 CIndustrial (A, B Versions) . . . . . . . . . . . . . . –40 C to 85 CExtended (S Version) . . . . . . . . . . . . . . . . . –55 C to 125 CStorage Temperature Range . . . . . . . . . . . . . –65 C to 150 CJunction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 CPDIP Package, Power Dissipation . . . . . . . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 125 C/W JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 50 C/WLead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 260 CSOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 160 C/W JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75 C/WLead Temperature, SolderingVapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215 CInfrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 CESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4000 V*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of thedevice at these or any other conditions above those listed in the operationalsections of this specification is not implied. Exposure to absolute maximum ratingconditions for extended periods may affect device reliability.CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccumulate on the human body and test equipment and can discharge without detection. Although theAD7896 features proprietary ESD protection circuitry, permanent damage may occur on devicessubjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommendedto avoid performance degradation or loss of functionality.–4–Rev. D
AD7896PIN CONFIGURATIONV IN 18 BUSYAD78967 CONVSTTOP VIEW3AGND(Not to Scale) 6 DGNDVDD 2SCLK 45 SDATAPIN FUNCTION DESCRIPTIONSPin No.MnemonicDescription1VINAnalog Input. The analog input range is 0 V to VDD.2VDDPositive supply voltage, 2.7 V to 5.5 V.3AGNDAnalog Ground. Ground reference for track-and-hold, comparator, and DAC.4SCLKSerial Clock Input. An external serial clock is applied to this input to obtain serial data from the AD7896.A new serial data bit is clocked out on the falling edge of this serial clock. Data is guaranteed valid for10 ns after this falling edge so data can be accepted on the falling edge when a fast serial clock is used.The serial clock input should be taken low at the end of the serial data transmission.5SDATASerial Data Output. Serial data from the AD7896 is provided at this output. The serial data is clockedout by the falling edge of SCLK, but the data can also be read on the falling edge of the SCLK. This ispossible because data bit N is valid for a specified time after the falling edge of the SCLK (data holdtime) and can be read before data bit N 1 becomes valid a specified time after the falling edge of SCLK(data access time) (see Figure 4). Sixteen bits of serial data are provided with four leading zeros followedby the 12 bits of conversion data. On the 16th falling edge of SCLK, the SDATA line is held for the datahold time and then disabled (three-stated). Output data coding is straight binary.6DGNDDigital Ground. Ground reference for digital circuitry.7CONVSTConvert Start. Edge-triggered logic input. On the falling edge of this input, the track-and-hold goes intoits hold mode and conversion is initiated. If CONVST is low at the end of conversion, the part goes intopower-down mode. In this case, the rising edge of CONVST “wakes up” the part.8BUSYThe BUSY pin is used to indicate when the part is doing a conversion. The BUSY pin goes high on thefalling edge of CONVST and returns low when the conversion is complete.Rev. D–5–
AD7896TERMINOLOGYRelative AccuracyTotal Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the rms sum ofharmonics to the fundamental. For the AD7896, it is defined as:This is the maximum deviation from a straight line passingthrough the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale (which is VIN AGND 1/2 LSB), a point 1/2 LSB below the first code transition (00 . . . 000 to 00 . . . 001), and full scale (which is VIN AGND VDD – 1/2 LSB), a point 1/2 LSB above the last codetransition (11 . . . 110 to 11 . . . 111).THD ( dB) 20 logDifferential NonlinearityThis is the difference between the measured and the ideal 1 LSBchange between any two adjacent codes in the ADC.Unipolar Offset ErrorThis is the deviation of the first code transition (00 . . . 000 to00 . . . 001) from the ideal VIN voltage (AGND 1 LSB).Positive Full-Scale ErrorThis is the deviation of the last code transition (11 . . . 110 to11 . . . 111) from the ideal (VIN AGND VDD – 1 LSB)after the offset error has been adjusted out.V2 2 V32 V4 2 V5 2 V6 2V1where V1 is the rms amplitude of the fundamental and V2, V3,V4, V5, and V6 are the rms amplitudes of the second through thesixth harmonics.Peak Harmonic or Spurious NoisePeak harmonic or spurious noise is defined as the ratio of therms value of the next largest component in the ADC outputspectrum (up to fS/2 and excluding dc) to the rms value of thefundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for partswhere the harmonics are buried in the noise floor, it will be anoise peak.Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa andfb, any active device with nonlinearities will create distortionproducts at sum and difference frequencies of mfa nfb wherem, n 0, 1, 2, 3, etc. Intermodulation distortion terms arethose for which neither m nor n are equal to zero. For example,the second order terms include (fa fb) and (fa – fb), while thethird order terms include (2fa fb), (2fa – fb), (fa 2fb), and(fa – 2fb).Track-and-Hold Acquisition TimeTrack-and-hold acquisition time is the time required for theoutput of the track-and-hold amplifier to reach its final value,within 1/2 LSB, after the end of conversion (the point at whichthe track-and-hold returns into track mode). It also applies to asituation where there is a step input change on the input voltageapplied to the selected VIN input of the AD7896. It means thatthe user must wait for the duration of the track-and-hold acquisition time after the end of conversion or after a step input changeto VIN before starting another conversion, to ensure the partoperates to specification.Signal-to-(Noise Distortion) RatioThis is the measured ratio of signal-to-(noise distortion) at theoutput of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up tohalf the sampling frequency (fS/2), excluding dc. The ratio isdependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise.The theoretical signal-to-(noise distortion) ratio for an idealN-bit converter with a sine wave input is given by:The AD7896 is tested using the CCIF standard where twoinput frequencies near the top end of the input bandwidth areused. In this case, the second order terms are usually distancedin frequency from the original sine waves while the third orderterms are usually at a frequency close to the input frequencies.As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is asper the THD specification where it is the ratio of the rms sum ofthe individual distortion products to the rms amplitude of thefundamental expressed in dB.Signal-to-(Noise Distortion) (6.02N 1.76) dBThus, for a 12-bit converter, this is 74 dB.–6–Rev. D
AD7896track-and-hold is greater than the Nyquist rate of the ADC evenwhen the ADC is operated at its maximum throughput rate of100 kHz (i.e., the track-and-hold can handle input frequenciesin excess of 50 kHz).CONVERTER DETAILSThe AD7896 is a fast, 12-bit ADC that operates from a single2.7 V to 5.5 V supply. It provides the user with a track-andhold, ADC, and serial interface logic functions on a singlechip. The ADC section of the AD7896 consists of a conventional successive approximation converter based on an R-2Rladder structure. The internal reference for the AD7896 isderived from VDD, which allows the part to accept an analoginput range of 0 V to VDD. The AD7896 has two operatingmodes: the high sampling mode and the auto sleep modewhere the part automatically goes into sleep after the end ofconversion. These modes are discussed in more detail in theTiming and Control section.The track-and-hold amplifier acquires an input signal to 12-bitaccuracy in less than 1.5 µs. The operation of the track-andhold is essentially transparent to the user. With the high samplingoperating mode, the track-and-hold amplifier goes from itstracking mode to its hold mode at the start of conversion (i.e.,the rising edge of CONVST). The aperture time for the trackand-hold (i.e., the delay time between the external CONVSTsignal and the track-and-hold actually going into hold) is typically 15 ns. At the end of conversion (on the falling edge ofBUSY), the part returns to its tracking mode. The acquisitiontime of the track-and-hold amplifier begins at this point. For theauto shutdown mode, the rising edge of CONVST wakes up thepart and the track-and-hold amplifier goes from its trackingmode to its hold mode 6 µs after the rising edge of CONVST(provided that the CONVST high time is less than 6 µs). Onceagain the part returns to its tracking mode at the end of conversion when the BUSY signal goes low.A major advantage of the AD7896 is that it provides all of thepreceding functions in an 8-lead package, PDIP or SOIC. Thisoffers the user considerable space saving advantages over alternative solutions. The AD7896 consumes only 9 mW typical, makingit ideal for battery-powered applications.Conversion is initiated on the AD7896 by pulsing the CONVSTinput. On the falling edge of CONVST, the on-chip track-andhold goes from track to hold mode and the conversion sequenceis started. The conversion clock for the part is generated internally using a laser-trimmed clock oscillator circuit. Conversiontime for the AD7896 is 8 µs in the high sampling mode (14 µsfor the auto sleep mode), and the track-and-hold acquisitiontime is 1.5 µs. To obtain optimum performance from the part,the read operation should not occur during the conversion orduring 400 ns prior to the next conversion. This allows the partto operate at throughput rates up to 100 kHz and achieves datasheet specifications (see the Timing and Control section).Timing and ControlFigure 2 shows the timing and control sequence required toobtain optimum performance from the AD7896. In thesequence shown, conversion is initiated on the falling edge ofCONVST and new data from this conversion is available in theoutput register of the AD7896 8 µs later. Once the read operation has taken place, another 400 ns should be allowed beforethe next falling edge of CONVST to optimize the settling of thetrack-and-hold amplifier before the next conversion is initiated.With the serial clock frequency at its maximum of 10 MHz (5 Voperation), the achievable throughput time for the part is 8 µs(conversion time) plus 1.6 µs (read time) plus 0.4 µs (acquisition time). This results in a minimum throughput time of 10 µs(equivalent to a throughput rate of 100 kHz). A serial clock ofless than 10 MHz can be used, but this will in turn mean thatthe throughput time will increase.CIRCUIT DESCRIP
2.7 V to 5.5 V, 12-Bit, 8 s ADC in 8-Lead SOIC/PDIP GENERAL DESCRIPTION The AD7896 is a fast, 12-bit ADC that operates from a single 2.7 V to 5.5 V supply and is housed in small 8-lead PDIP and 8-lead SOIC packages. The part contains an 8 µs successive approximation ADC, an on-chip track-and-hold amplifier, an
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Contents Chapter 1 Welcome to the AutoCAD Civil 3D Tutorials . . . . . . . . . . . . 1 Getting More Information . . . . . . . . . . . . . . . . . . . . . . . . . 2
