Strain For CMOS Performance Improvement

Deposition) or RTCVD (Rapid Thermal CVD) nitride), isuniformly deposited over the wafer. The drive currentdependence on stress is through the change in film thicknessand material [8]. The remaining steps follow a conventionalprocess flow, including interlayer dielectric and contactformation. Thicker nitride capping layer can increase thestress level. However, this will impact the conformity of gapfill itself, subsequent interlayer dielectric (ILD) gap fill, andcontact opening process.Fig. 6 shows the drive current improvement forNMOS with tensile stress and PMOS with compressive stressliner [9]. Tensile liner improves NMOS current by 11% (and17% after self-heating correction) and compressive linerimproves PMOS current by 20% than that of the non-stressedprocess.If one single liner is used, one drawback of thisapproach is that the device of the opposite type will bedegraded. One of the possible solutions is to use high dose ofGe implantation to destroy the nitride film and relax its stress[10]. For example, a highly tensile stress nitride film isdeposited over both N & PMOS, and Ge is selectivelyimplanted into PMOS region to relax the nitride stress. It isadvised that the subsequent processes to have low thermalbudget to prevent the stress stability of the liner.The above method cannot provide both NMOS andPMOS to their highest performance. In order to achieveultimate CMOS performance, two types of stress liners shouldbe applied to NMOS and PMOS accordingly. For example, ahighly tensile nitride liner is deposited first. It is selectivelyetched on the PMOS regions. Next, a highly compressiveIoff (A/Pm)10-4a) Ion (PA/Pm)b) PMOS10-6Ioff (A/Pm)1300Un-stressCompressiveTensile nitContactCompr nitNPSTtensileComprNPFig.7 SEM cross-section of an SRAM cell features tensile andcompressive liner in NMOS and PMOS respectively [9].nitride liner is deposited, and this film is also selectivelyetched on the NMOS region. This process can be applied inthe reverse order. Fig. 7 shows the SEM cross-section takenfrom a SRAM cell with the Dual Stress Liner (DSL) process[9]. Compared to non-stressed process, DSL process resultsring oscillator delay with 12 - 24%, dependent on the fan-outloading. IBM PowerPCTM microprocessor Fmax vs. powerimproves 7% with DSL compared to single tensile liner.AMD AthlonTM 64 microprocessor [9] Fmax vs. powerimproves 12 % with DSL compared to non-stressed liner.b) Stress Memorization Technique.Local strain can be applied to the channel through aStress Memorization Technique.In the conventionalfabrication process, Source / Drain Si area and poly gate areamorphized by S/D and extension implantation. In the stressmemorization process, conventional dopant activation spikeanneal is performed after the deposition of a tensile stressorcapping layer, such as nitride (Fig 8) [11-13]. The nitridelayer will subsequently be removed, and the next step issalicidation. The stress effect is transferred from the nitridefilm to the channel during annealing and memorized by there-crystallization of the S/D and poly gate amorphized layers.After active area and gate re-crystallization, the stress insidethe channel is memorized. Since the nitride film is disposable,a very thick capping layer can be used to increase the stresslevel without any process limitation.A 15% of NMOS improvement is demonstratedwhen this modular stressor element is added on top of a etchstop liner, as shown in Fig. 9. The amount of drive currentimprovement is related to the amorphous layer, annealcondition and stress level of the nitride liner.10-710-810-9350450550Ion (PA/Pm)Fig.6 Ion enhancement using stress liner compared to neutralliner (non-stressed process) for a) nMOS and b) PMOS [9].c) Embedded SiGe in S/DBesides the introduction of nitride stressor, a moredirect way to provide strain to channel is filling S/D withSiGe. One suggestion is, epitaxial-grown strained SiGe (eSiGe) is embedded in the S/D regions [14-16,26] or extensionlocation [17] (Fig. 10). When the lattice spacing of this SiGematerial is larger than Si, uniaxial compressive strain isinduced to the channel. Extra integration processes areinserted after spacer formation, such as selective Si recess23-3-3669

Amorphous layerNn AmorphorusBy implantlayerby implantPp p n STITensile NitOxideNn Pp p n STIFig.10 SEM photo of PMOS with e-SiGe structure in S/D [26]Anneal & nit removalNn Pn STIp p Si is crystallized and stressis memorizedFig. 11 PMOS Ion-Ioff for e-SiGe(Courtesy from Intel, 2004 Fig. 8 of [16])1 e -0 51000control1001 e -0 6Tensile Nitstressor101 e -0 71 e -0 80.00610.0070.0080.0090.010.0110.0120 .0 1 30.014600 700 800 900 1000 1100 1200 1300 1400b( M 1 FN1 010 0 08 0 07 M 1 I)nFET IonIon(uA/um)(uA/um)NMOSFig. 9 15% NMOS current improvement with Disposable TensileStressor. Tensile contact etch-stop liner is used.etch in the S/D regions, and selective and insitu-dopedepitaxial SiGe growth. NMOS was protected by cappinglayer to prevent Si recess and SiGe epitaxial growth. Thisstructure creates a large uniaxial compressive stress to thePMOS channel, thereby resulting in significant hole mobilityimprovement. An apparent drive current improvement fromIntel published data is shown in Fig. 11.The compressive stress is mainly dependent on the eSiGe thickness in the S/D, both below and above (raise S/D)the Si surface, and % Ge content in the SiGe. Too high Gecontent may cause defects and yield issue. Moreover, theimprovement will be also degraded for small S/D overhangregions ((distance from poly gate to STI edge), Furtheroptimization in process is necessary to reduce the adverseeffect [15].discussed in Fig. 2. Device drive current can be effectivelymodulated by mechanical built in stresses. Careful selectionon process modular enhancer is necessary to preventenhancement of one type and degradation of another type ofcarriers, and the expense of higher process complexity, costand integration yield. A complete stress model on deviceparameters, especially Ion and Vt, is recommended for anaccurate circuit simulation and verification.Strained Si begins to be implemented in 65 and90nm technologies. Fig. 12 shows the IonN / IonP ratio in therecent three generations. The enhancement of drive currentfrom strained Si process will influence the rise and fall timeof circuit logic stages and hence overall performance.Applying strain enhancement to both N and PMOS can adjustthe ratio back to the appropriate levels, such as DSL (Fig. 7).Moreover, Vt shift associated with shift in bandedges due to channel strain is seen on both NMOS and PMOSImplicationsNeutral N, Neutral P2.42.2Tens N, Neut P2.0Tens N, Compr P1.8Neut N, Compr P1.61.4The electron and hole mobility has differentdependence on the type of uni-axial stresses and this has been6702.6IonN / IonP ratioNMOSIoff(nA/um)(nA/um)nFET IoffFig. 8 Integration process of SMT. a) after S/D implantation;b) oxide and tensile nitride deposition; c) S/D and polydopant activation anneal; d) nitride removal; e) salicidationand subsequent processes.23-3-420 3040 5060 70 8090 100 110 120 130 140technology (nm)Fig.12 IonN / IonP ratio in the recent technologies.

stressPOROPPOROPTensileDisposable Stressor processWithout pMOS selective RIE-0.4-0.4-0.40.010.010.010.1Lpoly (um)Lpoly (um)0.10.1Fig.13 Vt shift due to tensile stress built along the channel.When the technology reaches deep submicronregime and the active area becomes small, the drive currentcan be modulated by the mechanical stress from the STI. Thesource is mainly from STI corners. Longitudinal stress can bemodulated by different (e.g. irregular or asymmetrical) S/Doverhang regions, whereas different lateral stress can beobtained by different channel widths and adjacent active area.Figs. 14-15 investigate the effect of STI proximity to the gateedge in device performance [1,18-20]. PMOS exhibits higherIon at constant Ioff with smaller S/D overhang regions i.e.higher compressive stress from STI in longitudinal direction,whereas NMOS Ion is decreased. When the channel width isreduced, NMOS is less sensitive to the stress effect; on thecontrary, PMOS becomes more sensitive to it. The stressvaries along the channel and hence different channel lengthsreceived different stress effects. STI proximity has minimaleffect on long channel devices (Fig. 14). As the gate lengthreduces, the STI stress effect becomes significant, but reduceswhen the gate length is nominal and short. This suggests thatthe drive current of the nominal devices is controlled by thehalo dose and carrier scattering.From Figs. 14-15, devices always have STI stressproximity effects, especially in small S/D overhang regions.The effects can be reduced by process material but cannot befully eliminated. In general, 50% devices with 2x minimumdistance of gate to STI edge in a product [1]. Therefore,understanding the phenomenon and fundamental behavior canhelp to build and develop an appropriate circuit level devicemodel, rather than using isolated test structure as baselinemodel.From the discussion above, stress engineeringinduced from process integration will affect the Vt and drivecurrent. This will also affect the SRAM design, such as thecell stability (access disturb margin, ADM) and writability(write margin, WRM). ADM is bigger with weak NMOS andstrong PMOS, whereas bigger WRM comes from strongNMOS and weak PMOS. SRAM operation margin (ADM &WRM) vary inversely with device current tolerance. If thedrive current tolerance increases, the operation margins -10x0.045p-0.24x0.045p-0.12x0.04520drive current change (%)000be degraded. Besides stability margin and write margin, readand write performance are also important. Gamma Ratio ofI(passgate) / I(pull-up) and Beta Ratio of I(pull-down) /I(passgate) must be adjusted to meet the operationrequirements. If NMOS current becomes higher, Beta Ratioremains the same and Gamma Ratio increases. The WRM isbetter but ADM will be degraded. On the other hand, ifPMOS current becomes higher, Gamma ratio is reduced. Thecell will be written more slowly. ADM will be better andmore stable. Thus, Vt and current have to be adjusted whenstress engineering is implemented.In addition toconventional Vt-adjustment and halo implantation correctionto modulate the drive and standby current, stress-transfermodular process is important. For example, the stress level inthe nitride fil

Stress Engineering: Process & Results The two main approaches being pursued are strain engineering (from both substrate- and process-induced) and orientation effects. Substrate-induced strain.One of the most effective way to introduce high tensile strain to the channel is to epitaxially grow strained-silicon on a relaxed SiGe layer (Fig 3a).