064 Ds 1v1 - Fujitsu
DatasheetOctober 2004Version 1.1MB86064FME/MS/DAC80/DS/4972Dual 14-bit 1GSa/s DACThe Fujitsu MB86064 is a Dual 14-bit 1GSa/s digital to analogconverter (DAC), delivering exceptional dynamic performance.Each high performance DAC core is capable of generatingmulti-standard, multi-carrier communication transmit signals,suitable for 2, 2.5 and 3G systems. DAC data is input via twohigh-speed LVDS ports. These operate in a pseudo double datarate (DDR) mode, with data latched on both rising and fallingedges of the clock. Alternatively, the device can be configuredas a multiplexed dual-port single DAC. To simplify systemintegration the DAC operates from a clock running at half theDAC conversion rate.PLASTIC PACKAGEEFBGA-120Package Dimensions12 mm x 12 mmFeaturesPIN ASSIGNMENTAC17AB18AA19X A5A5DVDDX A4A4X 11J12J14Y6R10N12L14K15J10All centre pins : D8C9B10A11W3U3P4B1H4DVSSNCNCDVDDX B7R1B7X B5B5P2N3DVSSX B3B3X B1X B9B9T2R3M4W1U1V2V4T4N1M2L3K4DVDDL1G1X B4B4X B2B2DVDDE1DVDDDVSSK2J3J1H2G3F4F2E3D6C7B8A9X B10B10DVSSX B8B8X B6B6C5IndexB6A7A5SERIAL OUTSERIAL CLKAVD18 BAVD18 BVLOW BVREFRREFAVSSCLKINCLKINBVLOW AAVD18 AAVD18 AX RESETTESTCopyright 2004 Fujitsu Microelectronics Europe GmbHP13M13M15D18 Multi-carrier, Multi-standard cellular infrastructure CDMA, W-CDMA, GSM/EDGE, UMTS Wideband communications systems High Direct-IF architectures Arbitrary waveform generation Test equipment Radar, video & display systemsR12N14C19ApplicationsY8SERIAL INSERIAL ENAVSSIOUTB BE21R14X A6A6DVSSX A3A3X A1F20G21F22E23A10DVSSX A8A8H20AB6AA7Y16IOUT BAVD33BGAPAVD18 CLKAVD25AVD33IOUT AIOUTB AAVSSDAC SCANSPAREDVDDDVSSV20U21T22Y10AC5AC7AB8AA9Y18X A10W21V22U23AB10AA11Y12Y14AC9AC11AB12AA13B11X B11DVSSB13X B13X LPCLK INLPCLK INDVSSLPCLK OUTX LPCLK OUTX A13A13X A7A7W23AB14AA15DVSSX A11A11X A9A9DVDDAC13AC15AB16AA17CLK2 OUTAC19B12X B12DVDDB14X B14X CLK2 OUTDVDDCLK1 OUTX CLK1 OUTX A14A14DVDDX A12A12 Dual 14-bit, 1GSa/s Digital to Analog conversion Exceptional dynamic performance 74dBc ACLR for 4 UMTS carriers @ 276MHz direct-IF 100MHz image-free generated bandwidth capability supports UMTS plus digital pre-distortion bandwidth Proprietary performance enhancement features LVDS data interface Register selectable on-chip LVDS termination resistors Fujitsu 4-wire serial control interface Two 16k point programmable on-chip waveform memories Low power 3.3V analog and 1.8V digital operation 750mW single DAC operation power dissipation at 1GSa/s 0.18µm CMOS technology with Triple Well Performance enhanced EFBGA package Industrial temperature range operation (-40 C to 85 C)Not to scale. Viewed from above.ProductionPage 1 of 52Disclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives beforeordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
October 2004 Version 1.1FME/MS/DAC80/DS/4972MB86064 Dual 14-bit 1GSa/s DACContents1Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.1.1 Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.1.2 DAC Core Clocks Programmable Delays . . . . . . . . . . . . . . . 51.1.3 Waveform Memory Module Clock Programmable Delay . . . 61.1.4 Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.1.5 Loop Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.2 DAC Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111.2.1 Data from the LVDS Interface. . . . . . . . . . . . . . . . . . . . . . . 111.2.2 Adjusting the Input Data Timing . . . . . . . . . . . . . . . . . . . . . 121.2.3 Data from the Waveform Memory Module . . . . . . . . . . . . . 131.3 DAC Core Current References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131.4 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141.5 Analog Output Reference Resistor . . . . . . . . . . . . . . . . . . . . . . . . . 141.6 Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141.6.1 Frequency Planning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151.7 Reset and Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.1 Programming a Read/Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 173Waveform Memory Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.1 Dual Port, Interleaved LVDS Data via the WMM . . . . . . . . . . . . . . .3.2 Waveform Memory Module Operation. . . . . . . . . . . . . . . . . . . . . . .3.2.1 Waveform Memory Access via the Serial Interface . . . . . .3.2.2 Writing Data into the Memories. . . . . . . . . . . . . . . . . . . . . .3.3 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2022232426274Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.2 Digital Interface Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.3 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.4 AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5 Dynamic Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.6 Clock Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.7 Serial Interface Timing Specifications . . . . . . . . . . . . . . . . . . . . . . .4.8 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2828282930313233335Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.2 Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.3 Package Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35353639Page 2 of 52ProductionCopyright 2004 Fujitsu Microelectronics Europe GmbHDisclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives beforeordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
October 2004 Version 1.1FME/MS/DAC80/DS/4972MB86064 Dual 14-bit 1GSa/s DAC5.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.1 PCB Power & Ground Plane Splits and Decoupling . . . . . . . . . . . .6.2 Input Clock Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.3 Clock Duty Cycle Optimisation . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.4 Analog Output Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5 Example Setup Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . .6.5.1 Dual DAC, LVDS data, Clock Outputs enabled . . . . . . . . .6.5.2 Single DAC, LVDS data port A, driving DAC A . . . . . . . . .6.5.3 Multiplexed LVDS data into DAC A (A EVEN, B ODD) . .6.5.4 Waveform Memory Module, Different A & B Waveforms . .6.6 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40404243444545454545477Development Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487.1 Using DKUSB-1 in Target Applications . . . . . . . . . . . . . . . . . . . . . . 49Appendix A Default Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50A.1DAC Core Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50A.2Waveform Memory Module Registers . . . . . . . . . . . . . . 51CAUTIONELECTROSTATIC DISCHARGE SENSITIVE DEVICEHigh electrostatic charges can accumulate in the human body and dischargewithout detection. Ensure proper ESD procedures are followed when handling thisdevice.This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields.However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximumrated voltages to this high impedance circuit.Copyright 2004 Fujitsu Microelectronics Europe GmbHProductionPage 3 of 52Disclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives beforeordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
October 2004 Version 1.1FME/MS/DAC80/DS/4972MB86064 Dual 14-bit 1GSa/s DAC1Functional DescriptionThe MB86064 is a high performance Dual 14-bit 1GSa/s DAC. In addition to two DAC cores thedevice features a host of features designed to help both system integration and operation. Afunctional block diagram is shown in Figure 1.Control Interface1.8V LVCMOS4-wire Serial Control Interface 1, 2, 4, 8Clock output 1LVDS 1, 2, 4, 8Clock output 2LVDSRF Clock inpute.g. 500MHzDouble-Edgeclocked(1GSa/s)Loop clock inputLVDSLoop clock outputLVDSWaveform Memory ModulePort A data input14-bit LVDSWaveformWaveformMemoryMemoryAA(16K Points)DAC AAnalog output A(14-bit)(16K Points)WaveformWaveformMemoryMemoryBB(16K Points)(16K Points)DAC BAnalog output B(14-bit)Port B data input14-bit LVDSEFBGA-120Figure 1 MB86064 Functional Block DiagramThe device features a number of proprietary performance enhancement features. For example,analog performance at high frequencies is enhanced by novel current switch and switch driverdesigns which provide constant data-independent switching delay, reducing jitter and distortion.Each DAC core can be regarded as two interleaved DACs running at half rate. The main reason foradopting this approach is that the switch driver inherently includes a multiplex function through its twoinput ports. Compared to a conventional switch driver this allows twice as long to acquire and convert,though because the two paths share current sources they match exactly at low frequencies. In termsof input data, this approach allows easy interfacing to DDR data generating devices.Also integrated into the device is a comprehensive Waveform Memory Module (WMM). Waveformscan be downloaded, via the serial control interface, to drive the DAC cores in the absence of asuitable external data generator.Page 4 of 52ProductionCopyright 2004 Fujitsu Microelectronics Europe GmbHDisclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives beforeordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
October 2004 Version 1.1FME/MS/DAC80/DS/4972MB86064 Dual 14-bit 1GSa/s DAC1.1ClockThe device requires an input clock at half the DAC conversion rate, with sufficient spectral purity tonot impact the target analog output performance. The DAC cores are clocked on both rising andfalling edges of the input clock. This forms an effect of two interleaved converters in each DAC core.A characteristic of this architecture is a suppressed image of the generated signal, appearingreflected about Fs(dac)/4 (Fclk-Fsig). Any duty cycle error in the input clock will exacerbate thisimage. This can be minimised by trimming the differential DC offset at the clock input pins.1.1.1 Input ClockThe input clock should be applied to the MB86064 through input pins CLKIN and CLKINB. The deviceis designed to accept a differential sinusoidal clock. Once on chip and converted to CMOS the clockis distributed to a number of blocks throughout the device. The DAC cores are supplied directly fromthe input clock buffer to ensure minimal degradation to the clock’s purity.en int term0x1C4 - pg11clkout1 clk dlyWaveform Memory ModuleLoop clock inputLVDS0x1C1 - pg7clkout1 cfgpdn outcks0x00 - pg70x1C3 - pg16Clock output 1LVDSloop clk dly0x1C1 - pg9 8Loop clock outputLVDS 4Clock output 2LVDS 2en int term0x1C4 - pg11en ref clken int term0x1C4 - pg70x1C4 - pg11Clock inputRF Nclkout2 clk dly0x1C1 - pg8X RESETclkout2 cfg0x00 - pg7wmm clk dly0x1C1 - pg6dac clk dlydac latch dly0x1B2 - pg60x1B2 - pg6en wmm clk0x1C4 – pg21Clocks toDAC coresClock toWaveform Memory ModuleFigure 2 Clock Distribution1.1.2 DAC Core Clocks Programmable DelaysThe DAC core clocks contain programmable delays. These allow adjustment to the point at whichdata is clocked into the DAC core and when the analog portion of the DAC subsequently latches theCopyright 2004 Fujitsu Microelectronics Europe GmbHProductionPage 5 of 52Disclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives beforeordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
October 2004 Version 1.1FME/MS/DAC80/DS/4972MB86064 Dual 14-bit 1GSa/s DACdata. The delay settings are programmed through register DAC CORE CLOCK DELAYS, bitsdac clk dly and dac latch dly. Based on detailed evaluation by Fujitsu these registers should beprogrammed in accordance with the recommendations given in Table 1.Table 1: DAC Core Register: DAC CORE CLOCK DELAYS [0x1B2]Reg BitsDAC Core Digital Clock Delay(0 - 1.5ns, 100ps steps)Labeldac clk dly32100000::::0100::::1111Reg BitsLabeldac latch dly76540000::::0100::::1111Minimum (* Recommended *)Medium (default)MaximumDAC Core Analog Latch Clock Delay(0 - 1.5ns, 100ps steps)Minimum (* Recommended *)Medium (default)MaximumNote: Bold type indicates default setting. See Appendix A.1.1.3 Waveform Memory Module Clock Programmable DelayA programmable delay stage is provided in the clock path prior to being applied to the WaveformMemory Module. This delay stage is programmed through register SYSTEM CLOCK DELAYS, bitswmm clk dly. See Table 2.Table 2: DAC Core Register: SYSTEM CLOCK DELAYS [0x1C1] (Part 1 of 4)Reg BitsLabelwmm clk dlyPage 6 of 52151413120000::::1111ProductionWaveform Memory Module Clock Delay(0 - 1.5ns, 100ps steps)Minimum (default & recommended)MaximumCopyright 2004 Fujitsu Microelectronics Europe GmbHDisclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives beforeordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
October 2004 Version 1.1FME/MS/DAC80/DS/4972MB86064 Dual 14-bit 1GSa/s DAC1.1.4 Clock OutputsTwo clock outputs, CLK1 OUT and CLK2 OUT, are provided to enable synchronisation of datagenerating devices to the DAC. The reference clock used by the Clock Output block can be disabledif required. See Table 3.Table 3: DAC Core Register: SYSTEM MISC [0x1C4] (Part 1 of 3)SYSTEM MISC(bit)Label0en ref clkFunctionReference clock control0 Enabled (default), 1 DisabledThe output frequency can be individually selected as the input clock divided-by-1, 2, 4 or 8.Configuration is through register WMM CONFIG, bits clkout1 cfg and clkout2 cfg. See Table 4.Table 4: Waveform Memory Module Register: WMM CONFIG [0x00] (Part 1 of 2)Reg BitsLabelDivided Clock Output Configuration321000Clock output 1 clock input (default)01Clock output 1 clock input divided by 210Clock output 1 clock input divided by 411Clock output 1 clock input divided by 8clkout1 cfg00Clock output 2 clock input (default)01Clock output 2 clock input divided by 210Clock output 2 clock input divided by 411Clock output 2 clock input divided by 8clkout2 cfgAlso, programmable delay stages are provided in both CLK1 OUT and CLK2 OUT outputs. Theseclock output delays are programmed through register SYSTEM CLOCK DELAYS clkout1 clk dlyand clkout2 clk dly. See Table 5 and Table 6.Table 5: DAC Core Register: SYSTEM CLOCK DELAYS [0x1C1] (Part 2 of 4)Reg BitsClock Output Delay(0 - 1.5ns, 100ps steps)Labelclkout1 clk dly76540000::::1111Copyright 2004 Fujitsu Microelectronics Europe GmbHMinimum (default)MaximumProductionPage 7 of 52Disclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives beforeordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
October 2004 Version 1.1FME/MS/DAC80/DS/4972MB86064 Dual 14-bit 1GSa/s DACTable 6: DAC Core Register: SYSTEM CLOCK DELAYS [0x1C1] (Part 3 of 4)Reg BitsClock Output Delay(0 - 1.5ns, 100ps steps)Labelclkout2 clk dly32100000::::1111Minimum (default)MaximumThe clock outputs are designed to drive a doubly-terminated LVDS line (7mA drive into abridged 50Ω load) for the best possible signal integrity. 100Ω termination resistors shouldbe connected across the Q and Q signals at each end of the differential line. Enabling theinternal LVDS terminations provides the required source termination on-chip.1.1.5 Loop ClockMaintaining valid clock-to-data timing becomes increasingly difficult at higher clock rates, particularlyover tolerance with device-to-device variations. The MB86064 minimises potential problems throughits DDR data interface and by providing a unique loop-clock facility.Clock(500 MHz)ReferenceClockDLL/PLLClock x2 (1GHz)Increase delay to‘retard’ dataFeedbackClockClock 2(500MHz)LVDS I/ODACFPGAIncrease delay to‘advance’ dataFujitsu MB86064 DACFigure 3 Loop Clock ImplementationThe on-chip ‘loop’ consists of an LVDS input buffer connected to an LVDS output buffer through aprogrammable delay stage. This loop-through, and the associated tracking from/to the dataPage 8 of 52ProductionCopyright 2004 Fujitsu Microelectronics Europe GmbHDisclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives beforeordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
October 2004 Version 1.1FME/MS/DAC80/DS/4972MB86064 Dual 14-bit 1GSa/s DACgenerating device, can be incorporated in the feedback loop of a Delay-Locked Loop (DLL) or PhaseLocked Loop (PLL) clock generator, within the generating device. This enables the system tocompensate for variations in input/output (I/O) and propagation delays in both the data generatingdevice and the DAC. PCB and/or cable propagation delays within the loop are also compensated forbut these are not expected to exhibit significant variation between systems. It is the I/O & on-chipdelays that will dominate.It is important to make sure that the Clock Output frequency is within the specification ofthe DLL/PLL. If it is too high an appropriate divided clock output should be programmed asdetailed in Table 7.With the loop clock implemented as illustrated in Figure 3, increasing the Clock Output delay delaysthe data arriving at the DAC relative to the DAC input clock. By contrast increasing the Loop Clockdelay, within the feedback loop of the DLL/PLL, advances the relative timing.It is important not to adjust both delays simultaneously
image. This can be minimised by trimming the differential DC offset at the clock input pins. 1.1.1 Input Clock The input clock should be applied to the MB86064 through input pins CLKIN and CLKINB. The device is designed to accept a differential sinusoidal clock. Once on chip and converted to CMOS the clock
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