IEEE Standard VHDL Language Reference Manual - VHDL Language Reference .
IEEE Std 1076, 2000 Edition(Incorporates IEEE Std 1076-1993and IEEE Std 1076a-2000)IEEE Standard VHDLLanguage Reference ManualCosponsorsDesign Automation Standards Committee (DASC)of theIEEE Computer SocietyandAutomatic Test Program Generation Subcommitteeof theIEEE Standards Coordinating Committee 20 (SCC 20)Approved 30 January 2000IEEE-SA Standards BoardAbstract: VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notationintended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, andprocurement of hardware. Its primary audiences are the implementors of tools supporting the language and the advanced users of the language.Keywords: computer languages, electronic systems, hardware, hardware design, VHDLThe Institute of Electrical and Electronics Engineers, Inc.3 Park Avenue, New York, NY 10016-5997, USACopyright 2000 by the Institute of Electrical and Electronics Engineers, Inc.All rights reserved. Published 29 December 2000. Printed in the United States of America.Print:PDF:ISBN 0-7381-1948-2ISBN 0-7381-1949-0SH94817SS94817No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the priorwritten permission of the publisher.
IEEE Standards documents are developed within the IEEE Societies and the Standards Coordinating Committees of the IEEE Standards Association (IEEE-SA) Standards Board. Members of the committees servevoluntarily and without compensation. They are not necessarily members of the Institute. The standardsdeveloped within IEEE represent a consensus of the broad expertise on the subject within the Institute aswell as those activities outside of IEEE that have expressed an interest in participating in the development ofthe standard.Use of an IEEE Standard is wholly voluntary. The existence of an IEEE Standard does not imply that thereare no other ways to produce, test, measure, purchase, market, or provide other goods and services related tothe scope of the IEEE Standard. Furthermore, the viewpoint expressed at the time a standard is approved andissued is subject to change brought about through developments in the state of the art and commentsreceived from users of the standard. Every IEEE Standard is subjected to review at least every five years forrevision or reaffirmation. When a document is more than five years old and has not been reaffirmed, it is reasonable to conclude that its contents, although still of some value, do not wholly reflect the present state ofthe art. Users are cautioned to check to determine that they have the latest edition of any IEEE Standard.Comments for revision of IEEE Standards are welcome from any interested party, regardless of membershipaffiliation with IEEE. Suggestions for changes in documents should be in the form of a proposed change oftext, together with appropriate supporting comments.Interpretations: Occasionally questions may arise regarding the meaning of portions of standards as theyrelate to specific applications. When the need for interpretations is brought to the attention of IEEE, theInstitute will initiate action to prepare appropriate responses. Since IEEE Standards represent a consensus ofall concerned interests, it is important to ensure that any interpretation has also received the concurrence of abalance of interests. For this reason, IEEE and the members of its societies and Standards CoordinatingCommittees are not able to provide an instant response to interpretation requests except in those cases wherethe matter has previously received formal consideration.Comments on standards and requests for interpretations should be addressed to:Secretary, IEEE-SA Standards Board445 Hoes LaneP.O. Box 1331Piscataway, NJ 08855-1331USANote: Attention is called to the possibility that implementation of this standard mayrequire use of subject matter covered by patent rights. By publication of this standard,no position is taken with respect to the existence or validity of any patent rights inconnection therewith. The IEEE shall not be responsible for identifying patents forwhich a license may be required by an IEEE standard or for conducting inquiries intothe legal validity or scope of those patents that are brought to its attention.IEEE is the sole entity that may authorize the use of certification marks, trademarks, or other designations toindicate compliance with the materials set forth herein.Authorization to photocopy portions of any individual standard for internal or personal use is granted by theInstitute of Electrical and Electronics Engineers, Inc., provided that the appropriate fee is paid to CopyrightClearance Center. To arrange for payment of licensing fee, please contact Copyright Clearance Center,Customer Service, 222 Rosewood Drive, Danvers, MA 01923 USA; (978) 750-8400. Permission to photocopy portions of any individual standard for educational classroom use can also be obtained through theCopyright Clearance Center.
Introduction(This introduction is not part of IEEE Std 1076, 2000 Edition, IEEE Standards VHDL Language Reference Manual.)The VHSIC Hardware Description Language (VHDL) is a formal notation intended for use in all phases ofthe creation of electronic systems. Because it is both machine readable and human readable, it supports thedevelopment, verification, synthesis, and testing of hardware designs; the communication of hardwaredesign data; and the maintenance, modification, and procurement of hardware.This document specifies IEEE Std 1076, 2000 Edition, which incorporates IEEE Std 1076-1993 and IEEEStd 1076a-2000.ParticipantsThe following individuals participated in the development of this standard:Stephen A. Bailey, ChairPeter J. AshendenDavid L. BartonVictor BermanAlain FonkouaAndrew GuylerJohn HillawiSerge MaginotPaul J. MenchiniJean MermetRob NewshutzWilliam R. PaulsenGregory D. PetersonJacques RouillardRon WernerJohn WillisPhil WilseyAlex ZamfirescuThe following members of the balloting committee voted on this standard:Peter J. AshendenStephen A. BaileyDavid L. BartonVictor BermanJ. BhaskerDominique BorrioneTodd P. CarpenterAllen DeweyDouglas D. DunlopWayne P. FischerRita A. GloverKenji GotoBrian S. GriffinAndrew GuylerM. M. Kamal HashmiCopyright 2000 IEEE. All rights reserved.Rich HatcherCarl E. HeinJohn HillawiJohn HinesOsamu KaratsuJake KarrfaltMichael D. McKinneyPaul J. MenchiniJohn T. MontagueGabe MorettiGerald MusgraveZainalabedin NavabiKevin O’BrienSerafin OlcozVincent OliveGregory D. PetersonMarkus PfaffSteffen RochelJacques RouillardQuentin G. SchmiererSteven E. SchulzMoe ShahdadCharles F. ShelorHiroshi ShinkaiJoseph J. StancoAtsushi TakaharaDavid TesterPeter TrajmarJ. Richard WegerJohn Willisiii
When the IEEE-SA Standards Board approved this standard on 30 January 2000, it had the followingmembership:Richard J. Holleman, ChairDonald N. Heirman, Vice ChairJudith Gorman, SecretarySatish K. AggarwalDennis BodsonMark D. BowmanJames T. CarloGary R. EngmannHarold E. EpsteinJay Forster*Ruben D. GarzonLouis-François PauRonald C. PetersenGerald H. PetersonJohn B. PoseyGary S. RobinsonAkio TojoHans E. WeinrichDonald W. ZipseJames H. GurneyLowell G. JohnsonRobert J. KennellyE. G. “Al” KienerJoseph L. Koepfinger*L. Bruce McClungDaleep C. MohlaRobert F. Munzner*Member EmeritusAlso included is the following nonvoting IEEE-SA Standards Board liaison:Robert E. HebnerAndrew D. IckowiczIEEE Standards Project EditorivCopyright 2000 IEEE. All rights reserved.
Contents0.Overview of this standard . 10.1 Intent and scope of this standard. 10.2 Structure and terminology of this standard. 10.2.1 Syntactic description. 20.2.2 Semantic description . 30.2.3 Front matter, examples, notes, references, and annexes . 31.Design entities and configurations. 51.1 Entity declarations . 51.1.1 Entity header . 51.1.1.1 Generics . 61.1.1.2 Ports . 71.1.2 Entity declarative part . 81.1.3 Entity statement part . 91.2 Architecture bodies . 91.2.1 Architecture declarative part . 101.2.2 Architecture statement part . 101.3 Configuration declarations. 121.3.1 Block configuration . 131.3.2 Component configuration . 152.Subprograms and packages. 192.1 Subprogram declarations . 192.1.1 Formal parameters . 202.1.1.1 Constant and variable parameters . 202.1.1.2 Signal parameter . 212.1.1.3 File parameters . 222.2 Subprogram bodies . 222.3 Subprogram overloading. 252.3.1 Operator overloading . 262.3.2 Signatures . 262.4 Resolution functions . 272.5 Package declarations. 282.6 Package bodies. 292.7 Conformance rules . 313.Types. 333.1 Scalar types . 343.1.1 Enumeration types . 343.1.1.1 Predefined enumeration types . 353.1.2 Integer types . 363.1.2.1 Predefined integer types . 363.1.3 Physical types . 363.1.3.1 Predefined physical types . 383.1.4 Floating point types . 393.1.4.1 Predefined floating point types . 403.2 Composite types. 40Copyright 2000 IEEE. All rights reserved.v
3.2.1 Array types . 403.2.1.1 Index constraints and discrete ranges . 423.2.1.2 Predefined array types . 443.2.2 Record types . 443.3 Access types. 453.3.1 Incomplete type declarations . 463.3.2 Allocation and deallocation of objects . 473.4 File types. 473.4.1 File operations . 483.5 Protected types . 503.5.1 Protected type declarations . 503.5.2 Protected type bodies . 514.Declarations . 554.1 Type declarations . 554.2 Subtype declarations . 564.3 Objects . 574.3.1 Object declarations . 584.3.1.1 Constant declarations . 584.3.1.2 Signal declarations . 594.3.1.3 Variable declarations . 604.3.1.4 File declarations . 624.3.2 Interface declarations . 634.3.2.1 Interface lists . 654.3.2.2 Association lists . 664.3.3 Alias declarations . 684.3.3.1 Object aliases . 694.3.3.2 Nonobject aliases . 704.4 Attribute declarations. 714.5 Component declarations. 724.6 Group template declarations . 724.7 Group declarations . 735.Specifications. 755.1 Attribute specification. 755.2 Configuration specification. 775.2.1 Binding indication . 785.2.1.1 Entity aspect . 805.2.1.2 Generic map and port map aspects . 815.2.2 Default binding indication . 835.3 Disconnection specification . 846.Names . 876.16.26.36.46.56.6viNames . 87Simple names . 88Selected names. 89Indexed names . 91Slice names . 92Attribute names. 92Copyright 2000 IEEE. All rights reserved.
7.Expressions . 957.1 Rules for expressions . 957.2 Operators. 967.2.1 Logical operators . 967.2.2 Relational operators . 977.2.3 Shift operators . 987.2.4 Adding operators . 1007.2.5 Sign operators . 1027.2.6 Multiplying operators . 1027.2.7 Miscellaneous operators . 1047.3 Operands . 1047.3.1 Literals . 1057.3.2 Aggregates . 1067.3.2.1 Record aggregates . 1067.3.2.2 Array aggregates . 1077.3.3 Function calls . 1087.3.4 Qualified expressions . 1087.3.5 Type conversions . 1097.3.6 Allocators . 1107.4 Static expressions. 1117.4.1 Locally static primaries . 1117.4.2 Globally static primaries . 1127.5 Universal expressions . 1138.Sequential statements. 1158.1 Wait statement . 1158.2 Assertion statement. 1178.3 Report statement . 1188.4 Signal assignment statement . 1188.4.1 Updating a projected output waveform . 1208.5 Variable assignment statement . 1238.5.1 Array variable assignments. 1248.6 Procedure call statement . 1248.7 If statement. 1258.8 Case statement . 1258.9 Loop statement. 1268.10 Next statement . 1278.11 Exit statement. 1278.12 Return statement . 1288.13 Null statement . 1289.Concurrent statements. 1299.1 Block statement. 1299.2 Process statement . 1309.3 Concurrent procedure call statements. 1319.4 Concurrent assertion statements . 1329.5 Concurrent signal assignment statements . 1339.5.1 Conditional signal assignments . 1359.5.2 Selected signal assignments . 1379.6 Component instantiation statements . 1389.6.1 Instantiation of a component . 139Copyright 2000 IEEE. All rights reserved.vii
9.6.2 Instantiation of a design entity . 1419.7 Generate statements . 14410.Scope and visibility. 14510.1 Declarative region. 14510.2 Scope of declarations . 14510.3 Visibility . 14610.4 Use clauses. 15010.5 The context of overload resolution . 15011.Design units and their analysis . 15311.1 Design units . 15311.2 Design libraries . 15311.3 Context clauses . 15411.4 Order of analysis . 15512.Elaboration and execution. 15712.1 Elaboration of a design hierarchy . 15712.2 Elaboration of a block header . 15912.2.1 The generic clause . 15912.2.2 The generic m
Language Reference Manual Cosponsors Design Automation Standards Committee (DASC) of the IEEE Computer Society and Automatic Test Program Generation Subcommittee of the IEEE Standards Coordinating Committee 20 (SCC 20) Approved 30 January 2000 IEEE-SA Standards Board Abstract: VHSIC Hardware Description Language (VHDL) is defined. VHDL is a .
The VHDL Golden Reference Guide is a compact quick reference guide to the VHDL language, its syntax, semantics, synthesis and application to hardware design. The VHDL Golden Reference Guide is not intended as a replacement for the IEEE Standard VHDL Language Reference Manual. Unlike that document, the Golden Reference guide does not offer a
IEEE 3 Park Avenue New York, NY 10016-5997 USA 28 December 2012 IEEE Power and Energy Society IEEE Std 81 -2012 (Revision of IEEE Std 81-1983) Authorized licensed use limited to: Australian National University. Downloaded on July 27,2018 at 14:57:43 UTC from IEEE Xplore. Restrictions apply.File Size: 2MBPage Count: 86Explore furtherIEEE 81-2012 - IEEE Guide for Measuring Earth Resistivity .standards.ieee.org81-2012 - IEEE Guide for Measuring Earth Resistivity .ieeexplore.ieee.orgAn Overview Of The IEEE Standard 81 Fall-Of-Potential .www.agiusa.com(PDF) IEEE Std 80-2000 IEEE Guide for Safety in AC .www.academia.eduTesting and Evaluation of Grounding . - IEEE Web Hostingwww.ewh.ieee.orgRecommended to you b
IEEE Standard VHDL Language Reference Manual IEEE 3 Park Avenue New York, NY 10016-5997, USA 26 January 2009 IEEE Computer Society Sponsored by the Design Automation Standards Committee 1076 TM Authorized licensed use limited to: Milwaukee School of Engineering. Downloaded on January 26,2018 at 14:42:56 UTC from IEEE Xplore. Restrictions apply.
Dec 29, 2000 · the standard. Use of an IEEE Standard is wholly voluntary. The existence of an IEEE Standard does not imply that there are no other ways to produce, test, measure, purchase, market, or provide other goods and services related to the scope of the IEEE Standard. Furthermore, the viewpoint expresse
effort to get a much better Verilog standard in IEEE Std 1364-2001. Objective of the IEEE Std 1364-2001 effort The starting point for the IEEE 1364 Working Group for this standard was the feedback received from the IEEE Std 1364-1995 users worldwide. It was clear from the feedback that users wanted improvements in all aspects of the language.File Size: 2MBPage Count: 791Explore furtherIEEE Standard for Verilog Hardware Description Languagestaff.ustc.edu.cn/ songch/download/I IEEE Std 1800 -2012 (Revision of IEEE Std 1800-2009 .www.ece.uah.edu/ gaede/cpe526/20 IEEE Standard for SystemVerilog— Unified Hardware Design .www.fis.agh.edu.pl/ skoczen/hdl/iee Recommended to you b
VHDL Retrospective zVHDL is an IEEE and ANSI standard for describing digital systems zCreated in 1981 for the DoD VHSIC program - First version developed by IBM, TI, and Intermetric - First release in 1985 - Standardized in 1987 and revised several times thereafter zStandard 1076, 1076.1 (VHDL-AMS), 1076.2, 1076.3 zStandard 1164, VHDL-2006 - Inherits many characteristics of ADA: Strong .
VHDL is a description language for digital electronic circuits that is used in di erent levels of abstraction. The VHDL acronym stands for VHSIC (Very High Spdee Integrated Circuits) Hardware Description Language . This means that VHDL can be used to accelerate the design process.
‘Stars’ can allow a business to be a market leader ‘Problem Child’ products give businesses opportunity to invest ‘Dogs’ should be divested Increased profits can ari se f rom selling different products Newer products can replace thos e at the end of the life cycle A range of pro ducts increases brand awareness Easier to launch new products with larg e existing portfolio 5 Award 1 .
