Designing Digital Circuits Using VHDL
Designing DigitalCircuits Using VHDL partial draftJanuary 2012Jonathan Turner
Jonathan Turner1. Getting StartedLet’s start with the basics. Signal assignments are the most commonelement of a VHDL circuit specification. Here's an example.A (B and C) or (not D);Here, A, B, C and D are names of VHDL signals; is the signal assignmentoperator and the keywords and, or and not are the familiar logicaloperators. The parentheses are used to determine the order of operations(in this case, they are not strictly necessary, but do help make the meaningmore clear) and the semicolon terminates the assignment. This assignmentcan be implemented by the combinational circuit shown below.Any logic circuit made up of AND gates, OR gates and inverters in whichthere are no feedback paths is a combinational circuit (a feedback path is acircuit path that leads from a gate output back to an input of the samegate). Every VHDL assignment corresponds to a combinational circuit,and any combinational circuit can be implemented using one or moreVHDL assignments. The specific circuit shown above is only one possibleimplementation of the given signal assignment. Any logically equivalentcircuit is also an acceptable implementation (when we say logicallyequivalent circuit, we mean any circuit that produces the same outputvalue as the above circuit for every set of input values). The meaning of the5
Designing Digital Circuits Using VHDL given assignment is any circuit that is logically equivalent to the oneshown above.The following pair of signal assignments specifies one bit position of ann bit adder.S A xor B xor Ci;Co (A and B) or ((A xor B) and Ci);Here, A and B represent corresponding bits of the two binary numbersbeing added together and Ci represents the carry into this bit position. Sis the sum for this bit position and Co is the carry out of this bit position.The xor keyword represents the exclusive-or operator. For anyexpressions X and Y, X xor Y is equivalent to(X and (not Y)) or ((not X) and Y)We note that no parentheses are required in the assignment to S since theexclusive-or operator is associative. This pair of assignments could beimplemented by two separate circuits that happen to share the sameinputs, but the circuit shown below provides a more efficientimplementation, since it uses the first exclusive-or gate to produce both ofthe output signals.The signal assignments are only one part of a VHDL circuit specification.To completely define a circuit, we must also specify its inputs andoutputs. As an example, here is a complete specification of the full addercircuit.6
Jonathan Turner-- Full adder.-- Produces sum bit (S) and carry-out (Co),-- given data inputs (A,B) and carry-in (Ci).entity fullAdder is port(A, B, Ci: in std logic;S, out: out std logic);end fullAdder;architecture faArch of fullAdder isbeginS A xor B xor Ci;Co (A and B) or ((A xor B) and Ci);end faArch;The first three lines are a comment describing the circuit. In general, a pairof dashes introduces a comment, which continues to the end of the line.Comments don’t affect the meaning of the specification, but are essentialfor making it readable by other people. It’s a good idea to use commentsto explain the inputs and outputs of your circuits, document what yourcircuits do and how they work. Get in the habit of documenting all yourcode.The next few lines are the entity declaration for our full adder circuit.The entity declaration defines the name of the circuit (fullAdder), itsinputs and outputs and their types (std logic). The inputs and outputsare specified in a port list. Successive elements of the port list are separatedby semicolons (note that there is no semicolon following the last element).The last five lines above, constitute the architecture specification, whichincludes two signal assignments. VHDL permits you to have multiplearchitectures for the same entity, hence the architecture has its own label,separate from the entity name. Note that the architecture name alsoappears in the statement that ends the architecture specification.7
Designing Digital Circuits Using VHDL It's important to understand the distinction between the entitydeclaration and the architecture. The entity declaration defines thecircuit’s external interface and the architecture defines its internalimplementation. In a block diagram or abridged schematic, we often showa portion of a larger circuit as a block with labeled inputs and outputs, asillustrated below for the fullAdder.This corresponds directly to the entity declaration. When we supplementsuch a diagram, by filling in the block with an appropriate schematic, weare effectively specifying its architecture.We often find it convenient to define internal signals that are used in otherassignments, but are not outputs of the circuit we are specifying. Forexample, we might specify the full adder using the following assignments.generate A and B;propagate A xor B;S propagate xor Ci;Co generate or (propagate and Ci);This specifies a circuit that is logically equivalent to the previous one.Before we can use these internal signals, we must declare them. Here’s amodified version of the architecture that includes the necessarydeclarations.8
Jonathan Turnerarchitecture faArch2 of fullAdder issignal generate, propagate: std logic;begingenerate A and B;propagate A xor B;S propagate xor Ci;Co generate or (propagate and Ci);end faArch2;This example provides a good illustration of the difference betweenVHDL and conventional programming languages. Suppose that we wrotethe assignments as shown below.S propagate xor Ci;Co generate or (propagate and Ci);generate A and B;propagate A xor B;If these were assignments in a conventional programming language thisversion would not mean the same thing as the original version. Indeed, itmight trigger an error message since propagate and generate arebeing used before they have been assigned values. However, in VHDLthis version has exactly the same meaning, as the original because theyboth specify the same circuit. The order in which the statements appearmakes no difference.VHDL also supports composite signals or signal vectors which allowseveral simple signals to be treated as a unit. For example, if A and B areboth signal vectors that represent the component signals A0, A1, A2 andB0, B1, B2 the assignment A B; is equivalent to the three simpleassignmentsA(0) B(0); A(1) B(1); A(2) B(2);If C is a similar signal vector, the assignment A B and C; is equivalentto9
Designing Digital Circuits Using VHDL A(0) B(0) and C(0);A(1) B(1) and C(1);A(2) B(2) and C(2);We can also refer to parts of signal vectors. So, the assignmentA(0 to 2) B(3 downto 2) & C(2);is equivalent toA(0) B(3); A(1) B(2); A(2) C(2);Here the ampersand (&) is a signal concatenation operator that is used tocombine signals or signal vectors to form longer signal vectors. Thedirection indicators, to and downto, determine which end of a range ofsignals is considered the left end and which is the right end. Signalassignments use this notion of left-to-right ordering to determine whichsignals of the right-hand side vector are paired with signals on the lefthand side.The right-hand side of a signal assignment may also include constantvalues, and there are several ways to specify constants. Single bit valuesare enclosed in single quotes ('0' or '1'). Multi-bit signals are written asstrings enclosed by double quotes ("001" or "11001"). For multi-bitsignals with more than a few bits, it's convenient to use hexadecimalconstants. The constant x"c4" specifies the same value as "11000100".VHDL allows constants to be specified in more general ways as well. Forexample, if A is an 8 bit signal vector, then the assignmentA (7 6 '1', 5 downto 3 '0', others '1');is equivalent to A "11000111". The special caseA (others '0');provides a convenient way to specify that all bits of A are 0. This works nomatter how many bits A actually has.10
Jonathan Turner2. Warming UpIn Chapter 1, we saw how we could use VHDL to design some verysimple combinational circuits. In this chapter, we’ll introduce someadditional features of the language and see how they can be used todesign more complex circuits. As an example, we’ll use a circuit thatimplements a very simple arithmetic calculator. The circuit has an 8 bitdata input called dIn, an 8 bit data output called result and controlinputs clear, load and add. It has an internal storage register that canstore an 8 bit value. The result output is the value stored in this register.When the clear input is asserted, the stored value is cleared, when theload input is asserted the value of dIn is stored, and when the add inputis asserted, the value of dIn is added to the stored value. The entitydeclaration for the circuit is shown below.entity calculator is port (clk: in std logic;clear, load, add: in std logic;dIn: in std logic vector(7 downto 0);result: out std logic vector(7 downto 0));end calculator;The clk input controls when the circuit responds to control inputs. Inparticular, it performs an operation only when the clk input makes a11
Designing Digital Circuits Using VHDL transition from low to high. So here is the architecture of a circuit thatimplements the desired functionality.architecture calcArch of calculator issignal dReg: std logic vector(7 downto 0);beginprocess (clk) beginif rising edge(clk) thenif clear '1' thendReg x"00";elsif load '1' thendReg dIn;elsif add '1' thendReg dReg dIn;end if;end if;end process;result dReg;end calcArch;The storage register dReg is declared at the beginning of the architecturespecification. The process block implements the core functionality of thecircuit. The initial if-statement defines a synchronization condition on theclk signal. All assignments within the scope of the synchronizationcondition take place when there is a low-to-high transition on the clksignal. What this means, in terms of the circuit implementation, is that thesignals that are assigned values within the scope of the synchronizationcondition must be stored in clocked registers that are triggered by the risingedge of clk. In this case, it means dReg is stored in such a register. Here’sa diagram of a circuit that implements the given VHDL specification.12
Jonathan TurnerThis circuit diagram includes some components that we haven’t seen sofar. The block labeled Adder implements an eight bit binary additionfunction, so its 8 bit output is the sum of its two 8 bit inputs. Thetrapezoidal symbols are 2:1 multiplexors. Each of these has a pair of datainputs labeled 0 and 1, and a data output, on the right. They also have acontrol input at the bottom. The output of a 2:1 multiplexor (or mux, forshort) is the value on one of its two data inputs. In particular, if the controlinput is low, the output is equal to the value on the data input labeled 0,and if the control input is high, the output is equal to the value on the datainput labeled 1. The adder and multiplexor components are combinationalcircuits, so they can be implemented using AND gates, OR gates andinverters with no feedback.The rectangular component at the right of the diagram is a clockedregister made up of positive edge-triggered D flip flops. A flip flop is astorage device capable of storing one bit of information. The clocked D flipflop is the particular type of flip flop that is used most often. It has a datainput and a clock input. The value stored in the flip flop appears as itsoutput. A new value is stored in the flip flop every time the clock makes atransition from low to high. In particular, the value that is present on theD input is stored whenever such a transition occurs. Clock signals likeclk are usually periodic, square wave signals with a fixed frequency. So13
Designing Digital Circuits Using VHDL for example, if clk were a 50 MHz square wave, the calculator circuitcould potentially perform an operation every 20 ns.Considering the block diagram, we can see that on every clocktransition, a value is stored in the register. If the clear signal is high, thisvalue is x00. If the clear signal is low, but the load signal is high, thevalue stored comes from the data input. If clear and load are low, butadd is high, the stored value is the sum of the “old” value and the datainput. Finally, if all the control signals are low, the register is loaded withits old value (so, it doesn’t change). Note how this reflects the logicexpressed in the VHDL specification. Also notice how various elements ofthe circuit correspond to the VHDL. In particular, because the dReg signalis assigned within the scope of the synchronization condition, a register ofclocked flip flops is included in the circuit to hold its value. The inner ifthen-elsif-elsif construct in the VHDL specification is implemented usingthe sequence of multiplexors in the circuit diagram. Each conditiondetermines the value of the control input of one of the multiplexors.There are a couple more details worth noting. First, observe that theprocess statement includes the clk signal in parentheses. In general, theprocess statement can have a list of signals associated with it. This iscalled the sensitivity list. By placing a signal in the sensitivity list, we aremaking an assertion that the signals that are controlled by the processonly change when one of the signals in the sensitivity list changes. In thiscase, because all assignments in the process fall within the scope of thesynchronization condition, the signals controlled by the process can onlychange when clk changes.Second, notice that the result output is assigned a value outside theprocess block. We could have placed this assignment inside the processblock so long as it was placed outside the scope of the synchronizationcondition. If we had placed it inside the scope of the synchronizationcondition, the implementation would have included an additional registerfor result, connected in pipeline fashion to the register for dReg. Thiswould effectively delay the appearance of the result by one clock tick,which is not what we want in this case.14
Jonathan TurnerProcesses can also be used to define purely combinational circuits. Forexample, we could re-write the full-adder circuit from the previouschapter as shown below.architecture a1 of fullAdder isbeginprocess (A, B, Cin) beginCout A;if A / B thenS not Cin;Cout Cin;elseS Cin;end if;end process;end;This VHDL specification can be implemented by this circuit.which is logically equivalent to the circuit we saw in the previous chapter.Notice that the process does not include an if-statement with asynchronization condition. This means that the signals that are specifiedby the process (S and Cout) need not be stored in flip flops. Also noticethat S and Cout are defined for all possible combinations of the inputsignals A, B and Cin. It’s important that this be true for any process thatwe are using to define a combinational circuit. If we do not specify an15
Designing Digital Circuits Using VHDL output for all possible input values, the VHDL language processorassumes that we intended for that output to retain its “old” value for thatundefined set of inputs. For example, suppose we left out the defaultassignment of A to Cout. This would imply that whenever A and B gofrom being unequal to equal, the value of Cout should not change. Thecircuit shown below uses a D-latch to provide the required behavior.A D-latch is a storage element that is similar to a flip flop, but it stores anew value not on the rising clock edge, but anytime the control input (C) ishigh. It useful to think of the D latch as being “transparent” when the Cinput is high (that is, the output equals the input), and it retains its “oldvalue” whenever the C input is low. Notice that the symbol for the D-latchwhile similar to that the D flip flop is slightly different, since the clockinput of the D flip flop is labeled with ‘ C’, where the ‘ ’ indicates thatthe input is sensitive to the clock edge.It’s easy, when writing a process to implement a combinational circuit,to accidentally leave out an assignment that’s needed to guarantee that theprocess’ output signals are defined for all combinations of its inputsignals. When this happens, a circuit synthesizer will infer a latch toproduce the specified behavior. If this is not what we want, the result willbe a circuit that behaves differently from how we intended. This can bebaffling when we are trying to verify the circuit’s operation. A good wayto avoid this problem is to assign some default value to every output signalof a process, right at the top of the process.This example brings out another point about VHDL that is worthemphasizing. Let’s take another look at the process.16
Jonathan Turnerprocess (A, B, Cin) beginCout A;if A / B thenS not Cin;Cout Cin;elseS Cin;end if;end process;In Chapter 1, we discussed an example in which the relative order ofseveral assignment statements did not have any effect on the meaning ofthe VHDL. However, within a process, the relative order of assignments to thesame signal does matter. So for example, if we moved the assignment Cout A so that it came after the if-then-else, the resulting circuit wouldcause Cout to equal A all the time. This is what we would expect, basedon our experience with ordinary programming languages, but is differentfrom what we might expect, based on our earlier discussion aboutordering of assignments. The crucial distinction is that here we are talkingabout two assignments to the same signal within a process. VHDL treatsthe initial assignment to Cout as a default value to be used under anyconditions where the value of Cout is otherwise unspecified. This leads tobehavior that is similar to what we are used to from ordinaryprogramming languages, but is not quite the same, since here we are stilldefining a circuit, not specifying a sequence of memory storageoperations, as in conventional programming. It’s important to keep this inmind when writing circuit specifications using processes.There is one last aspect of this example that merits a closer look, andthat is the sensitivity list. Notice that in this case, the sensitivity listincludes the signals A, B and Cin. These signals are included, because achange to any one of these signals can cause the outputs of the process (Sand Cout) to change. When using a process to define a combinational17
Designing Digital Circuits Using VHDL circuit, it’s best to include all signals that appear in conditionalexpressions or on the right side of assignments, in the sensitivity list.Now, you might be wondering, what’s the point of the sensitivity list, andthat’s a reasonable question. The sensitivity list is included in thelanguage primarily as an aid to simulation and modeling tools. If a circuitsimulator knows that the only signals that can affect the outputs of aprocess are the ones included in its sensitivity list, it only needs to updateits simulation state for the process when one of those signals changes.Unfortunately, if one inadvertently neglects to include a signal in thesensitivity list, this can cause a circuit simulation to behave differentlythan we expect. So, one of the first things to do when a simulation of acombinational process is behaving strangely, is to double-check thesensitivity list and make sure that every signal that can affect the process’outputs is included.Before concluding this chapter, there are a few more things it’simportant to point out about processes. First, an architecture may containmore than one process, but there is an important restriction on howdifferent processes interact. In particular, each signal that is definedwithin an architecture should be specified (assigned a value) by only oneprocess. If two different processes had assignments to the same signal, theresulting circuit
circuit path that leads from a gate output back to an input of the same gate). Every VHDL assignment corresponds to a combinational circuit, and any combinational circuit can be implemented using one or more VHDL assignments. The specific circuit shown above is only one possible implementation of the given signal assignment. Any logically .
exposed to VHDL modeling of digital circuits, they learn the concepts and non-VHDL design of the digital circuits. Additionally, they spend two hours (or more) per week in the lab to go over the lab assignments and do the lab assignments in which VHDL and FPGAs are used from week 3 through week 10.
VHDL/PLD design methodology VHDL is a programming language for designing and modeling digital hardware systems. Using VHDL with electronic design automation (EDA) software tools and user programmable logic devices (PLDs), we can quickly design, verify, and implement a digital system. W
VHDL is a description language for digital electronic circuits that is used in di erent levels of abstraction. The VHDL acronym stands for VHSIC (Very High Spdee Integrated Circuits) Hardware Description Language . This means that VHDL can be used to accelerate the design process.
The VHDL Golden Reference Guide is a compact quick reference guide to the VHDL language, its syntax, semantics, synthesis and application to hardware design. The VHDL Golden Reference Guide is not intended as a replacement for the IEEE Standard VHDL Language Reference Manual. Unlike that document, the Golden Reference guide does not offer a
VHDL Retrospective zVHDL is an IEEE and ANSI standard for describing digital systems zCreated in 1981 for the DoD VHSIC program - First version developed by IBM, TI, and Intermetric - First release in 1985 - Standardized in 1987 and revised several times thereafter zStandard 1076, 1076.1 (VHDL-AMS), 1076.2, 1076.3 zStandard 1164, VHDL-2006 - Inherits many characteristics of ADA: Strong .
I CIRCUIT DESIGN 1 Introduction 1.1 About VHDL 1.2 Design Flow 1.3 EDA Tools 1.4 Translation of VHDL Code into a Circuit 1.5 Design Examples 2 Code Structure 2.1 Fundamental VHDL Units 2.2 LIBRARY Declarations 2.3 ENTITY 2.4 ARCHITECTURE 2.5 Introductory Examples 2.6 Problems 3 Data Types 3.1 Pre-Defined Data Types
Language Reference Manual Cosponsors Design Automation Standards Committee (DASC) of the IEEE Computer Society and Automatic Test Program Generation Subcommittee of the IEEE Standards Coordinating Committee 20 (SCC 20) Approved 30 January 2000 IEEE-SA Standards Board Abstract: VHSIC Hardware Description Language (VHDL) is defined. VHDL is a .
reading comprehension. DIRECTIONS. this practice test contains one reading selection with two multiple-choice questions and one open-response question. Mark your answers to these questions in the spaces provided on page 5 of your practice test answer document. 1. The porcupine is a controversial, yet important, forest creature. Our more prickly encounters with “quill pigs” may be remedied .
