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TED GIGABIT ETHERNET CONTROLLERFOR PCI EXPRESS APPLICATIONSDATASHEET(CONFIDENTIAL: Development Partners Only)Rev. 1.522 July 2010Track ID: JATR-2265-11Realtek Semiconductor Corp.No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, TaiwanTel.: 886-3-578-0211. Fax: 886-3-577-6047www.realtek.com
RTL8111EDatasheetCOPYRIGHT 2010 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by anymeans without the written permission of Realtek Semiconductor Corp.DISCLAIMERRealtek provides this document “as is”, without warranty of any kind. Realtek may make improvementsand/or changes in this document or in the product described in this document at any time. This documentcould include technical inaccuracies or typographical errors.TRADEMARKSRealtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this documentare trademarks/registered trademarks of their respective owners.LICENSEThis product is covered by one or more of the following patents: US5,307,459, US5,434,872,US5,732,094, US6,570,884, US6,115,776, and US6,327,625.USING THIS DOCUMENTThis document is intended for the software engineer’s reference and provides detailed programminginformation.Though every effort has been made to ensure that this document is current and accurate, more informationmay have become available subsequent to the production of this guide.REVISION HISTORYRevision1.01.1Release /182010/06/071.52010/07/22SummaryFirst release.Removed TWSI data.Revised section 6.2.6 Customizable LED Configuration, page 12.Revised Figure 14 Auxiliary Signal Timing, page 32.Revised Table 4 Clock, page 6.Revised section 6.2.6 Customizable LED Configuration, page 12.Revised section 8.5 Environmental Characteristics, page 25.Revised Table 24 Auxiliary Signal Timing Parameters, page 32.Revised Table 19 DC Characteristics, page 25.Added the RTL8111E-VC-GR product number.Revised section 6.9.2 ASF (Alert Standard Format) 2.0 Support, page 20.Added RTL8111E-VB-CG and RTL8111E-VC-CG product numbers.Removed the RTL8111E-VC-GR product number.Revised IEEE802.3az version from Draft 3.0 to Draft 3.2.Integrated Gigabit Ethernet Controller for PCI ExpressiiTrack ID: JATR-2265-11Rev. 1.5
RTL8111EDatasheetTable of Contents1.GENERAL DESCRIPTION .12.FEATURES .33.SYSTEM APPLICATIONS.34.PIN ASSIGNMENTS .44.1.5.PIN 5.10.6.PACKAGE IDENTIFICATION .4POWER MANAGEMENT/ISOLATION .5PCI EXPRESS INTERFACE .5TRANSCEIVER INTERFACE .6CLOCK .6REGULATOR AND REFERENCE .6EEPROM .7LEDS .7SMBUS .8POWER AND GROUND .8GPO PIN .8FUNCTIONAL DESCRIPTION.96.1.PCI EXPRESS BUS INTERFACE.96.1.1. PCI Express Transmitter .96.1.2. PCI Express Receiver .96.2.LED FUNCTIONS .96.2.1. Link Monitor.96.2.2. RX LED .106.2.3. TX LED.106.2.4. TX/RX LED.116.2.5. LINK/ACT LED .116.2.6. Customizable LED Configuration .126.3.PHY TRANSCEIVER .136.3.1. PHY Transmitter.136.3.2. PHY Receiver .136.4.NEXT PAGE .146.5.EEPROM INTERFACE .146.6.POWER MANAGEMENT.156.7.VITAL PRODUCT DATA (VPD).176.8.RECEIVE-SIDE SCALING (RSS) .186.8.1. Receive-Side Scaling (RSS) Initialization .186.8.2. Protocol Offload.196.8.3. RSS Operation .196.9.ALERT STANDARD FORMAT (ASF) .196.9.1. Security-Extensions .196.9.2. ASF (Alert Standard Format) 2.0 Support .206.10.ENERGY EFFICIENT ETHERNET (EEE).227.SWITCHING TE MAXIMUM RATINGS .23RECOMMENDED OPERATING CONDITIONS .23CRYSTAL REQUIREMENTS .24Integrated Gigabit Ethernet Controller for PCI ExpressiiiTrack ID: JATR-2265-11Rev. 1.5
RTL8111EDatasheet8.4.OSCILLATOR REQUIREMENTS .248.5.ENVIRONMENTAL CHARACTERISTICS .258.6.DC CHARACTERISTICS .258.7.AC CHARACTERISTICS .268.7.1. Serial EEPROM Interface Timing .268.8.PCI EXPRESS BUS PARAMETERS .278.8.1. Differential Transmitter Parameters .278.8.2. Differential Receiver Parameters .288.8.3. REFCLK Parameters.288.8.4. Auxiliary Signal Timing Parameters .329.MECHANICAL DIMENSIONS.3310.ORDERING INFORMATION.34Integrated Gigabit Ethernet Controller for PCI ExpressivTrack ID: JATR-2265-11Rev. 1.5
RTL8111EDatasheetList of TablesTABLE 1.TABLE 2.TABLE 3.TABLE 4.TABLE 5.TABLE 6.TABLE 7.TABLE 8.TABLE 9.TABLE 10.TABLE 11.TABLE 12.TABLE 13.TABLE 14.TABLE 15.TABLE 16.TABLE 17.TABLE 18.TABLE 19.TABLE 20.TABLE 21.TABLE 22.TABLE 23.TABLE 24.TABLE 25.POWER MANAGEMENT/ISOLATION .5PCI EXPRESS INTERFACE .5TRANSCEIVER INTERFACE .6CLOCK .6REGULATOR AND REFERENCE .6EEPROM .7LEDS .7SMBUS .8POWER AND GROUND .8GPO PIN .8LED SELECT (IO REGISTER OFFSET 18H 19H).12CUSTOMIZED LEDS .12EEPROM INTERFACE .14ABSOLUTE MAXIMUM RATINGS .23RECOMMENDED OPERATING CONDITIONS .23CRYSTAL REQUIREMENTS .24OSCILLATOR REQUIREMENTS .24ENVIRONMENTAL CHARACTERISTICS .25DC CHARACTERISTICS .25EEPROM ACCESS TIMING PARAMETERS .26DIFFERENTIAL TRANSMITTER PARAMETERS .27DIFFERENTIAL RECEIVER PARAMETERS .28REFCLK PARAMETERS .28AUXILIARY SIGNAL TIMING PARAMETERS.32ORDERING INFORMATION .34List of FiguresFIGURE 1.FIGURE 2.FIGURE 3.FIGURE 4.FIGURE 5.FIGURE 6.FIGURE 7.FIGURE 8.FIGURE 9.FIGURE 10.FIGURE 11.FIGURE 12.FIGURE 13.FIGURE 14.PIN ASSIGNMENTS .4RX LED .10TX LED .10TX/RX LED.11LINK/ACT LED .11SERIAL EEPROM INTERFACE TIMING .26SINGLE-ENDED MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT AND SWING .30SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT .30SINGLE-ENDED MEASUREMENT POINTS FOR RISE AND FALL TIME MATCHING .30DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE AND PERIOD .31DIFFERENTIAL MEASUREMENT POINTS FOR RISE AND FALL TIME .31DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK .31REFERENCE CLOCK SYSTEM MEASUREMENT POINT AND LOADING .32AUXILIARY SIGNAL TIMING .32Integrated Gigabit Ethernet Controller for PCI ExpressvTrack ID: JATR-2265-11Rev. 1.5
RTL8111EDatasheet1. General DescriptionThe Realtek RTL8111E-VB-GR/RTL8111E-VB-CG/RTL8111E-VC-CG Gigabit Ethernet controllercombines a triple-speed IEEE 802.3 compliant Media Access Controller (MAC) with a triple-speedEthernet transceiver, PCI Express bus controller, and embedded memory. With state-of-the-art DSPtechnology and mixed-mode signal technology, the RTL8111E offers high-speed transmission overCAT 5 UTP cable or CAT 3 UTP (10Mbps only) cable. Functions such as Crossover Detection andAuto-Correction, polarity correction, adaptive equalization, cross-talk cancellation, echo cancellation,timing recovery, and error correction are implemented to provide robust transmission and receptioncapability at high speeds.The RTL8111E supports the PCI Express 1.1 bus interface for host communications with powermanagement, and is compliant with the IEEE 802.3u specification for 10/100Mbps Ethernet and the IEEE802.3ab specification for 1000Mbps Ethernet. It also supports an auxiliary power auto-detect function,and will auto-configure related bits of the PCI power management registers in PCI configuration space.The RTL8111E features embedded One-Time-Programmable (OTP) memory to replace the externalEEPROM (93C46/93C56/93C66).Advanced Configuration Power management Interface (ACPI)—power management for modernoperating systems that are capable of Operating System-directed Power Management (OSPM)—issupported to achieve the most efficient power management possible. PCI MSI (Message SignaledInterrupt) and MSI-X are also supported.In addition to the ACPI feature, remote wake-up (including AMD Magic Packet and Microsoft Wake-upframe) is supported in both ACPI and APM (Advanced Power Management) environments. To supportWOL from a deep power down state (e.g., D3cold, i.e., main power is off and only auxiliary exists), theauxiliary power source must be able to provide the needed power for the RTL8111E.The RTL8111E is fully compliant with Microsoft NDIS5, NDIS6 (IPv4, IPv6, TCP, UDP) Checksum andSegmentation Task-offload (Large send and Giant send) features, and supports IEEE 802 IP Layer 2priority encoding and IEEE 802.1Q Virtual bridged Local Area Network (VLAN). The above featurescontribute to lowering CPU utilization, especially benefiting performance when in operation on a networkserver.The RTL8111E supports Receive Side Scaling (RSS) to hash incoming TCP connections andload-balance received data processing across multiple CPUs. RSS improves the number of transactionsper second and number of connections per second, for increased network throughput.Integrated Gigabit Ethernet Controller for PCI Express1Track ID: JATR-2265-11Rev. 1.5
RTL8111EDatasheetAlert Standard Format (ASF 2.0) is also supported to provide system manageability in OS-absentenvironments. The ASF defines remote control and alerting interfaces that serve managed PCs inOS-absent states. The ASF capability can minimize on-site IT maintenance, improve system availability,and allow remote control of power management. The RTL8111E-VC (only) supports ASFEEPROM-Less operation. Refer to the RTL8111E EEPROM-Less App Note for details.The RTL8111E supports Protocol offload. It offloads some of the most common protocols to NIChardware in order to prevent spurious wake up and further reduce power consumption. The RTL8111Ecan offload ARP (IPv4) and NS (IPv6) protocols while in the D3 power saving state.The RTL8111E supports IEEE 802.3az Draft 3.2, also known as Energy Efficient Ethernet (EEE). IEEE802.3az operates with the IEEE 802.3 Media Access Control (MAC) Sublayer to support operation inLow Power Idle mode. When the Ethernet network is in low link utilization, EEE allows systems on bothsides of the link to save power.The device also features inter-connect PCI Express technology. PCI Express is a high-bandwidth,low-pin-count, serial, interconnect technology that offers significant improvements in performance overconventional PCI and also maintains software compatibility with existing PCI infrastructure.The RTL8111E is suitable for multiple market segments and emerging applications, such as desktop,mobile, workstation, server, communications platforms, and embedded applications.Integrated Gigabit Ethernet Controller for PCI Express2Track ID: JATR-2265-11Rev. 1.5
RTL8111EDatasheet2. Features Integrated 10/100/1000 transceiver Serial EEPROM Auto-Negotiation with Next Page capability Transmit/Receive on-chip buffer support Supports PCI Express 1.1 Supports pair swap/polarity/skew correctionSupports power down/link down powersaving Crossover Detection & Auto-Correction Built-in switching regulator Wake-on-LAN and remote wake-up support Supports PCI MSI (Message SignaledInterrupt) and MSI-X Microsoft NDIS5, NDIS6 ChecksumOffload (IPv4, IPv6, TCP, UDP) andSegmentation Task-offload (Large send v1and Large send v2) support Supports quad core Receive-Side Scaling(RSS) Supports Full Duplex flow control(IEEE 802.3x)Supports Alert Standard Format 2.0(ASF2.0) Supports Protocol Offload (ARP & NS) Supports jumbo frame to 9K bytes Supports Customized LEDs Fully compliant with IEEE 802.3,IEEE 802.3u, IEEE 802.3ab Supports 1-Lane 2.5Gbps PCI Express Bus Supports IEEE 802.1P Layer 2 PriorityEncodingSupports hardware ECC (Error CorrectionCode) function Supports IEEE 802.1Q VLAN taggingSupports hardware CRC (CyclicRedundancy Check) function Supports IEEE 802.3az Draft 3.2 (EEE) 48-pin QFN ‘Green’ package Embedded OTP memory can replace theexternal EEPROM 3. System Applications PCI Express Gigabit Ethernet on Motherboard, Notebook, or Embedded systemsIntegrated Gigabit Ethernet Controller for PCI Express3Track ID: JATR-2265-11Rev. 1.5
RTL8111EDatasheet4. Pin AssignmentsFigure 1.Pin Assignments4.1. Package IdentificationGreen package is indicated by a ‘G’ in the location marked ‘T’ in Figure 1. The version is shown in thelocation marked ‘V’.Integrated Gigabit Ethernet Controller for PCI Express4Track ID: JATR-2265-11Rev. 1.5
RTL8111EDatasheet5. Pin DescriptionsThe signal type codes below are used in the following tables:I: InputS/T/S: Sustained Tri-StateO: OutputO/D: Open DrainT/S: Tri-State bi-directional input/output pinP: Power5.1. Power Table 1. Power Management/IsolationPin No DescriptionPower Management Event: Open drain, active low.Used to reactivate the PCI Express slot’s main power rails and reference clocks.28Refer to the reference schematic for strapping pin information.All strapping pins are power-on-latch pins.Isolate Pin: Active low.Used to isolate the RTL8111E from the PCI Express bus. The RTL8111E will not26drive its PCI Express outputs (excluding LANWAKEB) and will not sample itsPCI Express input as long as the Isolate pin is asserted.5.2. PCI Express InterfaceSymbolREFCLK PREFCLK NHSOPHSONHSIPHSINPERSTBCLKREQBTypeIIOOIIPin No192022231718I25O/D16Table 2.DescriptionPCI Express InterfacePCI Express Differential Reference Clock Source: 100MHz 300ppm.PCI Express Transmit Differential Pair.PCI Express Receive Differential Pair.PCI Express Reset Signal: Active low.When the PERSTB is asserted at power-on state, the RTL8111E returns to apre-defined reset state and is ready for initialization and configuration after thede-assertion of the PERSTB.Reference Clock Request Signal.This signal is used by the RTL8111E to request starting of the PCI Expressreference clock.Refer to the reference schematic for strapping pin information.All strapping pins are power-on-latch pins.Integrated Gigabit Ethernet Controller for PCI Express5Track ID: JATR-2265-11Rev. 1.5
RTL8111EDatasheet5.3. Transceiver InterfaceSymbolMDIP0TypeIOPin OIOIO781011Table 3. Transceiver InterfaceDescriptionIn MDI mode, this is the first pair in 1000Base-T, i.e., the BI DA /- pair, and isthe transmit pair in 10Base-T and 100Base-TX.In MDI crossover mode, this pair acts as the BI DB /- pair, and is the receive pairin 10Base-T and 100Base-TX.In MDI mode, this is the second pair in 1000Base-T, i.e., the BI DB /- pair, and isthe receive pair in 10Base-T and 100Base-TX.In MDI crossover mode, this pair acts as the BI DA /- pair, and is the transmitpair in 10Base-T and 100Base-TX.In MDI mode, this is the third pair in 1000Base-T, i.e., the BI DC /- pair.In MDI crossover mode, this pair acts as the BI DD /- pair.In MDI mode, this is the fourth pair in 1000Base-T, i.e., the BI DD /- pair.In MDI crossover mode, this pair acts as the BI DC /- pair.5.4. ClockSymbolCKXTAL1TypeIPin No43CKXTAL2IO44Table 4. ClockDescriptionInput of 25MHz Clock Reference.Input of External Clock Source.Output of 25MHz Clock Reference.5.5. Regulator and ReferenceTable 5. Regulator and ReferenceSymbolTypePin No DescriptionREGOUTO36Switching Regulator 1.05V Output.3.3V: Enable switching regulator.ENSWREGI330V: Disable switching regulator.VDDREGP34, 35Digital 3.3V Power Supply for Switching Regulator.RSETI46Reference. External resistor reference.Note: See section 7, page 22 for switching regulator.Integrated Gigabit Ethernet Controller for PCI Express6Track ID: JATR-2265-11Rev. 1.5
RTL8111EDatasheet5.6. EEPROMSymbolEESKTypeOPin No37EEDIO/I32EEDOI3130EECSOTable 6. EEPROMDescriptionSerial Data Clock.EEDI: Output to serial data input pin of EEPROM.Refer to the reference schematic for strapping pin information.All strapping pins are power-on-latch pins.Input from Serial Data Output Pin of EEPROM.EECS: EEPROM Chip Select.Refer to the reference schematic for strapping pin information.All strapping pins are power-on-latch pins.5.7. LEDsTable 7.SymbolLED0LED1LED3TypeOOOPin 1000LINK1000/ACT1000Note 1: During power down mode, the LED signals are logic high.Note 2: LEDS1-0’s initial value comes from the EEPROM. If there is no EEPROM, the default value of the(LEDS1, LEDS0) (1, 1).When implementing dual color LEDs and EEPROM at the same time:Pin31 and Pin37 of the RTL8111E are shared pins. Follow the RTLRTL8111E reference design (version1.00 or later) to select these 2 pins for a dual-color LED circuit. Otherwise, the RTLRTL8111E EEPROMmay not function.Integrated Gigabit Ethernet Controller for PCI Express7Track ID: JATR-2265-11Rev. 1.5
RTL8111EDatasheet5.8. SMBusSymbolTypePin NoSMBCLKO/D14SMBDATAO/D15SMBALERTO/D38Table 8. SMBusDescriptionSMBus Clock.Refer to the reference schematic for strapping pin information.All strapping pins are power-on-latch pins.SMBus Data.Refer to the reference schematic for strapping pin information.All strapping pins are power-on-latch pins.SMBus Alert.Refer to the reference schematic for strapping pin information.All strapping pins are power-on-latch pins.5.9. Power and GroundTable 9. Power and GroundSymbolTypePin NoDescriptionDVDD33P27, 39Digital 3.3V Power S
Alert Standard Format (ASF 2.0) is also supported to provide system manageability in OS-absent environments. The ASF defines remote control and alerting interfaces that serve managed PCs in OS-absent states. The ASF capability can minimize on-site IT maintenance, improve system availability, and allow remo
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The asset management plan also includes: clear links to (or incorporates) the organisation’s capital/procurement plan long-term (5-10 years) needs based on the direction of travel for the organisation the gap between the current and future asset base, and the way this will be addressed in the form of asset acquisitions and disposals, by each asset category plans for .
