Testing MIPI Interfaces With The R&S RTO Oscilloscope
General purpose OscilloscopesTesting MIPI interfaces with theR&S RTO oscilloscopeMany components in modern smartphones communicate with each other via interfaces standardized by theMIPI Alliance. R&S RTO oscilloscopes can analyze these interfaces’ signal integrity and data content withmaximum efficiency to quickly locate errors.The MIPI standards’ ecosystemEach new generation of modern mobile phones enters themarket with new features such as additional sensors, higherdisplay resolutions and an extended range of equipment. Thenumerous components inside these devices communicatequickly and efficiently via common interfaces to offer smoothfunctionality. The most widely used standards for hardwareand software interfaces in mobile phones are from the nonprofit MIPI Alliance, which consists of more than 280 member companies. According to the MIPI Alliance, at least oneof their standards is implemented in every modern smartphone and in about 90 % of all classic mobile phones. TheMIPI standards, which are constantly evolving, are also usedin tablets and digital cameras as well as products for the automotive and health care sector. Fig. 2 shows the current status.The standard framework defines three physical layers: D-PHY,C-PHY and M-PHY (Fig. 3). These physical layers are optimized for high-speed (HS) data transmission while maintaining low power (LP) consumption. This optimization placesspecial demands on test equipment during development.This article describes the interplay with oscilloscope parameters, as well as the variety of debugging capabilities offeredby the R&S RTO oscilloscopes (Fig. 1) for MIPI protocolimplementations.Fig. 1: The R&S RTO oscilloscopes’ outstanding RF characteristics and their numerous debugging functions forMIPI interfaces save time during development.26
MIPI specifications for a mobile deviceMass storageUFSFunctional interface with native protocolDSIDisplay(s)Network connections(TCP, UDP; wired / wireless)GdD for USB(GbT, SPP)USB-C / USB2 / USB3connectorMIPI NIDnT: PHY / Pin overlayCSICamera(s) /imagingGbD for IP sockets(GbT, SPP)HTI,IEEE 1149.7USB-C / USB2 / USB3connectorHTIAudio codecSD, HDMI or DP connectorSoundWireMicrophone(s)PTI,IEEE 1149.7SD connectorHTI, PTI,IEEE 1149.7Dedicated debug andtrace connector(s)Speaker(s)AudiobridgeSoundWire XLI3CApplication processor(host)AudiobridgeSensor hubSensorsSLIMbus Bluetooth , GNSS,FM radio, NFCLLI/M-PCIeUniPort-M/SSICETPSVGIPower amplifiereTrakCompanion orbridge chipSPMIVGICellularmodemIoT connectivitymodemSwitchWireless LANmodemDigRFPowermanagementRFICAntenna tunerRFFEM-PHY D-PHYC-PHYM-PHY / D-PHY / C-PHYChip-to-chip / IPCMultimediaBIFControl and dataBatteryDebug and traceMIPI, DigRF, M-PHY, SLIMbus and SoundWire are registered service marks of MIPI Alliance. Other designations for MIPI specifications are service marks of MIPI Alliance.All other trademarks are the property of their respective owners.Fig. 2: Overview of the MIPI specifications’ ecosystem (source: MIPI Alliance).The physical layers – specifications and useD-PHY, the most commonly used specification, supports camera and display applications. The recently published specification for C-PHY describes an efficient unidirectional streaming interface with low-speed, in-band reverse channel, whichshould replace D-PHY for higher speed requirements in thefuture. The third specification, M-PHY , supports a broaderrange of applications, including interfaces for display, camera, audio, video, memory, power management and interchipcommunications, for example, between baseband chips andthose for RF. In addition, it was adopted as a physical layerfor protocols outside of the MIPI ecosystem such as MobilePCIe (M-PCIe) and SuperSpeed Inter-Chip (SSIC) USB.Several higher-level protocols are specified for each physical layer (Fig. 3). Presently, the variants based on C-PHYare
bridge chip Cellular modem ETPS I3C VGI LLI/M-PCIe UniPort-M/SSIC IoT connectivity modem Wireless LAN modem RFIC Power management Battery SPMI BIF USB-C / USB2 / USB3 connector HTI, IEEE 1149.7 MIPI NIDnT: PHY / Pin overlay SD, HDMI or DP connector HTI, PTI, IEEE 1149.7 PTI, IEEE 1149.7 HTI
MIPI CSI- 2 . Front Camera Design a sensor aggregator chip on ECU side - ECU support 1 or 2 sensors System configurable - Sensors One high lane rate Two mid-range lane rate How can MIPI C/D-PHY support this with MIPI CSI-2 controller? MIPI CSI-2 RX. ECU. C/D-PHY. Bridge. MIPI CSI- 2 . Rear Camera. MIPI CSI-2 TX
2.2. MIPI signal CSI-2 uses the MIPI standard for the D-PHY physical layer. This document provides an overview of the MIPI signal format. For more information about the MIPI specification, see MIPI Alliance Standard for Camera Serial Interface 2 documentation at mipi.org. 2.2.1. Lanes CSI-2 is a lane-scalable specification.
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MIPI CSI-2 RX Subsystem v2.2 www.xilinx.com 6 PG232 April 05, 2017 Chapter 1: Overview Sub-Core Details MIPI D-PHY The MIPI D-PHY IP core implements a D-PHY RX interface and provides PHY protocol layer support compatible with the CSI-2 RX interface. See the MIPI D-PHY LogiCORE IP Product Guide (PG202) [Ref 3] for details. MIPI D-PHY .
display interfaces in the mobile devices and It has since been the industry's main high-speed PHY solution for these mobile applications. It is often used in combination with the MIPI Camera Serial Interface-2 (CSI-2 ) and MIPI Display Serial Interface (DSI ) protocol specifications. MIPI D-PHY satisfies the
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