Clock Domain Crossing Aware Sequential Clock Gating
Clock Domain Crossing AwareSequential Clock GatingJianfeng Liu, Mi-Suk Hong, Kyungtae Do,Jung Yun Choi and Jaehong ParkMohit Kumar, Manish Kumar, Nikhil Tripathi andAbhishek RanjanS. LSI, Samsung Electronics Co. Ltd.Hwasong-Si KoreaCalypto Design Systems Inc.Noida, an}@calypto.comToday’s SOC systems have a multitude of components withmultiple interfaces. These components are working withmultiple asynchronous clock domains running at varyingspeeds. Major sub-blocks of the SoCs are designed to run onindependent clocks to ease the problems of clock skew acrosslarge chips. The clock domains are originated from differentclock sources or derivatives of those. As a result timing of theasynchronous clock domain crossing paths cannot beaccurately verified since the order of the clock edges cannot beguaranteed. These asynchronous clock domain crossings(henceforth referred to as CDC) are termed as CDC violations[8][9][10].Abstract — Power has become the overriding concern formost modern electronic applications today. To reduce clockpower, which is a significant portion of the dynamic powerconsumed by a design, sequential clock gating is increasinglygetting used over and above combinational clock gating. With theshrinking device sizes and increasingly complex designs, data isfrequently transferred from one clock domain to the other. Thesequential clock gating optimizations can use signals from acrosssequential boundaries and thus, can introduce new clock domaincrossing (CDC) violations which can cause catastrophicfunctional issues in the fabricated chip. Hence, it has become veryimportant that sequential clock gating optimizations be CDCaware.As sequential clock gating techniques analyze the designacross multiple cycles, new CDC violations may be introducedin the design. Hence, it is required that the sequential clockgating techniques should be CDC aware and should notintroduce any new CDC violations. It is also essential that thepower saving provided by sequential clock gating optimizationis not compromised when handling CDC violations.In this paper, we present an algorithm to handle CDCviolations as part of the objective function for sequential clockgating optimizations. With the proposed algorithm, we haveobtained an average of 22% sequential power savings — this iswithin 3% of the power savings obtained by the CDC unawaresequential clock gating. In comparison, the state-of-the-art twopass solution is leading to an almost complete loss of powersavings.In this paper, we first define the state-of-the-art solution toremove CDC violations introduced by the sequential clockgating optimizations in the designs. This is a two-pass processwhich constitutes performing sequential clock gatingoptimizations and then removing those clock gatingoptimizations which are causing new CDC violations in thedesign [7]. This process has the potential of causing severe lossin power savings. To overcome the limitation of two-passflow, we propose a method to handle CDC natively in thesequential clock gating optimization algorithm. This requiresthe CDC to be modeled as an objective function for the clockgating optimizations.Keywords— Clock Domain Crossing, Sequential Clock Gating,Sequential Analysis, Sequential Optimization, Observability,Stability, Power Analysis, Power Optimization.I.INTRODUCTIONReducing power consumption in a semiconductor device isbecoming one of the most important design criteria. It has beensuggested that power will be the limiting factor whendetermining the maximum number of applications that cansimultaneously be active [1] and not just the amount offunctionality that can be packed in a single die as governed byMoore’s law [2]. Clock and register power is one of the mostpower consuming components in our designs today. To reduceclock power, clock gating is used to gate the clocks whenwriting into the register is redundant [3]. Sequential clockgating, where design behavior is analyzed across multiplecycles to identify redundant writes into a register, has emergedas a very powerful technique to identify new clock gatingconditions in the design [4][5][6]. To reduce manual effort,there are solutions [7], which can automatically identify andmodify the RTL to insert new clock gating conditions based onsequential clock gating analysis.c978-3-9815370-4-8/DATE15/ 2015EDAAIn the subsequent sections, we will discuss types ofsequential clock gating optimizations, types of CDC violationsand the need for CDC awareness in sequential clock gatingoptimizations. We will then discuss the two-pass process toremove CDC violations and its associated limitations. Then, wepropose a solution for modeling CDC as part of poweroptimization objective. In the results section, we will show thatthe proposed methodology not only provides significantlyhigher power savings compared to the two-pass flow but alsoproduces a CDC clean RTL. Finally, we will conclude bysummarizing our findings and provide directions for furtherwork.1
II.PRIOR WORKClock Gating is one of the most frequently used techniquesin RTL to reduce dynamic power consumption withoutaffecting the functionality of the design [3]. It involvesinserting gating conditions in the RTL, which the synthesis tool[13][14] translates to clock gating cells in the clock-path of aregister bank. This helps to reduce the switching activity on theclock network thereby reducing dynamic power consumptionin the design. Since the translation is purely combinational, it isalso referred to as Combinational Clock Gating.Sequential clock gating on the other hand uses multi-cycleanalysis of the design to identify writes that are eitherunobservable down-stream or the same value is written inconsecutive cycles. The first type of redundant writes are calledObservability Based Clock Gating and the second type ofredundant writes are called Stability Based Clock Gating [5].Fig. 1 shows an example of writes to the register which, undersome conditions are never going to be observed at the designoutput.version of vld 1 for f 2 (and similarly one-cycle delayedversion of vld 2 for g 2).A clock domain crossing [9] occurs whenever data istransferred from a register driven by one clock domain (launch)to a register driven by another clock domain (capture). This isillustrated in Fig. 3, where the signal B is launched by a registerin the clock domain CLK1 and captured by a register in theclock domain CLK2. Asynchronous clock domain crossings arethose where the launch and the capture clock domains have noconstant phase and time relationship. Transferring signalsbetween asynchronous clock domains may lead to setup andhold time violations of registers.Fig. 3. Clock Domain CrossingFig. 1. Unobservable WritesIf the signal vld 2 is low in a particular cycle, the registerdout retains its older value. This means that the writes thatwould have happened in register d 2 one cycle back and d 1two cycles back are redundant. Observability based clockgating would identify this redundant write and add a suitablegating condition for the register d 1 based on the signal vld(and similarly based on the signal vld 1 for the register d 2).Fig. 2 shows an example where the same value gets writtento registers across consecutive clock cycles.Fig. 2. Stable WritesThe other important categories of CDC violations aredivergence of meta-stable signals and re-convergence of thesynchronized signals [8][9][10]. In Fig. 3, had the signal Cbeen feeding other logic as well, it would have been flagged asa divergence of meta-stable signal type violation.Fig. 4 shows an example of re-convergence of synchronizedsignals violation. The synchronized signals D3 and C3 areconverging and could cause functional issues in the chip. Weare not mentioning all types of CDC violations to maintain thebrevity of the paper.Fig. 4. Re-convergence of synchronized signalsWhen the signals vld 1 and vld 2 are low, the registers f 1and g 1 retain their previously held values. Consequently,values written to registers f 2 and g 2 in the next clock cycleare identical to what was written to them in the previous cycle.Stability based clock gating would identify this redundant writeand add a suitable gating condition using one-cycle delayed2These violations can cause meta-stability in the design [12].The signal C is termed as a meta-stable signal. These kinds ofsignals are unstable signals which take long to reach a validlogic value. The meta-stability issues can be mitigated by usingsynchronizers [11] in the capture clock domains. A commonlyused synchronizer is the 2-stage synchronizer shown in Fig. 3.The signal D is termed as a synchronized signal which issynchronized with respect to the clock edge of the captureclock domain and can be safely used in the logic downstream.III.ISSUES WITH CDC UNAWARE SEQUENTIAL CLOCKGATINGSequential clock gating optimizations require reasoningabout the behavior of the design across multiple cycles. This2015 Design, Automation & Test in Europe Conference & Exhibition (DATE)
often involves tracing signals across multiple designhierarchies. In the complex designs with multiple clockdomains, it is possible that new gating condition uses signalsfrom different clock domains. This could introduce new CDCviolations in the design.In Fig. 1, if the signal vld was in an asynchronous clockdomain to the clock domain clk, a CDC unaware observabilitybased clock gating would still add a gating condition for theregister d 1 based on vld signal. This would introduce a newasynchronous CDC violation on the register d 1. Similarly, inthe Fig. 2, if the signal vld 1 was in an asynchronous clockdomain to clk, a CDC unaware stability based clock gatingoptimization would still add a gating condition using a onecycle delayed version of vld 1 for the register f 2. Again, thisis a new CDC violation on f 2.IV.STATE-OF-THE-ART SOLUTIONFOR REMOVING CDC VIOLATIONSWhile determining the clock gating condition, signals frommultiple clock domains can end up participating in the clockgating condition. This would create CDC violations in thepower optimized RTL. In this section, we describe the state-ofthe-art solution for getting a CDC clean power optimizedRTL— this is a two-pass process.In this two-pass process, the CDC violations are removedfrom the RTL design as a post-process of the sequential clockgating. Fig. 7 shows a traditional RTL design flow whichmakes use of the violations reported by CDC checking tools[15][16][17] to remove the clock gating conditions which areintroducing new CDC violations.Fig. 5 shows an example where sequential clock gatingoptimization can introduce re-convergence of the synchronizedsignals. The signals vld 1 and vld 2 are synchronized controlsignals in the clock domain CLK2. A CDC unaware stabilitybased clock gating optimization would add a gating conditionfor the register dout using a one cycle delayed version of thesignals vld 1 and vld 2. This would introduce are-convergence of the synchronized signals on the registerdout.Fig. 7. Two-Pass FlowFig. 5. CDC Unaware Stability OptimizationIn Fig. 6, the signal sync meta is a meta-stable signal. CDCunaware observability based gating optimization would makeuse of this signal to generate a gating condition for the registerd 2. This clock gating condition would introduce a divergenceof the meta-stable signal which is a CDC violation.In the RTL design flow, the input design specifications andthe initial RTL is taken through a CDC checking tool. Based onthe information of the clock domains, these CDC tools do thestructural and functional analysis of the design. These toolsreport all the clock domain crossing signals. In addition tothese signals, these tools also report CDC violations likere-convergence of the synchronized signals and divergence ofthe meta-stable signals to name a few [8][9][10].Sequential clock gating optimizations can be performedusing tools like [7]. These tools provide an automated way toimplement sequential clock gating in the design. Once theclock gating logic has been inserted into the design, RTL isagain taken through the CDC checking tool. Additional CDCviolations are reported which are due to the newly insertedclock gating logic. The clock gating logic responsible for theadditional CDC violations can be removed by providingconstraints to the automated clock gating optimization tool [7].Fig. 6. CDC Unaware Observability OptimizationClearly, sequential clock gating should not be creatingstructures which will lead to CDC violations in the design.However, care has to be taken that power savings achieved bysequential clock gating is not adversely impacted.The two-step flow is an iterative way of removing clockgating conditions. A major limitation of this method is that itcould end up removing several clock gating conditions, therebybringing down power savings drastically. Additionally, it isalso runtime intensive; the process requires running thesequential clock gating tool and the CDC tool multiple times toget a CDC clean design.2015 Design, Automation & Test in Europe Conference & Exhibition (DATE)3
Fig. 8 illustrates the first limitation by using observabilitybased clock gating as an example. The clock domain of theregisters d 1 and d 2 is CLK1. The complete observabilitybased clock gating condition for the register d 1 constitutesone cycle earlier values of the registers vld 1 and cntl 1. Theone cycle earlier value of the register cntl 1 is the signal cntlwhich is in a different clock domain, CLK2. The usage of thesignal cntl in the clock gating condition for the register d 1would create a new CDC violation from the signal cntl to theregister d 1.The two-step process would remove the entire clock gatingcondition to eliminate the CDC violation. Interestingly, asmaller clock gating condition with the signal vld is stillpossible. It might provide lesser power savings as compared tothe complete clock gating condition but is CDC clean.domain specification of the primary input signals, the clockdomain of a signal s i.e., CD(s) can be computed as follows:The clock domain of a signal driven by a register is inferred asthe clock domain of the register. The clock domain of a signaldriven by a combinational logic gate is the union of the clockdomains of all the inputs of the combinational logic gate.Once all design signals are annotated with the appropriateclock domains, it is easy to apply the same procedure tocompute the clock domain of the signals for the new clockgating logic generated. This is equivalent to clock domaincomputation on the design except that it is on a smaller logicwith the available clock domains on the support signals. Here,because analysis is performed on the additional clock gatinglogic, CDC analysis is incremental and fast.B. Handling All Types of CDC ViolationsApart from the new asynchronous clock domaincrossings, all types of CDC violations should be handled i.e.,divergence of meta-stable signals, re-convergence ofsynchronized signals [8][9][10] etc.To handle all CDC violations, already existing metastable and synchronized signals should be identified. This canbe achieved by identifying all types of synchronizer patterns inthe design. Most commonly used synchronizers are 2-stagesynchronizers, multi-stage synchronizers and MUXsynchronizers [15][16][17]. In all of these synchronizers,specific signals are attributed as meta-stable and synchronizedsignals. This knowledge can be leveraged to generate a gatingcondition free of CDC violations.Fig. 8. Complete Loss of Gating Condition in the Two-Pass FlowIn the next section, we propose a new solution to mitigatethe limitations of the two-pass flow by modeling the CDC aspart of the objective function for the power optimizations.V.PROPOSED SOLUTIONWe propose an algorithm to model CDC natively in thecost/benefit analysis of the sequential clock gating optimizationalgorithms to ensure that the inserted clock gating condition isCDC clean. Out of multiple signals which could lie in differentclock domains, gating condition is created to obtain maximumpower savings without introducing new CDC violations.This algorithm would be much faster than the two-stepprocess as it would produce CDC clean clock gating conditionin single pass only.Before delving into the algorithm, it is essential tounderstand the key requirements to model CDC natively:xxxFast and incremental CDC analysisHandling of all types of CDC violationsIncorporating CDC in the cost function of SequentialClock GatingA. Fast and Incremental CDC AnalysisGiven that sequential clock gating can introduce gatinglogic for large number of registers [6], fast and incrementalCDC analysis is of utmost importance. Based on the clock4C. Incorporating CDC in the Cost Function of SequentialClock GatingA typical cost function of sequential clock gatingoptimization comprises of the area and power impact analysisof the clock gating condition [6]. The area estimation of thegating condition is straight forward. To compute the gate area,gating condition is converted to the form of an AND-ORINVERT balanced tree and the area of these cells is thencomputed from the target technology library.The power estimation is done based on the signal transitiondensities and probabilities of the support signals of the gatingcondition [6]. Statistical methods are used to propagate thesignal transition densities and probabilities across all the logicgates in the gating condition [18][19]. Using the transitiondensity on each signal of the gating condition, power can becomputed easily.Similarly, CDC analysis can be incorporated as part of thecost function of the sequential clock gating. The meta-stablesupport signals of the gating condition would need to beeliminated from the gating condition. The support signalspertaining to the asynchronous clock domain as against thetarget register would either need to be eliminated from thegating condition or can be synchronized to the target clockdomain using a synchronizer. The additional area and power ofthe synchronization logic would then have to be considered inthe cost function. In a gating condition, only one synchronizedsignal can participate; otherwise, it would lead to violationcaused by re-convergence of synchronized signals. Of the2015 Design, Automation & Test in Europe Conference & Exhibition (DATE)
}if P’ P {P : P’;G’: G’’;}synchronized signals, the signal providing maximum powersavings is kept as part of the gating condition while others arediscarded. The algorithm to model CDC as part of sequentialclock gating cost/benefit analysis is described below — alongwith the inputs required and the output generated.}}return G’;InputsxxxxxA gating condition as a Boolean function G(v1, , vn);Probability [18][19] of each support variable v i stays true,i.e., Pr(vi 1), i 1, ., n;Transition Density [18][19] of each support variable v i i.e.TD(vi), i 1, , n;The register in the design which G is targeted for;Target technology library;OutputxA boolean function G’(v1, , vk) satisfying:x G’ G, i.e., G covers G’;x Among all candidate functions that are covered by G,G’ optimally reduces power consumption related tothe register including the gating logic itself;x G’ would not introduce any new CDC violation;AlgorithmProcedure CDC AWARE COST FUNCTION(R, G, TD, Pr, CD)// R: Target Register// G: Complete Gating Condition with v1, vn supports// TD: Transition Densities of R inputs and G supports// Pr: Probabilities of R inputs and G supports// CD: Clock Domains of R inputs and G supportsbeginV : {v1, , vn}; // Support set of G;C : CD(R);// Clock domain of register R;V’ {}; // Support set of G without meta-stable signals;PRE SYNCED {}; // set of already synchronized signals;NEW SYNCED {}; // set of new synchronized signals;for each support v in V {if v is a meta-stable signal {Eliminate v from G; // Universal quantification of vV’ V – v;}if v is already synchronized {PRE SYNCED v;}if (CD(v) ! C) {Add synchronizer on signal v;NEW SYNCED v;}}// Remove all synchronized signals from G to form G’;G’ G – {PRE SYNCED NEW SYNCED};P : ComputeTotalPower(R G’);for each support v in V’ {if v ȯ {PRE SYNCED NEW SYNCED} {Eliminate all synchronized signals other than v from Gto form G’’;if v ȯ NEW SYNCED {P’ ComputeTotalPower(R G’’ synchronizer power);} else {P’ ComputeTotalPower(R G”);endFig. 9 illustrates how the above algorithm works to identifysynchronized signals that would produce maximum powersavings. If the signal sync1 is low in a particular cycle, a writeon the register d 1 in that cycle would not be observable at thedesign output; likewise for signal sync2.Assume that the probabilities of signals sync1 and sync2being high are 0.2 and 0.8 respectively. The completeobservability based gating condition for the register d 1 wouldconstitute both the signals sync1 and sync2 [4][5]. However,only one of these signals can participate in the final gatingcondition as both these signals are synchronized signals. Basedon the probabilities of these signals, it is evident that the signalsync1 (probability 0.2) remains low for more duration ascompared to the signal sync2 (probability 0.8). Since the totalpower of the register d 1 with the gating condition comprisingonly of signal sync1 would be lesser than the gating conditioncomprising of only signal sync2, signal sync1 would beselected by procedure CDC AWARE COST FUNCTION toparticipate in the final gating condition.Fig. 9. CDC and Power Aware Sequential Clock GatingVI.RESULTSIdeas discussed in previous sections have been tried on sixlarge design blocks having millions of gates (MG) from a smartphone application. Details of the designs are presented in thefirst three columns of Table 1. All these designs have threeasynchronous clock-domains.The numbers shown in the “CDC Unaware Flow’’ sectionof the table show the performance (total number of gatedregisters in KG (Kilo Gates) and their percentage with respectto total design registers, sequential power savings and totalruntime) of Sequential Clock Gating tool [7] when it isworking in the CDC unaware mode. These numbers providethe baseline for performance of a CDC aware solution.2015 Design, Automation & Test in Europe Conference & Exhibition (DATE)5
TABLE I.RESULTS COMPARING PERFORMANCE OF TWO-PASS AND CDC AWARE FLOWSCDC Unaware FlowDesignSize(MG)TotalRegisters(KG)Two-Pass (12.7%)26.6%2837Power savings are computed by running an industrialPower Analysis tool [7] on the original and sequentially-clockgated designs. The “Two-Pass Flow” section of the table showsthe performance of two-pass solution. The results of the twopass flow show a drastic reduction in number of gatedregisters (almost 10x) as well as sequential power savings. Atthe same time, runtime of two-pass flow is about 2x that ofCDC unaware flow.The last section shows the performance of CDC aware flowproposed in Section V. It is clear from the results that modelingCDC as part of sequential clock-gating optimization objectiveprovides much superior performance compared to a two-passflow. In fact, percentage of gated registers and sequentialpower savings (22% on average) of CDC aware solution isalmost similar to that of CDC unaware flow’s sequential powersavings (25% on average). In five out of six designs, thereduction in percentage of gated registers and power savings isless than 3%. Results show the clear superiority of ourproposed algorithm versus state-of-the-art two-pass flow.A CDC-checking tool [15] was used on the original designsand outputs of CDC aware flow as well as the two pass flow.There were no violations in any of them. Number of CDCviolations in CDC unaware flow can be obtained by subtractingnumber of gated registers in CDC unaware flow from thenumber of gated registers in 2-pass flow. Use of signals tocreate gating expressions from controllers in asynchronousclock domains was causing the CDC violations in a largenumber of gating expressions in the CDC unaware flow.VII. CONCLUSION AND FUTURE WORKIn this paper, we presented the need for handling CDCs as partof sequential clock gating. A new approach was presentedwhere CDCs were natively modeled as a cost function in thepower optimization objective. We showed that the approachprovides significantly superior power savings compared to thetwo-pass flow. In fact, the power savings of this approach arecomparable to the flow which is not aware of CDC restrictions.One significant aspect of the CDC aware flow is that itsruntime is comparable to the CDC unaware flow and is abouttwo times faster than the post-processing based two-pass flow.6(KG)CDC Aware FlowSequentialPowerSavingsOur approach needs to be enhanced to handle designs wherethere are existing CDC violations. In some cases, it is possiblethat new clock gating optimizations are dropped even if a CDCviolation already existed on the register being ][12][13][14][15][16][17][18][19]J. Markoff, “Progress Hits Snag: Tiny Chips Use Outsize /01chips.html? r 2.Gordon Moore, “Cramming More Components onto IntegratedCircuits,” Electronics, Volume 38, Number 8, April 19, 1965.L. Benini and G. De Micheli, "Automatic synthesis of low power gatedclock finite state machine," IEEE Trans. Computer-Aided Design, vol.15, pp. 630--643, June 1996.J. Sukumar. et al, “Clock gating for power optimization in ASIC designcycle theory & practice,” ISLPED, pp. 307--308, 2008.J. Sukumar, S. Das, A. Ranjan et al, “RTL Power Optimization inSequential Analysis Platforms,” poster presentation in DAC’2010.N. Vyagrheswarudu, S. Das, A. Ranjan, “PowerAdviser: An RTL PowerPlatform for Interactive Sequntial Optimizations”, Design Automationand Test in Europe Conference (DATE), pp. 550-553 , 12-16 March,2012.PowerPro CG, Calypto Design Systems Inc. (http://www.calypto.com/).S. Chaturvedi, “Static Analysis of Asynchronous Clock DomainCrossings”, Design Automation and Test in Europe Conference(DATE), pp. 1122-1125 , 12-16 March, 2012.Cadence Design Systems, “Clock Domain Crossing: Closing the Loopon Clock Domain Functional Implementation Problems”, technicalpaper. http://www.cadence.com/india/newsletters/icon 2005-05.pdfC. E. Cummings, “Clock Domain Crossing (CDC) Design andVerification Techniques using SystemVerilog,” SNUG 2008.P. Parakh and S. Kommrusch, “A Smart Synchronizer: Pragmatic way tocross asynchronous clock domains”, DVCON, 2011.C. L. Portmann and T. H. Y. Meng, “Metastability in CMOS Libraryelements in reduced supply and technology scaled applications,” IEEEJournal of Solid-State Circuits, 1995.Design Compiler, Synopsys Inc. (http://www.synopsys.com/).RTL Compiler, Cadence Inc. (http://www.cadence.com/).Name witheld upon request.Questa CDC, Mentor Graphics Inc. (http://www.mentor.com)SpyGlass CDC, Atrenta Inc. (http://www.atrenta.com)F. Najm, "Low-pass filter for computing the transition density in digitalcircuits," IEEE Transactions on Computer-Aided Design, vol. 13, no. 9,pp. 1123--1131, September 1994.Michael G. Xakellis, Farid N. Najm, “Statistical estimation of theswitching activity in digital circuits,” Proceedings of the 31st annualConference on Design Automation, pp.728--733, June 06-10, 19942015 Design, Automation & Test in Europe Conference & Exhibition (DATE)
as a very powerful technique to identify new clock gating conditions in the design [4][5][6]. To reduce manual effort, there are solutions [7], which can automatically identify and modify the RTL to insert new clock gating conditions based on sequential clock gating analysis. Today's SOC systems have a multitude of components with
SNUG Boston 2008 Clock Domain Crossing (CDC) Design & Verification Rev 1.0 Techniques Using SystemVerilog 6 1.0 Introduction In 2001, I presented my first paper on multi-asynchronous clock design. At that time, I had not found any good sources to describe the design and synthesis techniques required to do proper multi-clock design.
The extensive lyrics of their traditional songs . 5 o'clock (lit.: hour 5) 6 o’clock at 6 o’clock o’clock 7 at 7 o’clock o’clock 8 at o’clock 8 o'clock 11 half . Saturday Unleashing the brain’s potential Learning to music is not only
Domain Cheat sheet Domain 1: Security and Risk Management Domain 2: Asset Security Domain 3: Security Architecture and Engineering Domain 4: Communication and Network Security Domain 5: Identity and Access Management (IAM) Domain 6: Security Assessment and Testing Domain 7: Security Operations Domain 8: Software Development Security About the exam:
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SystemVerilog assertions applied to clock domain crossing has been highlighted as part of at least one paper [5] by Litterick, and is part of SV training classes as a means to monitor data as it passes between clock domains. The Litterick paper does show an example of using SystemVerilog assertions but does not cover the various corner con-ditions.
Alex’s parents had been killed shortly after he was born and he had been brought up by his father’s brother, Ian Rider. Earlier this year, Ian Rider had died too, supposedly in a car accident. It had been the shock of Alex’s life to discover that his uncle was actually a spy and had been killed on a mission in Cornwall. That was when MI6 had
