VS1053b - Ogg Vorbis/MP3/AAC/WMA/MIDI AUDIO CODEC
VS1053 BVS1053bVS1053b Ogg Vorbis/MP3/AAC/WMA/MIDIAUDIO CODECFeaturesDescription Decodes Ogg Vorbis;VS1053b is a single-chip Ogg Vorbis/MP3/AAC/MPEG 1 & 2 audio layer III (CBR VBRWMA/MIDI audio decoder and an IMA ADPCM ABR); layers I & II optional;and user-loadable Ogg Vorbis encoder. It containsMPEG4 / 2 AAC-LC( PNS),a high-performance, proprietary low-power DSPHE-AAC v2 (Level 3) (SBR PS);processor core VS DSP4 , working data memory,WMA 4.0/4.1/7/8/9 all profiles (5-384 kbps);16 KiB instruction RAM and 0.5 KiB data RAMWAV (PCM IMA ADPCM);for user applications running simultaneously withGeneral MIDI 1 / SP-MIDI format 0 filesany built-in decoder, serial control and input data Encodes Ogg Vorbis with software pluinterfaces, upto 8 general purpose I/O pins, angin (available Q4/2007)UART, as well as a high-quality variable-samplerate stereo ADC (mic, line, line mic or 2 line) Encodes IMA ADPCM from mic/line (stereo)and stereo DAC, followed by an earphone ampli Streaming support for MP3 and WAVfier and a common voltage buffer. EarSpeaker Spatial Processing Bass and treble controlsVS1053b receives its input bitstream through a Operates with a single 12.13 MHz clockserial input bus, which it listens to as a system Can also be used with a 24.26 MHz clockslave. The input stream is decoded and passedthrough a digital volume control to an 18-bit over Internal PLL clock multipliersampling, multi-bit, sigma-delta DAC. The decod Low-power operationing is controlled via a serial control bus. In addi High-quality on-chip stereo DAC with notion to the basic decoding, it is possible to addphase error between channelsapplication specific features, like DSP effects, to Zero-cross detection for smooth volumethe user RAM memory.change Stereo earphone driver capable of driving aOptional factory-programmable unique chip ID pro30 Ω loadvides basis for digital rights management or unit Quiet power-on and power-offidentification features. I2S interface for external DACI2S Separate voltages for analog, digital, I/OaudioVS1053LStereo Ear StereoStereo On-chip RAM for user code and data differentialMUXMIC AMPmic / line 1phone DriverADCDACRline 2output Serial control and data interfaces8GPIOGPIO Can be used as a slave co-processorX ROMDREQ SPI flash boot for special applicationsSOSerialSIX RAMData/ UART for debugging purposes4SCLKControlVSDSPInterface New functions may be added with software XCSXDCSY ROMand upto 8 GPIO pinsRX Lead-free RoHS-compliant package (Green) TXUARTY RAMClockmultiplierVersion 1.01,2008-05-22InstructionRAMInstructionROM1
VLSIVS1053bySolutionVS1053 s94Characteristics & Specifications104.1Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104.2Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .104.3Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114.4Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124.5Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124.6Switching Characteristics - Boot Initialization . . . . . . . . . . . . . . . . . . . . . . .125Packages and Pin Descriptions135.1Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135.1.113LQFP-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Connection Diagram, LQFP-48167SPI Buses187.1General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187.2SPI Bus Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187.2.1VS1002 Native Modes (New Mode) . . . . . . . . . . . . . . . . . . . . . . . .187.2.2VS1001 Compatibility Mode (deprecated) . . . . . . . . . . . . . . . . . . . . .18Data Request Pin DREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197.3Version 1.01,2008-05-222
VLSIVS1053bySolution7.4CONTENTSSerial Protocol for Serial Data Interface (SDI) . . . . . . . . . . . . . . . . . . . . . . .197.4.1General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197.4.2SDI in VS1002 Native Modes (New Mode) . . . . . . . . . . . . . . . . . . . .197.4.3SDI in VS1001 Compatibility Mode (deprecated) . . . . . . . . . . . . . . . . .207.4.4Passive SDI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Serial Protocol for Serial Command Interface (SCI) . . . . . . . . . . . . . . . . . . . .207.5.1General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207.5.2SCI Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217.5.3SCI Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217.5.4SCI Multiple Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227.6SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237.7SPI Examples with SM SDINEW and SM SDISHARED set . . . . . . . . . . . . . . .247.7.1Two SCI Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247.7.2Two SDI Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247.7.3SCI Operation in Middle of Two SDI Bytes . . . . . . . . . . . . . . . . . . . .257.58VS1053 BFunctional Description268.1Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268.2Supported Audio Codecs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268.2.1Supported MP3 (MPEG layer III) Formats . . . . . . . . . . . . . . . . . . . .268.2.2Supported MP1 (MPEG layer I) Formats . . . . . . . . . . . . . . . . . . . . .278.2.3Supported MP2 (MPEG layer II) Formats . . . . . . . . . . . . . . . . . . . . .278.2.4Supported Ogg Vorbis Formats . . . . . . . . . . . . . . . . . . . . . . . . . . .278.2.5Supported AAC (ISO/IEC 13818-7 and ISO/IEC 14496-3) Formats . . . . . . .288.2.6Supported WMA Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30Version 1.01,2008-05-223
VLSIVS1053bySolution9VS1053 BCONTENTS8.2.7Supported RIFF WAV Formats . . . . . . . . . . . . . . . . . . . . . . . . . . .318.2.8Supported MIDI Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328.3Data Flow of VS1053b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .348.4EarSpeaker Spatial Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358.5Serial Data Interface (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368.6Serial Control Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368.7SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378.7.1SCI MODE (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .388.7.2SCI STATUS (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .408.7.3SCI BASS (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .418.7.4SCI CLOCKF (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .428.7.5SCI DECODE TIME (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . .438.7.6SCI AUDATA (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .438.7.7SCI WRAM (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .438.7.8SCI WRAMADDR (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .438.7.9SCI HDAT0 and SCI HDAT1 (R) . . . . . . . . . . . . . . . . . . . . . . . . .458.7.10 SCI AIADDR (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .468.7.11 SCI VOL (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .478.7.12 SCI AICTRL[x] (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47Operation489.1Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .489.2Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .489.3Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .489.4Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49Version 1.01,2008-05-224
VLSISolutionVS1053by9.5VS1053 BCONTENTSPlay and Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .499.5.1Playing a Whole File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .499.5.2Cancelling Playback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .509.5.3Fast Play . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .509.5.4Fast Forward and Rewind without Audio . . . . . . . . . . . . . . . . . . . . .509.5.5Maintaining Correct Decode Time . . . . . . . . . . . . . . . . . . . . . . . . .519.6Feeding PCM data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .529.7Ogg Vorbis Recording . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .529.8ADPCM Recording . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .539.8.1Activating ADPCM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .539.8.2Reading IMA ADPCM Data . . . . . . . . . . . . . . . . . . . . . . . . . . . .549.8.3Adding a RIFF Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .559.8.4Playing ADPCM Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .569.8.5Sample Rate Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . .56SPI Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .579.10 Real-Time MIDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .579.11 Extra Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .589.11.1 Common Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .599.11.2 WMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .609.11.3 AAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .619.11.4 Midi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .629.11.5 Ogg Vorbis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .629.12 SDI Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .639.12.1 Sine Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .639.9Version 1.01,2008-05-225
VLSISolutionVS1053byVS1053 BCONTENTS9.12.2 Pin Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .639.12.3 SCI Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .649.12.4 Memory Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .649.12.5 New Sine and Sweep Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6410 VS1053b Registers6610.1 Who Needs to Read This Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6610.2 The Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6610.3 VS1053b Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6610.4 SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6610.5 Serial Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6710.6 DAC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6710.7 GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6710.8 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6810.9 Watchdog v1.0 2002-08-26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6910.9.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6910.10UART v1.1 2004-10-09 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7010.10.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7010.10.2 Status UARTx STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7010.10.3 Data UARTx DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7110.10.4 Data High UARTx DATAH . . . . . . . . . . . . . . . . . . . . . . . . . . . .7110.10.5 Divider UARTx DIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7110.10.6 Interrupts and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7210.11Timers v1.0 2002-04-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7310.11.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73Version 1.01,2008-05-226
VLSISolutionVS1053byVS1053 BCONTENTS10.11.2 Configuration TIMER CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . .7310.11.3 Configuration TIMER ENABLE . . . . . . . . . . . . . . . . . . . . . . . . . .7410.11.4 Timer X Startvalue TIMER Tx[L/H] . . . . . . . . . . . . . . . . . . . . . . .7410.11.5 Timer X Counter TIMER TxCNT[L/H] . . . . . . . . . . . . . . . . . . . . . .7410.11.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7410.12VS1053b Audio Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7510.13I2S DAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7610.13.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7610.13.2 Configuration I2S CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . .7611 VS1053 Version Changes11.1 Changes Between VS1033c and VS1053a/b Firmware, 2007-03-08 . . . . . . . . . . . .777712 Document Version Changes7913 Contact Information80Version 1.01,2008-05-227
VLSISolutionVS1053byVS1053 BLIST OF FIGURESList of Figures1Pin Configuration, LQFP-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132VS1053b in LQFP-48 Packaging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133Typical Connection Diagram Using LQFP-48. . . . . . . . . . . . . . . . . . . . . . . .164BSYNC Signal - one byte transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205BSYNC Signal - two byte transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206SCI Word Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217SCI Word Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218SCI Multiple Word Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229SPI Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2310Two SCI Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2411Two SDI Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2412Two SDI Bytes Separated By an SCI Operation. . . . . . . . . . . . . . . . . . . . . . .2513Data Flow of VS1053b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3414EarSpeaker externalized sound sources vs. normal inside-the-head sound . . . . . . . . .3515RS232 Serial Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7016VS1053b ADC and DAC data paths . . . . . . . . . . . . . . . . . . . . . . . . . . . .7517I2S Interface, 192 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76Version 1.01,2008-05-228
VLSIVS1053bySolution1VS1053 B1. LICENSESLicensesMPEG Layer-3 audio decoding technology licensed from Fraunhofer IIS and Thomson.Note: If you enable Layer I and Layer II decoding, you are liable for any patent issues that mayarise from using these formats. Joint licensing of MPEG 1.0 / 2.0 Layer III does not cover all patentspertaining to layers I and II.VS1053b contains WMA decoding technology from Microsoft.This product is protected by certain intellectual property rights of Microsoft and cannot be usedor further distributed without a license from Microsoft.VS1053b contains AAC technology (ISO/IEC 13818-7 and ISO/IEC 14496-3) which cannot be usedwithout a proper license from Via Licensing Corporation or individual patent holders.VS1053b contains spectral band replication (SBR) and parametric stereo (PS) technologies developed byCoding Technologies. Licensing of SBR is handled within MPEG4 through Via Licensing Corporation.Licensing of PS is handled with Coding Technologies.See s.htm for more information.To the best of our knowledge, if the end product does not play a specific format that otherwise wouldrequire a customer license: MPEG 1.0/2.0 layers I and II, WMA, or AAC, the respective license shouldnot be required. Decoding of MPEG layers I and II are disabled by default, and WMA and AAC formatexclusion can be easily performed based on the contents of the SCI HDAT1 register. Also PS and SBRdecoding can be separately disabled.2DisclaimerThis is a preliminary datasheet. All properties and figures are subject to change.3DefinitionsB Byte, 8 bits.b Bit.Ki “Kibi” 210 1024 (IEC 60027-2).Mi “Mebi” 220 1048576 (IEC 60027-2).VS DSP VLSI Solution’s DSP core.W Word. In VS DSP, instruction words are 32-bit and data words are 16-bit wide.Version 1.01,2008-05-229
VS1053 BVLSIVS1053b4. CHARACTERISTICS & SPECIFICATIONSySolution4Characteristics & Specifications4.1Absolute Maximum RatingsParameterAnalog Positive SupplyDigital Positive SupplyI/O Positive SupplyCurrent at Any Non-Power Pin1Voltage at Any Digital InputOperating TemperatureStorage 3-30-65Max3.61.853.6 50IOVDD 0.32 85 150UnitVVVmAV C CHigher current can cause latch-up.Must not exceed 3.6 V4.2Recommended Operating ConditionsParameterAmbient Operating TemperatureAnalog and Digital Ground 1Positive Analog, REF 1.23VPositive Analog, REF 1.65V 2Positive DigitalI/O VoltageInput Clock Frequency 3Internal Clock FrequencyInternal Clock Multiplier 4Master Clock Duty CycleSymbolAGND 121.0 40Typ0.02.83.31.82.812.28836.8643.0 50Max 853.63.61.853.61355.34.5 60Unit CVVVVVMHzMHz%1Must be connected together as close the device as possible for latch-up immunity.Reference voltage can be internally selected between 1.23V and 1.65V, see section 8.7.2.3 The maximum sample rate that can be played with correct speed is XTALI/256 (or XTALI/512 ifSM CLK RANGE is set). Thus, XTALI must be at least 12.288 MHz (24.576 MHz) to be able to play48 kHz at correct speed.4 Reset value is 1.0 . Recommended SC MULT 3.5 , SC ADD 1.0 (SCI CLOCKF 0x8800).Do not exceed maximum specification for CLKI.2Version 1.01,2008-05-2210
VS1053 BVLSIVS1053b4. CHARACTERISTICS & SPECIFICATIONSySolution4.3Analog CharacteristicsUnless otherwise noted: AVDD 3.3V, CVDD 1.8V, IOVDD 2.8V, REF 1.65V, TA -30. 85 C,XTALI 12.13MHz, Internal Clock Multiplier 3.5 . DAC tested with 1307.894 Hz full-scale outputsinewave, measurement bandwidth 20.20000 Hz, analog output load: LEFT to GBUF 30 Ω, RIGHT toGBUF 30 Ω. Microphone test amplitude 48 mVpp, fs 1 kHz, Line input test amplitude 1.26 V, fs 1 kHz.ParameterDAC ResolutionTotal Harmonic DistortionThird Harmonic DistortionDynamic Range (DAC unmuted, A-weighted)S/N Ratio (full scale signal)Interchannel Isolation (Cross Talk), 600Ω GBUFInterchannel Isolation (Cross Talk), 30Ω GBUFInterchannel Gain MismatchFrequency ResponseFull Scale Output Voltage (Peak-to-peak)Deviation from Linear PhaseAnalog Output Load ResistanceAnalog Output Load CapacitanceMicrophone input amplifier gainMicrophone input amplitudeMicrophone Total Harmonic DistortionMicrophone S/N RatioMicrophone input impedances, per pinLine input amplitudeLine input Total Harmonic DistortionLine input S/N RatioLine input 80030.014Unitbits%%dBdBdBdBdBdBVpp ΩpFdBmVpp AC%dBkΩmVpp AC%dBkΩ13.0 volts can be achieved with -to- wiring for mono difference sound.AOLR may be much lower, but below Typical distortion performance may be compromised.3 Above typical amplitude the Harmonic Distortion increases.2Version 1.01,2008-05-2211
VS1053 BVLSIVS1053b4. CHARACTERISTICS & SPECIFICATIONSySolution4.4Power ConsumptionTested with an MPEG 1.0 Layer-3 128 kbps sample and generated sine. Output at full volume. Internalclock multiplier 3.0 . TA 25 C.ParameterPower Supply Consumption AVDD, ResetPower Supply Consumption CVDD 1.8V, ResetPower Supply Consumption AVDD, sine test, 30 Ω GBUFPower Supply Consumption CVDD 1.8V, sine testPower Supply Consumption AVDD, no loadPower Supply Consumption AVDD, output load 30 ΩPower Supply Consumption AVDD, 30 Ω GBUFPower Supply Consumption CVDD 1.8V4.5High-Level Output Voltage at XTALO -0.1 mALow-Level Output Voltage at XTALO 0.1 mAHigh-Level Output Voltage at IO -1.0 mALow-Level Output Voltage at IO 1.0 mAInput Leakage CurrentSPI Input Clock Frequency 2Rise time of all output pins, load 50 AmAmAmAmAmAmADigital CharacteristicsParameterHigh-Level Input VoltageLow-Level Input Voltage1MinMust not exceed 3.6VValue for SCI reads. SCI and SDI writes allowMin0.7 CVDD-0.20.7 IOVDDMaxIOVDD 0.310.3 CVDD0.3 IOVDD0.7 IOVDD-1.00.3 IOVDD1.0CLKI750UnitVVVVVVµAMHznsCLKI4 .4.6 Switching Characteristics - Boot InitializationParameterXRESET active timeXRESET inactive to software readyPower on reset, rise time to EQ rises when initialization is complete. You should not send any data or commands before that.Version 1.01,2008-05-2212
VLSIVS1053bySolution5VS1053 B5. PACKAGES AND PIN DESCRIPTIONSPackages and Pin Descriptions5.1PackagesLPQFP-48 is a lead (Pb) free and also RoHS compliant package. RoHS is a short name of Directive2002/95/EC on the restriction of the use of certain hazardous substances in electrical and electronicequipment.5.1.1LQFP-48481Figure 1: Pin Configuration, LQFP-48.LQFP-48 package dimensions are at http://www.vlsi.fi/ .Figure 2: VS1053b in LQFP-48 Packaging.Version 1.01,2008-05-2213
VLSIVS1053bySolutionPad NameMICP / LINE1MICNXRESETDGND0CVDD0IOVDD0CVDD1DREQGPIO2 / DCLK1GPIO3 / SDATA1GPIO6 / I2S SCLK3GPIO7 / I2S SDATA3XDCS / 4XCSCVDD2GPIO5 / I2S MCLK3RXTXSCLKSISOCVDD3XTESTGPIO0GPIO1GNDGPIO4 / I2S OAPWRAOAPWRAIVS1053 B5. PACKAGES AND PIN DESCRIPTIONSFunctionPositive differential mic input, self-biasing / Line-in 1Negative differential mic input, self-biasingActive low asynchronous reset, schmitt-trigger inputCore & I/O groundCore power supplyI/O power supplyCore power supplyData request, input busGeneral purpose IO 2 / serial input data bus clockGeneral purpose IO 3 / serial data inputGeneral purpose IO 6 / I2S SCLKGeneral purpose IO 7 / I2S SDATAData chip select / byte syncI/O power supplyFor testing only (Clock VCO output)Core & I/O groundCrystal outputCrystal inputI/O power supplyCore & I/O groundCore & I/O groundCore & I/O groundChip select input (active low)Core power supplyGeneral purpose IO 5 / I2S MCLKUART receive, connect to IOVDD if not usedUART transmitClock for serial busSerial inputSerial outputCore power supplyReserved for test, connect to IOVDDGen. purp. IO 0 (SPIBOOT), use 100 kΩ pull-down resistor2General purpose IO 1I/O GroundGeneral purpose IO 4 / I2S LROUTAnalog ground, low-noise referenceAnalog power supplyRight channel outputAnalog groundAnalog groundCommon buffer for headphones, do NOT connect to ground!Analog power supplyFiltering capacitance for referenceAnalog power supplyLeft channel outputAnalog groundLine-in 2 (right channel)1First pin function is active in New Mode, latter in Compatibility Mode.Unless pull-down resistor is used, SPI Boot is tried. See Chapter 9.9 for details.3 If I2S CF ENA is ’0’ the pins are used for GPIO. See Chapter 10.13 for details.2Version 1.01,2008-05-2214
VLSISolutionVS1053byVS1053 B5. PACKAGES AND PIN DESCRIPTIONSPin types:TypeDIDODIODO3AIVersion 1.01,DescriptionDigital input, CMOS Input PadDigital output, CMOS Input PadDigital input/outputDigital output, CMOS Tri-stated Output PadAnalog onAnalog outputAnalog input/outputAnalog power supply pinCore or I/O ground pinCore power supply pinI/O power supply pin15
VLSIVS1053bySolution6VS1053 B6. CONNECTION DIAGRAM, LQFP-48Connection Diagram, LQFP-48Figure 3: Typical Connection Diagram Using LQFP-48.Figure 3 shows a typical connection diagram for VS1053.Figure Note 1: Connect either Microphone In or Line In, but not both at the same time.Note: This connection assumes SM SDINEW is active (see Chapter 8.7.1). If also SM SDISHARE isused, xDCS should be tied low or high (see Chapter 7.2.1).Version 1.01,2008-05-2216
VLSISolutionVS1053byVS1053 B6. CONNECTION DIAGRAM, LQFP-48The common buffer GBUF can be used for common voltage (1.23 V) for earphones. This will eliminatethe need for large isolation capacitors on line outputs, and thus the audio output pins from VS1053b maybe connected directly to the earphone connector.GBUF must NOT be connected to ground under any circumstances. If GBUF is not used, LEFT andRIGHT must be provided with coupling capacitors. To keep GBUF stable, you should always have theresistor and capacitor even when GBUF is not used. See application notes for details.Unused GPIO pins should have a pull-down resistor. Unused line and microphone inputs should not beconnected.If UART is not used, RX should be connected to IOVDD and TX be unconnected.Do not connect any external load to XTALO.Version 1.01,2008-05-2217
VLSIVS1053bySolution7VS1053 B7. SPI BUSESSPI Buses7.1GeneralThe SPI Bus - that was originally used in some Motorola devices - has been used for both VS1053b’sSerial Data Interface SDI (Chapters 7.4 and 8.5) and Serial Control Interface SCI (Chapters 7.5 and 8.6).7.2SPI Bus Pin Descriptions7.2.1VS1002 Native Modes (New Mode)These modes are active on VS1053b when SM SDINEW is set to 1 (default at startup). DCLK andSDATA are not used for data transfer and they can be used as general-purpose I/O pins (GPIO2 andGPIO3). BSYNC function changes to data interface chip select (XDCS).SDI PinXDCSSCI PinXCSSCKSI-7.2.2SODescriptionActive low chip select input. A high level forces the serial interface intostandby mode, ending the current operation. A high level also forces serialoutput (SO) to high impedance state. If SM SDISHARE is 1, pinXDCS is not used, but the signal is generated internally by invertingXCS.Serial clock input. The serial clock is also used internally as the masterclock for the register interface.SCK can be gated or continuous. In either case, the first rising clock edgeafter XCS has gone low marks the first bit to be written.Serial input. If a chip select is active, SI is sampled on the rising CLK edge.Serial output. In reads, data is shifted out on the falling SCK edge.In writes SO is at a high impedance state.VS1001 Compatibility Mode (deprecated)This mode is active when SM SDINEW is set to 0. In this mode, DCLK, SDATA and BSYNC are active.SDI Pin-SCI PinXCSBSYNCDCLKSCKSDATA-SISOVersion 1.01,2008-05-22DescriptionActive low chip select input. A high level forces the serial interface intostandby mode, ending the current operation. A high level also forces serialoutput (SO) to high impedance state.SDI data is synchronized with a rising edge of BSYNC.Serial clock input. The serial clock is also used internally as the masterclock for the register interface.SCK can be gated or continuous. In either case, the first rising clock edgeafter XCS has gone low marks the first bit to be written.Serial input. SI is sampled on the rising SCK edge, if XCS is low.Serial output. In reads, data is shifted out on the falling SCK edge.In writes SO is at a high impedance state.18
VLSIVS1053bySolution7.3VS1053 B7. SPI BUSESData Request Pin DREQThe DREQ pin/signal is used to signal if VS1053b’s 2048-byte FIFO is capable of receiving data. IfDREQ is high, VS1053b can take at least 32 bytes of SDI data or one SCI command. DREQ is turnedlow when the stream buffer is too full and for the duration of a SCI command.Because of the 32-byte safety area, the sender may send upto 32 bytes of SDI data at a time withoutchecking the status of DREQ, making controlling VS1053b easier for low-speed microcontrollers.Note: DREQ may turn low or high at any time, even during a byte transmission. Thus, DREQ shouldonly be used to decide whether to send more bytes. It does not need to abort a transmission that hasalready started.Note: In VS10XX products upto VS1002, DREQ was only used for SDI. In VS1053b DREQ is alsoused to tell the status of SCI.There are cases when you still want to send SCI commands when DREQ is low. Because DREQ isshared between SDI and SCI, you can not determine if a SCI command has been executed if SDI is notready to receive. In this case you need a long enough delay after every SCI command to make certainnone of them is missed. The SCI Registers table in section 8.7 gives the worst-case handling time foreach SCI register write.7.47.4.1Serial Protocol for Serial Data Interface (SDI)GeneralThe serial data interface operates in slave mode so DCLK signal must be generated by an external circuit.Data (SDATA signal) can be clocked in at either the rising or falling edge of DCLK (Chapter 8.7).VS1053b assumes i
MPEG Layer-3 audio decoding technology licensed from Fraunhofer IIS and Thomson. Note: If you enable Layer I and Layer II decoding, you are liable for any patent issues that may arise from using these formats. Joint licensing of MPEG 1.0 / 2.0 Layer III does not cover all patents pertaining to layers I and II.
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Tulang Penyusun Sendi Siku .41 2. Tulang Penyusun Sendi Pergelangan Tangan .47 DAFTAR PUSTAKA . Anatomi dan Biomekanika Sendi dan Pergelangan Tangan 6 Al-Muqsith Ligamentum annularis membentuk cincin yang mengelilingi caput radii, melekat pada bagian tepi anterior dan posterior insicura radialis pada ulna. Bagian dari kondensasi annular pada caput radii disebut dengan “annular band .
