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INTERNATIONAL JOURNAL OF SCIENTIFIC & TECHNOLOGY RESEARCH VO LUME 10, ISSUE 02, FEBRUARY 2021ISSN 2277-8616Design And Implementation Of Multi-User OFDMBased Orthogonal Chaotic Vector Shift KeyingUsing FPGA TechniquesAnsam M. Abed, Fadhil S. HassanAbstract: In this paper, an effective design and implementation of the Multi-user orthogonal frequency division multiplexing based orthogonal chaoticvector shift keying (Multi-User OFDM-OCVSK) system over multipath fading channel by using field programmable gate array (FPGA) platform ispresented. The system model is designed and implemented using Xilinx system generator (XSG) tool with Vivado 2019.1 software. The Xilinx SystemGenerator (XSG) is used because it is more reliable, flexible, easy to update and modify the system design in addition to give the perfect design forFPGA technique compared with the traditional FPGA design. The VHDL code file is generated and the hardware co-simulation of the suggested systemis performed on the Kintex 7 KC705 evaluation kit. The system is routed in successfully using Vivado 2019.1 program with 100 MHZ clock frequency.The results of hardware simulation prove that the system is worked in the correct form in real time process.Index Terms: Multiuser OFDM-DCSK, OCVSK, FPGA.—————————— ——————————1 INTRODUCTIONBEING non periodic, wide-band, sensitive to initial conditions,random-like nature with easiness to generate, chaotic signalsare more suitable for communication with the spread-spectrum[1],[2]. The Differential Chaos Shift Keying (DCSK) is preferredamong numbers of chaotic modulation schemes due to itsrobustness to multipath fading environments and non-coherentability of implementation and simple transceiver requirement.In DCSK system every bit duration is split into two equalsegments and a reference chaotic sequence is transmittedwithin the first time duration. According to the value of the bitto be sent, the reference signal is either copied or inverted andsent within the second time slot [1]-[3]. Many DCSK systemshave been studied to evaluate its performance under differentscenarios. In fact, the primary defect of the DCSK is that halfof the bit’s time slot in this system is employed for bearingreference signals so it is spent sending no-data. This can beconsidered as a significant data rate reducer and energyinefficient for transmission [4]-[9] Orthogonal FrequencyDivision Multiplexing (OFDM) is the more dominant multicarriermodulation for discrete signals in nowadays technology [10][12]. OFDM-DCSK system is suggested to combine theadvantages of OFDM and DCSK system, decrease thecomplexity of the multicarrier DCSK system and offer betterspectral efficiency compared to conventional DCSK systems[13]-[15]. In [16] the authors presented the multi-user OFDMDCSK to support multi-user communication. Although thissystem enhances the spectral and energy efficiency, itincreases multiple access interference (MAI). To decrease themultiple access interference (MAI) of multi-user OFDM DCSKsystem the authors in [17] increasing the orthogonality of thechaotic sequences and design an improved system withorthogonal chaotic vector shift keying (OCVSK) using GramSchmidt orthonormalization process. In the moderncommunication systems field programmable gate array(FPGA) is preferred among different kinds of implementations,because it is very cost-effective, enhances the processingspeed and highly flexible solution, that provides best systemperformance and enables easy system improvement [18].Xilinx system Generator (XSG) is supported tools to implementthe digital systems in FPGA that is a flexible, and reliable toolused for building different models and generating VHDL codewith easiness to upgrade the design for the system. It providesdifferent building blocks of digital processing (DSP) that existsin XSG block set in Simulink tools to build a different modeland generate VHDL code for the system design with optimumway [19]. An effective FPGA design of DCSK system ispresented in [20] the authors used the DSP builder technique.Using XSG, in [21] the implementation of the non-coherentdifferential chaos shift keying (DCSK) system over AWGNchannel for different values of spreading factor is presented.FPGA technique is also used in [22] to implement HaarWavelet Packet Modulation (HWPM-DCSK) in efficient waywith high clock rates. In this paper, we use FPGA technique toimplement the hardware design of MU-OFDM-OCVSK systemwhich is analyzed and compared with multi-user OFDM-DCSKsystem [17]. The proposed system is implemented using anFPGA Kintex7 KC705 evaluation kit integrated with Vivado2019.1 software. The rest of the paper is organized as thefollowing: section II introduce the architecture of MU- OFDMOCVSK communication system and Section III contains XSGbased MU-OFDM-OCVSK system. In Section Four thesimulation results and the XSG waveforms are presented, andFPGA results, the synthesis reports and The Hardware cosimulation are shown in Sections V and VI respectively.Finally, the conclusion is drawn in the VII Section.2 MULTI-USER-OFDM-OCVSKCOMMUNICATIOM SYSTEMThe proposed two-users OFDM-OCVSK system block diagramis shown in Figure 1 which include three main parts: thetransmitter, channel , and the receiver of two-users. The inputdata of each user is converted to parallel bits du,p (p 1, .,M)using serial to parallel converter. The chaotic reference isgenerated by chaotic generator that is used to spread thedigital signal over a wideband to obtain a modulated signalwith spreading factor value equal to 16. The modulated signalis then passing through 16 point IFFT producing themulticarrier signal. A parallel to serial converter is taken placeafter that to convert the parallel stream of data bits to serial bitstream in order to be sent through the channel. Two flat fadingchannels (one for each user) and AWGN are taking place toproduce the received signal. At the receiver side, an inverseaction to that of the transmitter side with serial to parallelconverter, FFT, and a non-coherent DCSK demodulation135IJSTR 2021www.ijstr.org
INTERNATIONAL JOURNAL OF SCIENTIFIC & TECHNOLOGY RESEARCH VO LUME 10, ISSUE 02, FEBRUARY 2021ISSN 2277-8616(correlator and threshold ) will be applied to the combinedreceived signal to reproduce the original data bits of each user.2.1 Review StageFig. 2 Xilinx System Generator block diagram of 2 UsersOFDM OCVSK transceiver.(a)3.1 Transmitter SectionThis section contains the blocks of binary input source, chaosgenerator, serial-to-parallel (S/P) converter, mapping,spreading and zero padding, IFFT and finally, TDM as shownin figure 3. Each one of these blocks has been implementedusing XSG in Simulink/Matlab.3.1.1Binary input sourceThe binary input signal is generated using Bernoulli binarygenerator block which is Simulink/MATLAB (S/M) functiongenerate a stream of binary sequence. This binary data will beused for testing the proposed system performance. The typeof the output data of this block should be doubled and thesample time must be 1 with 0.5 probability of zero to produceones and zeros with same probability. The gateway-in andgateway-out are used to convert from S/M to SystemGenerator (SG) and from SG to S/M environment respectively.Fig. 1 Block diagram of the system model (a) Transmitter (b)Receiver.3 XSG IMPLEMENTATION OF MU-OFDMOCVSK SYSTEM DESIGNThe communication system model presented in section 2 isperformed using XSG as shown in Figure 2, each block shownin the figure is designed with a certain parameters tocorrespond the blocks in Figure 1. At the transmitter side (foreach user), the input bits are generated using Bernoulli binarysignal generator of 100 Mbps rate. A serial-to-parallelconverter is used to convert the serial input bits into 8 parallelbits with rate varying to 12.5 Mbps. Every bit in the parallelgroup is mapped to 1 or -1 depends on the value of the bitwhether it is 1 or 0 respectively using the mapping blockfunction. After that, DCSK system is used to spread thesymbol which will be passed through the IFFT to generate theOFDM signal. After that, the signal will be distorted byMultipath Rayleigh fading channel with AWGN. The receiverside is designed to perform the reverse operation to that of thetransmitter to recover the binary bit stream of each user. Thedetails of each block will be explained individually in the nextsubsections.Fig. 3 XSG block diagram of OFDM-OCVSK transmitter.3.1.2Chaos generator blockThe XSG block diagram of the chaos signal generator isshown in Figure 4. Chaotic signal is generated using theChebyshev Polynomial Function (CPF) of order two accordingto Equation (1). This signal represents the reference of thesystem that is used for spreading the input data sequence.136IJSTR 2021www.ijstr.org
INTERNATIONAL JOURNAL OF SCIENTIFIC & TECHNOLOGY RESEARCH VO LUME 10, ISSUE 02, FEBRUARY 2021(1)The output data format is assigned by a word length of 20 bitswith 16 bits for fractional length.Fig. 4 Xilinx System Generator block diagram of the chaosgenerator.3.1.3Serial-to-parallel converter blockThe S/P block is existing in the XSG library with the number ofbits is 8 and the latency is 1 the output is a symbol of 8 bitsthat need a set of 8 blocks of slices (one slice block for eachbit) which is available in XSG library used to convert the 8 bits’symbol into parallel bits. The slice blocks are used forselecting the range of bits for each input sample. The outputdata in each slice is unsigned and the bit number is 1. TheXSG block diagram of the serial to parallel converter is shownin Figure 5.ISSN 2277-8616diagram of the mapping block is shown in Figure 6.3.1.5Spreading and zero padding blockThe spreading process is done by multiplying the inputmapping data with the chaotic sequence. The Spreading blockconsists of eight multipliers with a constant block of zero valueused for zero padding. The multiplier is used for spreadinginformation by multiplying the mapping data with the chaoticsequence. The output data format for each multiplier is signed,the word length is 16 and the Fraction Length is 14 bits. TheXSG block diagram for spreading and zero padding block ispresented in Figure 7.3.1.6Inverse Fast Fourier transform (IFFT) blockAfter the spreading process, the signal is passing throughIFFT to obtain the OFDM signal. IFFT is carried out byparalleling techniques in which the throughput is increasedbecause multiple functions can be performed at the same time[23]. IFFT changes the spread signal domain from frequencyto time domain. The XSG block diagram of 16-point IFFT isshown in Figure 9. First, the 16 signals are mixed according tobit reversal order. Then, the mixed data is passing throughStage-1, Multiplication-1, Stage-2, Multiplication-2, Stage-3,Multiplication-3 and Stage-4 modules that are implementedusing XSG. The fixed-point precision word length for eachoperation is 24 bits with 16 bits for fractional.Fig. 6 XSG block diagram of the mapping block.Fig. 5 XSG block diagram of the serial to parallel converter.3.1.4Mapping blockThe mapping block is used to map the parallel bits into 1 and 1. It consists of 8 ROM blocks where every bit of the paralleldata has represented as an address to the ROM block toindicate either the phase of {00} or the phase of {1800}, whenthe initial value vector for the ROM is [-1 1]. The output dataformat for each ROM block will be signed with word length 2bits and fraction point of 0 bits. A delay block of 8 latency hasbeen linked to the enable pin of each ROM block to mask allthe bits till they are ready for the map process. The XSG blockFig. 7 XSG block diagram of spreading and zero padding blocks.137IJSTR 2021www.ijstr.org
INTERNATIONAL JOURNAL OF SCIENTIFIC & TECHNOLOGY RESEARCH VO LUME 10, ISSUE 02, FEBRUARY 2021ISSN 2277-86163.3 Receiver SectionThe 16 parallel OFDM signal must be converted to serialsymbol once again. Time division Multiplexing (TDM) block isused to multiplex the parallel samples into serial symbol. EachOFDM signal requires two 16 input TDM block one for the realpart of the signal and the other for the imaginary. Then the twoserial complex OFDM signals are passed through themultipath fading channel.The receiver section is shown in Figure 11. It consists of thefollowing blocks:3.3.1Fig. 8 Xilinx System Generator block diagram of 16 pointsdecimation in time IFFT.3.2 The channelFigure 9 shows XSG block diagram of two-users multipathRayleigh fading with AWGN channel. Where the transmittedsignal of each user passes through two paths channelimplemented using white Gaussian noise generator blockavailable in XSG communication library with seed value 512,multiplied by the channel coefficient of each path (1/3, 2/3).The XSG block diagram of user’s channel is shown in figure10. The two users’ channels are added together then addedwith AWGN signal, where the noise signal is produced usingWhite Gaussian Noise Generator block and the output ismultiplied by the standard deviation of the noise power (𝜎) thatis associated with the Signal to Noise Ratio (SNR).Fig. 11 Xilinx System Generator block diagram ofOFDM OCVSK receiver.Fast Fourier Transform (FFT)First, the two complex received signals are demultiplexed into16 parallel samples using Time Division Demultiplexing (TDD)block where each received signal requires two TDD one forthe real part and the other for imaginary. Then, the parallelsamples are applied to FFT function to recover the originalsignal. The implementation of FFT block is similar to IFFTblock except for the twiddle factor becomes conjugate. TheXSG block diagram of FFT is presented in Figure 12.3.3.2DespreadingThe XSG for the dispreading block is shown in Figure 13. Thisblock is implemented using eight complex multipliers thatperform the reverse action of the spreading block. The formatof the output data of each multiplier block is signed, the wordlength is 24 bits with 16 bits for fractional.Fig. 12 XSG block diagram of 16 points decimation in time FFTreceiver.Fig. 9 XSG block diagram of two-users multipath Rayleighfading channel.Fig. 10 XSG block diagram of single user channel.3.3.3Correlator and decision block138IJSTR 2021www.ijstr.orgFig. 13 XSG block diagram of the dispreading block.
INTERNATIONAL JOURNAL OF SCIENTIFIC & TECHNOLOGY RESEARCH VO LUME 10, ISSUE 02, FEBRUARY 2021The correlator block is implemented using 8 subsystems thatcarry out the correlation function between the chaoticreference signal and the chaotic data sequence. Eachsubsystem is implemented using 16 shift registers for the realpart and 16 shift registers for the imaginary part of the signaland one relational XSG block for decision. Each shift registeroutput is fed to a complex addition block where 15 complexaddition blocks must be used in each subsystem. The enablepin in complex addition block is used to start reading theparallel data simultaneously. The result signal is compared to azero value constant using the relational block. The function ofthe relational block is demapping the parallel data. Thecorrelator XSG block is shown in Figures 14 and 15.ISSN 2277-8616registers, and then the multiplexer read out one sample at atime based on the assignment of the counter. The function ofthe delay block is for synchronization and the linear feedbackshift register (LFSR) block has been used as a control signalto enable the registers. The XSG block diagram of the parallelto serial converter is shown in Figure 16.Fig. 16 XSG block diagram of the parallel to serial converterblock.4XSG SIMULATION RESULTSThe XSG simulation time waveforms that describe the outputsof every part in multi-user OFDM-OCVSK system model havebeen plotted using MATLAB program. Figure 17 shows theXSG waveform of the serial to parallel block where the numberof the parallel bits is 8. So, 8 slices are used in this block toobtain 8 parallel bits. The output of the first slice is appeared inthis figure. The XSG simulation waveforms of the mappingblock are shown in figure 18. Every 0 is mapped into -1 andevery 1 is mapped into 1. It is shown in the figure that theparallel data (bit 1) are not mapped until the enable pin turnedinto 1.Fig. 14 XSG block diagram of the correlator and decision block.Fig. 17 XSG simulation waveforms of the serial to parallel block.Fig. 15 XSG block diagram of the subsystem in correlator anddecision block3.3Parallel to serial converterThe parallel demapping samples are converted to serialsamples using this block. It is not obtainable in the XSGlibrary. It has been implemented using 8 registers, delays,LFSR, multiplexer and counter XSG blocks. When the enablepin is activated the parallel samples are latched to theFig. 18 XSG simulation waveforms of the mapping block.139IJSTR 2021www.ijstr.org
INTERNATIONAL JOURNAL OF SCIENTIFIC & TECHNOLOGY RESEARCH VO LUME 10, ISSUE 02, FEBRUARY 2021ISSN 2277-8616Figure 19 presents the XSG simulation waveforms of thespreading and zero padding block where the input data aremultiplied by the chaotic reference signal with spreading factorof (β 16). The XSG simulation waveforms of 16 inputdecimation in time IFFT are presented in figure 20.Fig. 23 XSG simulation waveforms of the despreading block.Fig. 19 XSG simulation waveforms of the spreading and zeropadding block.In Figure 24 the XSG simulation waveform of the parallel toserial block is depicted where the multiplexer is read out onesample each time based on the assignment of the counter.The comparison between transmitted and the received signalwaveforms of the first user has been illustrated in Figure 25.Fig. 20 XSG simulation waveforms of the IFFT blockThe XSG simulation waveforms of the two-users multipathfading channel are illustrated in Figure 21. The waveforms ofthe despreading block and the correlator block are shown inFigures 22 and 23 respectively.Fig. 21 XSG simulation waveforms of the multipath fadingchannel.Fig. 24 XSG simulation waveforms of the parallel to serial block.Fig. 25 Transmitted and received data waveforms of the firstuser.5 SYNTHESIS RESULTSThe VHDL codes or Bit stream file are generated by selectingthe board Kirtex-7 KC 705 evaluation platform 1.1 from theSystem Generator token. Then Vivado Design Suite 2019.1analyze and verify the system at a Register Transfer Level(RTL), to perform synthesis and implementation processes.Many reports (hardware and software) will be produced, thatexplain issues regarding implementation operations like thedevice resources utilization, power consumption, clock andtiming analysis reports. Figures 26 and 27 present theresources utilization for the transmitter and receiver side of the140IJSTR 2021www.ijstr.orgFig. 22 XSG simulation waveforms of the correlator block.
INTERNATIONAL JOURNAL OF SCIENTIFIC & TECHNOLOGY RESEARCH VO LUME 10, ISSUE 02, FEBRUARY 2021ISSN 2277-8616Xilinx Mu-OFDM-OCVSK model, respectivelyFig. 28 Timing analysis report for the transmitter side of XilinxMu-OFDM-OCVSK model.Fig. 29 Timing analysis report for the reciever side of Xilinx MuOFDM-OCVSK model.The power consumption and junction temperature is estimatedby power report based on the inputs of the design. the reportsof power analysis for the transmitter and receiver side designare shown in Figures 30 and 31, respectively. It can be seenfrom these reports that the transmitter side consumes about47% from the total power of the chip, while the receiver sidedesign consumes about 73% from the total power of the chip.This power consumption is divided among the Input/ Outputpins, clocks, signals, and logic with specific rates.Fig. 26 The area of utilization report for the transmitter side ofXilinx Mu-OFDM-OCVSK model.Fig. 30 The report of Power analysis for the transmitter side ofthe OFDM OCVSK model.Fig. 27 The area of utilization report for the receiver side of XilinxMu-OFDM-OCVSK model.The timing analysis reports summary for the transmitter andreceiver sides are illustrated in Figures 28 and 29 respectively.These reports indicate that there is no timing conflict in thedesign.Fig. 31 The report of Power analysis for the receiver side of theOFDM OCVSK model.6 HARDWARE CO-SIMULATIONThe final step of the design is to test the performance of thesystem in a hardware real time. Hardware Co-Simulation is a141IJSTR 2021www.ijstr.org
INTERNATIONAL JOURNAL OF SCIENTIFIC & TECHNOLOGY RESEARCH VO LUME 10, ISSUE 02, FEBRUARY 2021method provided by System Generator to transform thedesigns built using SIMULINK into hardware. The SystemGenerator transfer the design to FPGA target board through―Joint Test Action Group (JTAG)‖ connection to simulate thesystem on the FPGA platform. Then, the output is read backfrom JTAG and transfer again to SIMULINK to compare withsystem generator results. Figures 32, 33 present a photographfor FPGA hardware co-simulation for the MU OFDM OCVSKtransmitter and receiver respectively. The FPGA board used isKintex7 (XC7k325ti-2lffv900) with a JTAG connection. It canbe seen from these figures, that no error between the inputdata and the output from the MATLAB simulation model aswell as the output from the FPGA board which confirm that theproposed system model has been loaded successfully ontothe FPGA board.7 CONCLUSIONIn this paper, Multi-User OFDM based OCVSK system isdesigned and implemented by XSG software tools overmultipath fading channel. The software tools Vivado 2019.1design suite with Xilinx Kintex7(XC7k325ti-2lffv900) board withclock frequency 100 MHz are used in the implementation. Theresults of hardware simulation prove that the system is workedin correct form. The real time operation results show that thesignal is recovered correctly at the receiver side and the VHDLcode file is generated successfulFig. 32 Hardware Co-simulation for the MU OFDM OCVSKtransmitter.Fig. 33 Hardware Co-simulation for the MU OFDM OCVSKreceiver.ISSN 2277-8616REFERENCES[1] Xu W, Wang L, Chen G. ―Performance of DCSKcooperative communication systems over multipath fadingchannels‖, IEEE Transactions on Circuits and Systems I:Regular Papers, vol 58, pp. 196-204, 2010.[2] G. Kaddoum, & F. Shokraneh, ―Analog network coding formulti-user multi-carrier differential chaos shift keyingcommunication system‖, IEEE Transactions on WirelessCommunications, vol 14, pp. 1492–1505, 2015.[3] M. Dawa, G. Kaddoum, Z. Sattar.‖ A generalized lowerbound on the bit error rate of DCSK systems over multipath Rayleigh fading channels‖, IEEE Trans. on CircuitsSyst.-II. ; vol. 65, no. 3, pp. 321-325, March 2018.[4] H. Yang and G. ping Jiang.‖ High-efficiency differentialchaos-shif tkeying scheme for chaos-based non coherentcommunication‖, IEEE Trans. on Circuits and Syst. II: Exp.Briefs, vol 59, pp. 312– 316, 2012.[5] P. Chen, , L. Wang, & G. Chen, ―DDCSK-Walsh coding: que‖, IEEE Transactions on Circuits and Systems II:Express Briefs, vol 59, pp. 128-132, 2012.[6] H. Yang, & G. Jiang, ―Reference-modulated DCSK: anovel chaotic communication scheme‖, IEEE Transactionson Circuits and Systems II: Express Briefs, vol 60, pp.232-236, 2013.[7] W.K Xu, L. Wang, G. A. Kolumbán, ―Novel DifferentialChaos Shift Keying Scheme‖, International Journal ofBifurcation and Chaos., vol 21, pp. 799-814, 2011.[8] G, Kaddoum, & F. Gagnon, ―Design of a high-data-ratedifferential chaos-shift keying system‖, IEEE Transactionson Circuits and Systems II: Express Briefs, vol 59 pp. 448452, 2012.[9] F. Hasan, ―Design and analysis of an orthogonal municationsystem‖, Al-NahrainJournalforEngineering Sciences, vol 20, pp. 952-958, 2017.[10] W . Xu, Y .Tan, F.C. Lau, G. Kolumbán, ― Design andoptimization of differential chaos shift keying scheme withcode index modulation‖, IEEE Transactions onCommunications, vol 66, pp. 1970-1980, Feb. 2018.[11] P. Manhas, M.K Soni, ―OFDM Performance Evaluationunder Different Fading Channels using Matlab Simulink‖,Indonesian Journal of Electrical Engineering andComputer Science, vol 5, pp. 260-266, 2017.[12] H . Al Ibraheemi, M. Al Ibraheemi,―Wirelesscommunication system with frequency selective mmunication, Computing, Electronics and Control,vol 18 pp. 1203-1208, 2020.[13] S . Li, Y . Zhao, & Z. Wu, ―Design and analysis of ion system‖, Journal of communications, vol10, pp. 199-205, 2015.[14] F. Hasan, and A. Valenzuela, ―Design and Analysis of anOFDM-Based Orthogonal Chaotic Vector Shift KeyingCommunication System‖, IEEE Access. Vol 6, pp. 4632246333.[15] Z. Liu, L. Zhang, Z . Wu, J. Bian, ―Carrier InterferometryCode Index Modulation Aided OFDM-Based DCSKCommunications‖, 2019 IEEE 90th Vehicular TechnologyConference (VTC2019-Fall) pp. 1-5, Sep. 22 2019.[16] G. Kaddoum ―Design and performance analysis of amultiuser OFDM based differential chaos shift keying142IJSTR 2021www.ijstr.org
INTERNATIONAL JOURNAL OF SCIENTIFIC & TECHNOLOGY RESEARCH VO LUME 10, ISSUE 02, FEBRUARY 2021ISSN Communications, vol 64, pp. 249-60, 2015.[17] A. M. Abed, and F. S. Hasan, ―Multi-User-OFDM basedOrthogonal Chaotic Vectors Shift Keying CommunicationSystem‖, Journal of Advanced Research in Dynamical &Control Systems,vol 12 pp. 320-329, 2020.[18] F. S. Hasan, ―FPGA based 2 2 MMSE MIMO-OFDMsystem using Xilinx system generator. Journal ofEngineering and Sustainable Development‖, vol 21, pp.152-77, 2018.[19] Vivado Design Suite Tutorial ―Model-Based DSP DesignUsing System Generator‖:UG948 (v2019.1) May 22,(2019).[20] Z. Liu, J. Zhang, H. Liu, ―Design of the differential chaosshift keying communication system based on DSPbuilder‖, Computer Modelling & New Technologies, vol 18,pp. 138-43, 2014.[21] D. S. Ibrahim and F. S. Hassan. ― HardwareImplementation of DCSK Communication System UsingXilinx System Generator,‖ Journal of Engineering andSustainable Development.,First Online ScientificConference for Graduate Engineering Students, June2020[22] R. A. Mohammed, F. S. Hassan and M. J. Zaiter, ―Designand implementation of Haar wavelet packet modulationbased differential chaos shift keying communicationsystem using FPGA,‖ International Journal of AdvancedComputer Research, Vol 8(38) ISSN (Print), pp. 22497277. Sep, 2018.[23] A. Aruna, S. Augusta, ―FPGA Implementation of 32 pointRadix-2 Pipelined FFT‖ International Journal of Researchin Electronics & Communication Technology, Vol. 1, Issue1, pp. 72-77, 2013.143IJSTR 2021www.ijstr.org
Design And Implementation Of Multi-User OFDM Based Orthogonal Chaotic Vector Shift Keying Using FPGA Techniques Ansam M. Abed, Fadhil S. Hassan Abstract: In this paper, an effective design and implementation of the Multi-user orthogonal frequency division multiplexing based orthogonal chaotic vector shift keying (Multi-User OFDM-OCVSK) system .
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