Design & Implementation Of 32-Bit Risc (MIPS) Processor
International Journal of Engineering Trends and Technology (IJETT) – Volume 4 Issue 10 - Oct 2013Design & Implementation Of 32-Bit Risc (MIPS) Processor*Marri Mounika11PGAleti Shankar2Student (M. Tech-ECE), Dept. of ECE, Geetanjali College Of Enginnering & Technology, Hyderabad, AP.Professor, Dept. of ECE, Geetanjali College Of Engineering & Technology, Hyderabad, AP.2AssociateAbstract: In this paper we propose a novel technique of run-time loading of machine code forMIPS-32 soft-core processor. As we know, implementing fewer instructions and addressingmodes on silicon reduces the complexity of the instruction decoder, the addressing logic, andthe execution unit. This allows the machine to be clocked at a faster speed, since less workneeds to be done each clock period. Our proposed RISC MIPS Processor technique sends themachine code to the instruction memory of the soft-core from the software tool through UART.The user should use that software tool to write MIPS assembly code, debug the code andgenerate the machine code. Also, the software tool is used for establishing UART connection.Keywords: MIPS, Data Flow, Data Path, Pipeline, RISC, CISC.single-chip1. Introductiondesigns,somehigh-Processors are regarded as one of theperformance designs rely on a few chipsmost important devices in our everydayto provide multiple functional units andmachines called computers. Before werelatively large caches.start, we need to understand what exactlyprocessorsareandtheirappropriateProcessors have been described inmany different ways. They have beenancompared with the brain and the heart ofelectronic circuit that functions as thehumans. Their operation has been likedcentralato a switched board, and to the nervouscomputationalsystem in an animal. They have oftencontrol. Processors are also used in otherbeen called microcomputers. The originaladvanced electronic systems, such aspurpose of the processor was to controlcomputer printers, automobiles, and jetmemory. That is what they were originallyairliners, Calculators and etc.designed to do, and that is what they hmetic and logic functional units aswellastheassociated controllogic,today. Specifically, a processor is “acomponent that implements memory.”Processorsmuchportion of the memory hierarchy. Portionsclocked at 100 MHz would like to accessof the interface logic for the input/outputmemory in 10 nanoseconds, the period of(I/O) and memory subsystems may alsoits 100 MHz clock. Unfortunately, thebeoverallmemory interfaced to the processor mightsystems. While many processors andrequire 60 nanoseconds for an access.ISSN: mories.allowingexample,fasterinstruction processing circuitry, and ainfused,ForareprocessorPage 4466
International Journal of Engineering Trends and Technology (IJETT) – Volume 4 Issue 10 - Oct 2013So, the processor ends up waiting duringperformance the same way a memoryeach memory access, wasting executionaccess does. A complex calculation maycycles.require the use of several data values. IfTo reduce the number of accesses tothe data values all reside in memoryduring the calculations, many memorytheaccesses must be used to utilize them. Ifprocessors. A cache is a special type ofthe data values are stored in the internalhigh speed RAM where data and theregisters of the processor instead, theiraddress of the data are stored. Wheneveraccess during calculations will be muchthe processor tries to read data from mainfaster.memory, the cache is examined first.internal registers.Ifone of the addresses stored in the cacheIt is good then to have lot of2. THE MIPS PROCESSORmatches the address being used for theThe MIPS instruction set architecturememory read (called a hit), the cache will(ISA) is a RISC based microprocessorsupply theisarchitecture that was developed by MIPScommonly ten times faster than mainComputer Systems Inc. in the earlymemory, so you can see the advantage of1980s. MIPS is now an industry standardgetting data in 10 nanoseconds instead ofand the performance leader within the60 nanoseconds.Only when we missembedded industry. Their designs can be(i.e., do not find the required data in thefound in Canon digital cameras, Windowscache), does it take the full access time ofCE devices, Cisco Routers, Sony Play60 nanoseconds.But this can onlyStation 2 game consoles, and many moreSince a copy of the newproducts used in our everyday lives. Bydata is written into the cache after a miss.the late 1990s it was estimated that oneThe data will be there the next time wein three of all RISC chips produced was aneed it. Instruction cache is used to storeMIPS-based design.frequently used instructions. Data cacheArchitecturedata instead.happen once.Cacheis used to store frequently used data.Implementing fewer instructions ightforwarddecodedinstructionaddressing modes on silicon reduces theformat, memory accesses limited to loadcomplexity of the instruction decoder, theand store instructions, hardwired controladdressing logic, and the execution unit.unit, a large general purpose register file,This allows the machine to be clocked atand all operations are done within thea faster speed, since less work needs toregisters of the microprocessor.be done each clock availableDue to these design characteristics,typicallyinISSN: recoursesinuniversity and technical schools ythePage 4467MIPS
International Journal of Engineering Trends and Technology (IJETT) – Volume 4 Issue 10 - Oct 2013architecture. One of the most widely usedand always contains the value zero. The CPUtools that helps students understanduses byte addressing for word accesses andMIPS is SPIM (MIPS spelled backwards) amust be aligned on a byte boundary divisiblesoftware simulator that enables the userby four (0, 4, 8, ). MIPS only has threetoassemblyinstruction types: I-type is used for the Loadlanguage programs and execute them.and Stores instructions, R-type is used forSPIM is a great tool because it allows theArithmetic instructions, and J-type is useduser to execute programs one step orfor the Jump instructions as shown in Figureinstruction at a time. This then allows the1 which provides a description of each of theuser to see exactly what is happeningfields used in the three different instructionduring their program execution. SPIMtypes.readandwriteMIPSalso provides a window displaying allMIPSisaload/storearchitecture,general purpose registers which can alsomeaning that all operations are performed onbe used during the debug of a program.operands held in the processor registers andThis simulator is another impressive toolthe main memory can only be accessedthatarchitecturethrough the load and store instructions (e.gtolw, sw). A load instruction loads a value bserve how the MIPS processor works.memory into a register. A store instructionstores a value from a register to memory. Theload and store instructions use the sum ofI - Type instruction31655Opcoders116rt0n/offsetthe offset value in the address/immediatefield and the base register in the rs field toaddress the memory. Arithmetic instructionsor R-type include: ALU Immediate (e.g. addi),three-operand (e.g. add, and, slt), and shiftR - l,srl).TheJ-typeinstructions are used for jump instructions(e.g. j). Branch instructions (e.g. beq, bne) areI-type instructions which use the addition ofJ - Type626the address/immediate field along with theOpcoderaddrprogram counter (PC) to compute the branchan offset value from the current address intarget address; this is considered PC-relativeFigure 1 Instruction FormatsAs mentioned before MIPS is a rchitecture defines 32-bit general purposeregisters (GPRs). Register r0 is hard-wiredISSN: 2231-5381http://www.ijettjournal.orgPage 4468
International Journal of Engineering Trends and Technology (IJETT) – Volume 4 Issue 10 - Oct 20133. MIPS SINGLE-CYCLE PROCESSORresult or memory value back to theIMPLEMENTATIONTheMIPSsingle-cyclememory. The final step writes the ALUprocessorregister file.performs the tasks of instruction fetch,instruction decode, execution, memoryaccess and write-back all in one clockcycle. First the PC value is used as anaddress to index the instruction memorywhich supplies a 32-bit value of the edintoThisthedifferent fields shown in fig. 1. TheFigure 2 The MIPS Processorinstructions opcode field bits [31-26] aresent to a control unit to determine theThe initial task of this paper was totype of instruction to execute. The type ofimplement in VHDL the MIPS single-cycleinstruction then determines which controlprocessor .A good VHDL reference andsignals are to be asserted and whattutorial can be found in the appendices tofunction the ALU is to perform, thusthe book Fundamentals of Digital Logicdecoding the instruction. The instructionwith VHDL Design by Stephen Brown andregister address fields rs bits [25 - 21], rtZvonko Vranesic [2]. The IEEE Standardbits [20 - 16], and rd bits [15-11] are usedVHDL Language Reference Manual [3],to address the register file. The registeralso helped in the overall design of thefile supports two independent registerVHDL implementation. The first part ofreads and one register write in one clockthe design was to analyze the single-cyclecycle. Thedatapath and take note of the majorregister file reads in therequested addresses and outputs the datafunctionunitsvalues contained in these registers. Theseconnections.andtheirrespectivedata values can then be operated on byThe MIPS implementation as with allthe ALU whose operation is determined byprocessors, consists of two main types ofthe control unit to either compute alogicmemory address (e.g. load or store),sequentialcompute an arithmetic result (e.g. add,elements are elements that operate onand or slt), or perform a compare (e.g.data values, meaning that their outputsbranch). If the instruction decoded isdepend on the current inputs. Sucharithmetic,beelements in the MIPS implementationwritten to a register. If the instructioninclude the arithmetic logic unit (ALU)decoded is a load or a store, the ALUandresult is then used to address the dataelements that contain a hold state. EachtheISSN: ombinationalelementsPage 4469are
International Journal of Engineering Trends and Technology (IJETT) – Volume 4 Issue 10 - Oct 2013state element has at least two inputs and32 bytes of memory space. This easily fitsone output. The two inputs are the datainto one 256 x 8 EAB within the FPGA.value to be written and a clock signal. TheThe full 32-bit version of MIPS will requireoutput signal provides the data valuescombiningthat were written in an earlier clock cycle.implement the register file. The registerStateMIPSfile has two read and one write inputimplementation include the Register File,ports, meaning that during one clockInstruction Memory, and Data Memory ascycle, the processor must be able to readseen in Figure 2. While many of logictwo independent data values and write aunits are straightforward to design andseparate value into the register file. Figureimplement in VHDL, considerable effort3 shows the MIPS register file. Thewasregister file was implemented in VHDL our256x8EABstodeclaring it as a one-dimensional array ofIt was determined that the full 32-bit32 elements or registers each 8-bits wide.version of the MIPS architecture would(e.g. TYPE register file IS ARRAY (0 TOnot fit onto the chosen FLEX10K70 FPGA.31) OF STD LOGIC VECTOR (7 DOWNTOThe FLEX10K70 device includes nine0) ) By declaring the register file as a one-embeddedeachdimensional array, the requested registerproviding only 2,048 bits of memory for aaddress would need to be converted intototal of 2 KB memory space. The full 32-an integer to index the register file.(e.g.bit version of MIPS requires no less thanRead Data 1twelve EABs to support the processor’sCONV INTEGER (read register address1register file, instruction memory, and data(4 DOWNTO 0))) Finally, to save frommemory. In order for our design to modelhaving to load each register with a value,that in [1], the data width was reduced tothe8-bit while still maintaining a full 32-bitrespectiveinstruction. This new design allows us toReset signal is asserted. (e.g. r1 1, r2 implement all of the processor’s state2, etc.)arrayblocks(EABs)registers getregisterregister fileinitializednumbertowhenelements using six EABs, which can behandled by the FLEX10K70 FPGA device.Even though the data width was reduced,the design has minimal VHDL sourcemodifications from the full 32-bit version,thusnotimpactingtheinstructionalvalue of the MIPS VHDL model.With our new design, the register fileis implemented to hold thirty-two, 8-bitgeneral purpose registers amounting toISSN: 2231-5381Figure 3 MIPS Register FileINSTRUCTION FETCH UNIThttp://www.ijettjournal.orgPage 4470(theirthe
International Journal of Engineering Trends and Technology (IJETT) – Volume 4 Issue 10 - Oct 2013The function of the instruction fetchbe implemented in VHDL include severalunit is to obtain an instruction from themultiplexers and the register file that wasinstruction memory using the currentdescribed earlier.value of the PC and increment the PCvalue for the next instruction as shown inFigure 4. Since this design uses an 8-bitdata width we had to implement byteaddressing to access the registers andword address to access the instructionmemory. The instruction fetch componentcontains the following logic elements thatare implemented in VHDL: 8-bit programcounter(PC)register,anaddertoincrement the PC by four, the instructionmemory, a multiplexer, and an AND gateused to select the value of the next PC.Figure 5 Instruction Decoding UnitTHE CONTROL UNITThe control unit of the MIPS singlecycle processor examines the instructionopcode bits [31 – 26] and decodes theinstructiontogenerateninecontrolsignals to be used in the additionalFigure 4 Instruction Fetch Unitmodules as shown in Figure 6. TheINSTRUCTION DECODE UNITRegDst control signal determines whichThe main function of the instructionregister is written to the register file. The32-bitJump control signal selects the jumpinstruction provided from the previousaddress to be sent to the PC. The Branchinstruction fetch unit to index the registercontrol signal is used to select the branchfile and obtain the register data values asaddress to be sent to the PC. Theseen in Figure 5. This unit also signMemReadextends instruction bits [15 - 0] to 32-bit.during a load instruction when the dataHowever with our design of 8-bit datamemory is read to load a register with itswidth,thememory contents. The MemtoReg controlinstruction bits [7 – 0] bits instead of signsignal determines if the ALU result or theextending the value. The logic elements todata memory output is written to lsignalisassertedregister file. The ALUOp control signalsISSN: 2231-5381http://www.ijettjournal.orgPage 4471
International Journal of Engineering Trends and Technology (IJETT) – Volume 4 Issue 10 - Oct 2013determine the function the ALU performs.multiplexer, an adder, the ALU and the(e.g. and, or, add, sbu, slt) The MemWriteALU control as shown in Figure 2 & 7control signal is asserted when during astore instruction when a registers value isstored in the data memory. The ALUSrccontrol signal determines if the ALUsecond operand comes from the registerfile or the sign extend. The RegWritecontrolsignalisassertedwhentheregister file needs to be written. Table 1shows the control signal values from theinstruction decoded.Figure 7 MIPS Execution UnitDATA MEMORY UNITTheFigure 6 MIPS Control nstructions. The load instruction assertsTable 1 MIPS Control Signalsthe MemRead signal and uses the ALUResult value as an address to index thedata memory. The read output data isthenexecutionunitoftheMIPSprocessor contains the arithmetic logicunit (ALU) which performs the operationdetermined by the ALUop signal. Thebranch address is calculated by addingthe PC 4 to the sign extended immediatefield shifted left 2 bits by a separateadder.TheimplementedISSN: 2231-5381writtenintotheregister file. A store instruction assertsExecution UnitThesubsequentlylogicinelementsVHDLtoincludethe MemWrite signal and writes the datavalue previously read from a register intothecomputedmemoryaddress.TheVHDL implementation of the data memorywas described earlier. Figure 8 shows thesignals used by the memory unit toaccess the data memory.beahttp://www.ijettjournal.orgPage 4472
International Journal of Engineering Trends and Technology (IJETT) – Volume 4 Issue 10 - Oct 2013system we could get a statistical dataaboutthenumberofinput-outputbuffers, the number of registers, numberof flip-flops and latches were used erator,InstructionRegister, Multiplexer, Program Counter,Reset, Control Logic Decoder, ArithmeticLogic Unit and the overall system. Fewinstructions wereexecutedand theirFigure 8 MIPS Data Memory Unittiming sequences were analyzed. It is4. Results and Conclusionsfound that an each instruction takenThe work presented in this paperdescribes a functional implementation100ps.It shows that the different operation ofandthe instruction including the decodingpipelined processor designed using VHDL.and execution comes to 40ns in theThe VHDL designs of the MIPS processoroverall system. Therefore we concludewere all simulated to ensure that thethat the behavior shows, the system isprocessors were functional and operatedworking as MIPS as instruction will bejustexecuted within a single clock onandHennessy. The results show first theinstruction memory initialization, whichis used to fill the instruction memory withthe instructions to be executed, which areindexed by the program counter (PC). Thesecond is the actual 32-bit instructionrepresented using hexadecimal numbers.The third is the PC value used to indexthe instruction memory to retrieve aninstruction. The next four columns aretheMIPSinstruction’smnemonicdescription. Finally last columns are thepseudo instructions using theactualvalues used during the simulation.From This Work it is observed that theMIPS based system is simulated usingVHDL. The overall system is simulatedand synthesized, after synthesizing theISSN: 2231-5381http://www.ijettjournal.orgFigure 9 Simulation ResultsPage 4473
International Journal of Engineering Trends and Technology (IJETT) – Volume 4 Issue 10 - Oct 2013[4] Xizhi Li and Tiecai Li, "ECOMIPS: aneconomic MIPS CPU design on FPGA," inProc.ofthe4thIEEEInternationalWorkshop on System-on- Chip for RealTime Applications, pp. 291-294, 2004.[5] D. M. Harris and S. L. Harris, DigitalDesignandComputerArchitecture,1stedition, Morgan Kaufmann, 2007, USA.[6] Balpande, R.S. and Keote, R.S., "Design ofFPGA based Instruction Fetch & DecodeFigure 10 SchematicModule of 32-bit RISC (MIPS) Processor," msandonNetworkTechnologies, pp. 409-413, 2011.[7] MIPSTechnologies,Inc.MIPS32 Architecture For Programmers Volume II:The MIPS32 Instruction Set June 9,2003.Figure 11 RTL SchematicAuthors Profile:Marri Mounika is Pursuing M.AcknowledgementsTech from Geetanjali College OfThe authors would like to thank theEnginnering & Technology, JNTUHanonymous reviewers for their commentswith specialization in Electronics &which were very helpful in improving theCommunicationsquality and presentation of this paper.Engineering(ECE).References:[1] Zheng-WeiMin, Tang-ZhiZhong. ComputerSystem Structure (The second edition),Aleti Shankar is working as anTsinghua University Press, 2006.Associate[2] Pan-Song, Huang-JiYe, SOPC TechnologyinElectronics & CommunicationUtility Tutorial, Tsinghua University e of Engineering & Technology, A.P,[3] Ramdas, T. Li-Minn Ang and Egan, G.,and India. He received Masters Degree in"FPGA implementation of an integer MIPSSystems and Signal Processing from JNTUHprocessor in Handel-C and its applicationA.P India. He has 10years of Teachingto human face detection," in Proc. of IEEEExperience and his interesting fields are lowRegion 10 Conference, Vol. 1, pp. 36-39,power2004.Processing and Speech Processing.ISSN: essing,Page 4474Image
with VHDL Design by Stephen Brown and Zvonko Vranesic [2]. The IEEE Standard VHDL Language Reference Manual [3], also helped in the overall design of the VHDL implementation. The first part of the design was to analyze the single-cycle datapath and take note of the major function units and their respective connections.
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