Making Use Of Semiconductor Manufacturing Process Variations: FinFET .
Analog Integr Circ Sig Process (2017) 93:429–441DOI 10.1007/s10470-017-1053-9Making use of semiconductor manufacturing process variations:FinFET-based physical unclonable functions for efficient securityintegration in the IoTVenkata P. Yanambaka1 Saraju P. Mohanty1 Elias Kougianos2Received: 22 April 2017 / Revised: 4 September 2017 / Accepted: 2 October 2017 / Published online: 7 October 2017 Springer Science Business Media, LLC 2017Abstract In a typical design environment, semiconductormanufacturing variations are considered as challenges fornanoelectronic circuit design engineers. This has led tomulti-front research on process variations analysis and itsmitigations. As a paradigm shift of that trend the presentarticle explores the use of semiconductor manufacturingvariations for enhancing security of systems using FinFETtechnology as an example. FinFETs were introduced toreplace high-j transistors in nanoelectronic applications.From microprocessors to graphic processing units, FinFETs are being used commercially today. Along with thetechnological advancements in computing and networking,the number of cyber attacks has also increased. Simultaneously, numerous implementations of the Internet ofThings are already present. In this environment, one smallsecurity flaw is enough to place the entire network indanger. Encrypting communications in such an environment is vital. Physical unclonable functions (PUFs) can beused to encrypt device to device communications and arethe main focus of this paper. PUFs are hardware primitiveswhich rely on semiconductor manufacturing variations togenerate characteristics which are used for this purpose.Two different designs of a ring oscillator PUF are& Saraju P. Mohantysaraju.mohanty@unt.eduVenkata P. Yanambakavy0017@unt.eduElias Kougianoselias.kougianos@unt.edu1Computer Science and Engineering, University of NorthTexas, Denton, TX 76203, USA2Engineering Technology, University of North Texas, Denton,TX 76203, USAintroduced, one with low power consumption trading offdevice performance and one high-performance trading offdevice power consumption. There is an 11% decrease inpower consumption with the low power model along with asimple design and fabrication. Performance of the devicecan be increased with almost no increase in powerconsumption.Keywords FinFET Process variation Physicalunclonable function (PUF) Internet of Things (IoT) Security Encryption1 IntroductionThe first general purpose programmable microprocessor,the Intel 4004 was released in April 1970. It was used incalculator manufacturing and had 2250 transistors integrated in it [12]. It was manufactured in a 10 lm technology. After its release, the need for more powerfulmicroprocessors grew and research progressed in thatdirection at a rapid rate. In 1975, Gordon Moore predictedthat the number of transistors in an Integrated Circuit (IC)will double every two years, which became known asMoore’s law and has held for the next half century. This ispossible with rapid technology scaling and integration, butthere were some hurdles in the process. Until transistorsreached 90 nm technology, there were fewer issues withscaling. Beyond 90 nm, the channel length reduction gaverise to short channel effects. Leakage and other performance issues in transistors were more pronounced whentechnology reached the 45 nm mark [5]. The dielectricmaterial had to change to allow for more scaling. Hence ahigh-j material was used which caused charge carrierscattering when used with the usual poly-Si gate and a123
430metal gate was used instead. Thus, high-j Metal Gatetransistors were born. But this solution was temporary.From 22 nm downwards, the high-j Metal Gate combination could not be used. To address this issue planartransistors were transformed into a 3D structure.Fin Field Effect Transistors were introduced to reducethe leakage caused due to the short channel effects and therapid transistor scaling. The structure of a FinFET with 3Fins is shown in Fig. 1. Compared to a planar transistor,the source and drain of the FinFET are projected into thethird dimension. The protruded source and drain into thegate look like fins and hence the name FinFETs [16]. Thefin itself in a three dimensional structure that acts aschannel. Hence the width of the channel of the transistor isequal to twice the height of the fin. The respective channelwidth to length ratio is increased which acts as a solution tothe short channel effects. The gate also wraps on the fin,which is the channel. This gives more control over thecharge carriers flowing through the channel. FinFETs areconsidered a reliable solution for the scaling problem.Currently FinFET manufacturing has reached the 14 nmtechnology node [19] and is available in commercialmarkets.High performance device design is growing with theintroduction of FinFETs. Newer processors include around8 billion transistors compared to the 2250 in the 4004.Along with transistor scaling, another area attractingresearch is the Internet of Things (IoT). A simple implementation of an IoT environment could be a network ofdevices communicating with each other to reduce humaninvolvement in everyday activities as much as possible.The IoT is considered as one of the six most ‘‘DisruptiveCivil Technologies’’ by the US National IntelligenceCouncil [20]. Figure 2 presents an example of the IoTactively working in a home environment. The Iot mainlyincreases the quality of life and simplifies many activitieswith automation and networking [3, 16]. Radio FrequencyIdentification (RFID), mobile phones, sensors, etc. startedthe device to device communication. That marked thebeginning of the IoT. Devices are already being implemented where a single button can order goods onlineFig. 1 Structure of FinFET with three fins123Analog Integr Circ Sig Process (2017) 93:429–441CloudServicesHealthElectricitySecured Using PUF(Due to ProcessVariations)TransportationMedia PlayerTabletFig. 2 Internet of things at homeautomatically. The ‘‘Internet of Things’’ term is accreditedto ‘‘The Auto-ID Labs’’, a network of academic laboratories in this field. The IoT environment is already implemented in many areas [17].The rest of the paper is organized as follows: Sect. 2explains how manufacturing variations are taken advantageof to design physical unclonable functions (PUFs), andSect. 3 presents the novel contributions of the paper. Section 5 gives an overview of the designs proposed and Sect.6 presents the circuit level design of a Hybrid ArbiterOscillator PUF. Simulation results are presented in Sect. 7and conclusion and directions for future research are presented in Sect. 8.2 Use of manufacturing process variationsfor PUF based security: the big pictureWith all IoT devices potentially communicating with eachother, there is a great possibility of malicious attacks.Cyber attacks are increasing daily. In a household, almostall devices will be connected to a network and a smallvulnerability is sufficient for an attacker to gain access andtake control. This might endanger the entire household.Sometimes the devices are deployed in areas where theycan be easily accessed by the attacker [8]. In such devices,if the cryptographic key is stored in non Non-VolatileMemory (NVM), it can be easily obtained by the attacker.Hence, an alternative to the key storage in memory should
Analog Integr Circ Sig Process (2017) 93:429–441431Manufacturing Variations(e.g. Oxide Growth, Ion Implantation, Lithography)0 10-4-0.2Ids (A)-0.4-0.6-0.8-1-1.200.20.40.60.81Vgs (V)Fig. 4 N-type FinFET I–V characteristics with process variationtaken into account0.80.70.60.5Vout (V)be implemented. A PUF is a proven alternative in suchcase.A PUF is a circuit that takes advantage of manufacturingvariability to uniquely form random characteristicsbetween input and output [28]. Manufacturing variationsare inevitable in any fabrication process and these physicalvariations in the circuit will be unique for each device.Therefore, the behavior of each device will be unique forthe same given input. The input and output of a PUF arecalled collectively the challenge response pair (CRP).Figure 3 shows the working characteristics of a PUF. Themanufacturing variations naturally occur in the transistor orany other devices produced during the fabrication process.In the case of Fig. 3, a FinFET with three fins is shown,which is subjected to manufacturing variations. With thosedevices, different circuits are designed, such as StaticRAMs (SRAMs) or ring oscillators (ROs). A PUF based onthese designs is manufactured. The PUF takes in challengeinputs and gives out responses for those challenge inputs.The CRP for two RO PUFs will be different even if thechallenges are the same. Hence a key need not be stored; itwill be generated anytime needed and due to the highnumber of CRPs, even if the attacker has access to thedevice itself, it will be difficult to get the key needed todecrypt the communication between the client and theserver.Process variations are inevitable in the fabrication of anydevice, especially transistors. Process variations can occurat different stages of fabrication, such as implantation,photolithography, oxidation or deposition. Due to thesemanufacturing variations, the geometry of the device isaffected which will cause changes in the output of thedevice itself [1]. Figure 4 shows the I–V characteristics ofan n-Type FinFET with process variations. Subsequently,an inverter is designed with these FinFETs and is subjectedto DC Monte Carlo simulations. Figure 5 shows the DCtransfer characteristics of such an inverter under manufacturing variations. The dimensions of the n- and p-type0.40.30.20.1000.20.40.60.81Vin (V)Fig. 5 Inverter DC transfer function Monte Carlo simulation resultsChallenge Inputs(Inputs given to PUF Module, e.g. Select line of Multiplexer)ParametersAffected Dueto Variations(e.g. Length,Gate-OxideThickness,Fin Height,Fin Width)PUF Modules(Arbiter PUF, SRAM PUF,Ring Oscillator PUF)Challenge Response(Outputs from a PUF Module)Random Binary Output010101 Fig. 3 Working characteristics of the physical unclonable function123
432Analog Integr Circ Sig Process (2017) 93:429–441FinFETs used for these simulations are shown in Table 3,and further discussion is given in Sect. 5.3. For the MonteCarlo simulations, a variation (standard deviation) of 5%of the mean (r ¼ 0:05 l) and a Gaussian distribution forthe geometric dimensions was assumed. A total of 500Monte Carlo runs were performed. From the simulations,it is clear that even if the design of the inverter is thesame, under process variations there can be a significantchange in the device characteristics and the input–outputrelationship. A PUF uses the same concept to producedifferent CRPs. Various PUF designs are available basedon the architecture used, such as SRAM PUF, MemristorPUF, ring oscillator PUF, etc. A PUF generates an outputkey which can be used in cryptographic applications. Theadvantage is that the same key cannot be generatedwithout the device itself. Hence in an IoT environmentwhere the client device is not monitored regularly, thiscan be used to generate a key for communication orauthentication purposes. PUFs are also used in IP protection where a challenge response pair is generated bythe manufacturer to validate the authenticity of the device[8].3 Novel contributions of this paperThe encryption key is generated by a PUF and is used toencrypt the end-to-end communications. The mainadvantage of the PUF is that the key is not stored anywherein memory. Different types of PUF designs are availablefor use in the IoT [26]. An RO based PUF is used in thispaper. Compared to other PUF designs, the RO PUF willbe easy to manufacture. The main advantage of the proposed RO PUF in this paper over the other PUF designs isthat less area is needed and with N ring oscillators, N bitscan be obtained, unlike other designs. Hence, power consumption can be much lower for generating the samenumber of bits. Two different PUF designs are presented,one which can be ideal for small devices like smartwatches and another which is ideal for high speeddemanding devices like routers and network adapters. Thenovel contributions of this paper are the following twodistinct designs: A novel energy-optimal hybrid oscillator arbiter PUF.A novel speed-optimal hybrid oscillator arbiter PUF.The current paper is an extension of the work presented in[29]. 14 nm technology FinFETS are used in the currentpaper in contrast to 32 nm FinFETs used in [29]. The useof the 14 nm technology gives an advantage in powerconsumption and chip area reduction and is more in linewith current state-of-the-art manufacturing processes.1234 Related prior researchFinFETs have proven to be a promising replacement to theplanar transistors with less leakage and more scalabilitybeyond the 32 nm regimes. Now the FinFET has reached14 nm in commercially available processors and devices[19]. But one of the main issues in scaling the devicesbeyond 20 nm is the device to device manufacturingvariations. At such small transistor sizes, there will bemany factors contributing to the variations. A study of theprocess variation effects on sidewall roughness effects waspresented in [1]. Computer Aided Design models in 3Dwere used for the simulation of devices and the deviceswere subjected to Monte Carlo variations and results werepresented in [1]. To study the impact of these variations onmemory devices, 6T and 10T Static Random AccessMemory (SRAM) cells were designed and simulationresults were presented in that paper. The impact of processvariation of nanotube devices and nanowire devices ispresented in [22]. A 128 Mb high density 6T SRAM wasfabricated and presented in [25]. The SRAM was fabricatedusing the 14 nm FinFET technology and the proposeddesign of the SRAM shows a significant reduction in powerconsumption. This reduction in power consumption can bevery helpful in the case of a battery operated applications.In [16], many of the circuits were subjected to Process,Voltage and Temperature (PVT) variation analysis,including memory and oscillators. For the current paper, a15 nm FinFET PDK released by NCSU [4] is used.Different implementations of the IoT are presented in[3]. With the efficient use of cloud services, the storage andanalysis of data provided by various IoT devices and sensors has become easier [11]. Implementation of an energyefficient and user friendly architecture for the healthindustry and the IoT were presented in [27]. A thyroidmonitoring system that is dynamically optimized wasproposed in that paper. The IoT is also used in surveillance.One such application is presented in [10] which proposesan architecture for secure imaging.Many types of PUF designs are available such asreconfigurable PUF, ring oscillator PUF, arbiter PUF,SRAM PUF, etc. [7, 9, 26]. Various architectures atnanoscale used to design a PUF are presented in [8]. Animplementation of a PUF using the variability of RRAM ispresented in [6] but its functionality is affected by voltageand temperature variations. A reconfigurable PUF usingring oscillators is presented in [14]. A new design toaddress aging and environmental effects affecting the PUFreliability is presented in [23]. In [2], a protocol forauthenticating different devices connected in an IoT network to avoid various types of attacks is proposed. Different security problems in the IoT are described in [21].
Analog Integr Circ Sig Process (2017) 93:429–441433An elliptic curve based protocol was proposed using thePUF in [28]. In that paper, the PUF was designed on anFPGA and the proposed algorithm was implemented. Anelliptic curve based protocol that is secure and also fast ispresented in [28].consumed is large compared to the ring oscillator designs.The power consumed is also comparatively high. Toovercome these, the two designs of Hybrid OscillatorArbiter PUF are proposed. The main advantage of thisarbiter PUF is that from a single PUF module various keyscan be generated.5 Proposed physical unclonable function designs5.2 Traditional ring oscillator PUF designIn this section we present two novel designs of RO PUF,one being high performance and the other being low power.These are ideal for the two types of devices that are presentin the IoT environment. The power optimized HybridOscillator Arbiter PUF is useful in low power consumingdevices where the battery capacity is limited, for examplein a smart-watch. The speed optimized Hybrid OscillatorArbiter PUF is useful where there are no constraints onpower consumption and where there is a need for highspeed, for example in network routers and controllers. Eachof the designs is used in different domains and is ideal forthe conditions that are mentioned.The design of a FinFET based traditional RO PUF is shownin Fig. 7 [15]. The ring oscillators will generate therequired oscillations which are given to the inputs of amultiplexer. Due to the process variations, the frequency ofthe generated oscillations will be different in each of thering oscillators. As shown in the figure, the outputs from N/2 oscillators are given to one multiplexer, MUX1 and theoutputs from the other N/2 oscillators are given to the othermultiplexer MUX2. At a given time, two of the differentring oscillators are selected and the pulse signals generatedare counted. The counted numbers are given to a comparator which compares the number of signals generated upto that respective point of time and gives the outputaccordingly as ‘‘1’’ or ‘‘0’’. A 16-bit FinFET based traditional RO PUF was implemented and its characterizationwas performed. The transistor sizing and results are tabulated in Table 1. The relative sizing of the transistors wasmade to ensure a smooth current flow through the invertersand symmetrical transfer characteristics. In a traditionalRO PUF, generating the key will take time as pairs of ringoscillators are to be selected and the signals are to be givento the counter for some time to count the number of pulsesgenerated and then compared. This lag in generation can beavoided in the proposed PUF design presented next.Figure 7 shows the design of a FinFET based traditionalring oscillator PUF. The ROs generate the required oscillations. The generated pulse waves, due to the manufacturing variations of the transistors, will have differences intheir frequencies. N ring oscillators are used where N/2 ring5.1 Traditional multiplexer arbiter PUFThe Hybrid Oscillator Arbiter PUF is similar to the ArbiterMultiplexer PUF. The design of a traditional one bit arbiterPUF is shown in Fig. 6: a number of multiplexers areconnected in series as presented. The output from twomultiplexers is fed to the clock and input signals of a latch.The gate delays produced by the transistors will produce atime delay between the two signals. This time periodvariation between the signals will produce different outputsfrom the D flipflop. If the signal given to the clock reachesbefore the signal given to the input, the output will be high(1). If the signal given to the clock is slow compared to thesignal given to D, the output will be low (0). The signalsX½0 ; . . .; X½N are the select signals (or the challenges)given to the multiplexers. However, the chip areaFig. 6 One bit arbiter PUF123
434Analog Integr Circ Sig Process (2017) 93:429–4412Fig. 7 Traditional RO basedPUFTable 1 Characterization table for traditional PUFParameterValueTransistor sizesp-type (W:L)n-type (W:L)90 nm:20 nm45 nm:20 nmAverage power248 lWHamming distance50%Time to generate key150 ns (varies with frequency of RO)oscillators are given to Multiplexer 1 and the other half areconnected to Multiplexer 2. Two signals from each set areselected and compared with each other which gives theoutput 1 or 0.The 16 bit FinFET based PUF was implemented, whichrequires 32 ring oscillators. To check the uniqueness andreliability of the PUF, inter- and intra-distance PUF challenges were performed and the Hamming distance wascalculated to test the uniqueness. The inter-distance PUF ofthe implemented FinFET PUF is 0.500 (50%) which is theideal Hamming distance. To calculate the inter-distance,the same challenge was given to two different PUFs andthe outputs are compared. To calculate the intra-distance,the same challenge was given to the same PUF moduleover and over again to check any variations in the outputkey generated. Temperature and supply voltage fluctuations were taken into consideration to confirm that theintra-distance challenge gives out the same key.5.3 Proposed energy-optimal hybrid oscillatorarbiter PUFThe design of the FinFET based power optimized HybridOscillator Arbiter PUF is shown in Fig. 8. Like the traditional RO PUF design, the ring oscillators will generate thenecessary oscillations. Due to process variations, the123frequency of the generated oscillations will be different ineach of the ring oscillators. In this case, to conserve energyand create a low power environment, a multiplexer isemployed. As in the traditional RO PUF design, N/2 ringoscillators are given as inputs to multiplexer MUX1. Theother half are given to the other multiplexer MUX2. Theoutput from MUX1 is given as the input to the D flipflop.The output from MUX2 is given as the clock signal to theD flipflop. Depending on the different frequencies of ringoscillators, the output will be ‘‘1’’ or ‘‘0’’. In this case, toobtain the key will take more time than the speed optimized Hybrid Oscillator Arbiter PUF as pairs of ROs areselected and given to the D flipflop. The power optimizedHybrid Oscillator Arbiter PUF is characterized and thevalues are tabulated in Table 2.5.4 Proposed speed-optimal optimized hybridoscillator arbiter PUFThe design of the FinFET speed optimized Hybrid OscillatorArbiter PUF is shown in Fig. 9. Due to process variations,the frequency of the generated oscillations will be differentin each ring oscillator. In this design, the signals generatedby the RO are not given to the multiplexers, but are given tothe D-input and clock signal input of the D flipflop. In thiscase, the design may become complex compared to theprevious designs due to the routing that should be followed.The signal of one RO is given as D-input and the signal fromanother RO is given as a clock to the same D flipflop.Depending on the frequencies of the two RO signals, theoutput bit will be ‘‘1’’ or ‘‘0’’. The output bits are taken aftera time period of 50 ns in this experiment. To achieve morebits from the same design, two outputs can be taken from the In such a configuration, forflipflop outputs, Q and Q.N different ring oscillators, an N-bit key can be obtained.
Analog Integr Circ Sig Process (2017) 93:429–4414352Fig. 8 Novel power optimizedhybrid oscillator arbiter PUFTable 2 Characterization table for power optimized hybrid oscillatorarbiter PUFParametersValuesTransistor sizesp-type (W:L)n-type (W:L)90 nm:20 nm45 nm:20 nmAverage powerHamming distance219.34 lW48.51%Time to generate key150 ns (varies with frequency of RO)6 FinFET based design of the physical unclonablefunctionsIn the multiplexer arbiter PUF design, the gate delay of themultiplexers produces a time delay for the signals reachingthe latch at the end. Similar to this, in the design of theHybrid Oscillator Arbiter PUF, two ring oscillators areconnected to the input and the clock of the D flipflop. Dueto the process variation in the manufacturing of the transistors, the oscillations produced will be of different frequencies. Hence, as presented in the traditional arbiterPUF, the variation in the time period of signals reachingthe D flipflop will produce the different output keys.Figure 10 shows the design of one bit of the FinFETbased Hybrid Oscillator Arbiter PUF. It is similar to theMultiplexer Arbiter PUF shown in Fig. 6 presented in Sect.5.1. In the presented design, the environmental changeswill affect the output key generation. A single bit changecan affect the encryption and decryption of data and hencethe entire communication. Hence a current starved designof the ring oscillator is chosen to compensate for temperature variations. The traditional RO PUF and the HybridOscillator Arbiter PUF were subjected to 100 runs ofMonte Carlo variations. All geometric parameters arevaried with a variation (standard deviation) of 5% over theFig. 9 Novel speed optimizedhybrid oscillator arbiter PUF123
436Analog Integr Circ Sig Process (2017) 93:429–441Fig. 10 One bit FinFET based hybrid oscillator arbiter PUFnominal values. The nominal values are presented inTable 3. The parameters that were varied are height andwidth of the transistors, oxide thickness of p- and n-typetransistors, supply voltage, and threshold voltages of boththe transistors. A temperature variation was also performedto simulate the real-time environmental effects that thedevice can experience.7 Experimental results15 nm FinFET models are used for simulations in thispaper. The NCSU PDK is used for all simulations [4]. Themodels were developed as industry standard compact123models. The n-Type FinFET is subjected to Monte Carlovariation to simulate the manufacturing variations byvarying the geometric parameters. Table 3 shows thenominal values taken for the simulations. All the parameters are subjected to a 5% variation.Tables 1, 2 and 4 present the transistor sizes used todesign the RO and the respective results obtained. Twofigures of merit were considered: Time Period and AveragePower. Time Period is the total time taken by the circuit togenerate the key. Average power is taken as the sum ofdynamic power and leakage power of the transistors. Forsimulation purposes, the ring oscillators used are the samefor all three configurations: Traditional, Power Optimizedand Speed Optimized PUF. 32 different ring oscillators are
Analog Integr Circ Sig Process (2017) 93:429–441437Table 3 Nominal values for the FinFET device parametersNominal valuepFET length20 nmpFET width90 nmnFET length20 nmnFET width45 nmpFET fin width10 nmnFET fin width10 nmpFET fin thickness10 nmnFET fin thickness10 nmpFET fin height23 nmnFET fin height23 nmSupply voltage0.9 V 10 85Frequencies (Hz)Parameter4.541008030602040No. of Runs2010Ring OscillatorFig. 11 Ring oscillator frequencies of 100 different PUFsTable 4 Characterization table for speed optimized hybrid oscillatorarbiter PUFParametersTransistor sizesAverage powerValuesp-type (W:L)n-type (W:L)90 nm:20 nm45 nm:20 nm250.15 lWHamming distance49.6%Time to generate key50 ns (varies with frequency of RO)used to generate a 16 bit key in the case of the traditionalRO PUF and a 32 bit key in both cases of Hybrid OscillatorMultiplexer based PUF. 100 Monte Carlo runs are performed on the circuit and the frequencies of different ringoscillators are calculated. Figure 11 represents the frequencies of the ring oscillators in the 100 different runs.Temperature was varied from 24 to 30 C and the meansupply voltage of 0.9 V was considered with a 10% standard deviation, which is representative of on-chip powersupply tolerances.The geometric parameters are taken with a 10% variance. The mean values are the nominal values of thespecific technology. The main parameters that were considered for variation were Width and Height of the fin andthe oxide thickness. Along with these parameters, thetemperature variation and also supply voltage variation wasalso considered in each of the cases. The quality of a PUFcan be estimated using three factors: Uniqueness, Reliability and Attack Resilience.7.1 UniquenessUniqueness of a PUF is the ability of producing a uniquekey different from the other devices. In the proposeddesign, the output bit completely depends upon the frequencies of the ring oscillators. Figure 11 is the surfaceplot representing the frequency variation of each of the 32ring oscillators across 100 Monte Carlo Runs. From thisplot, the uniqueness of different frequencies can be clearlyshown. Hence all the signals reaching each of the D flipflops in the proposed design reach at different time periods.After the bits are generated, the Hamming distancebetween different keys is calculated. The ideal Hammingdistance for a key to be unique is 0.5 (50%). Figure 12shows the distribution of Hamming distances of the PowerOptimized Hybrid Oscillator Multiplexer based PUF whichhas a distribution from 40 to 58% with an average Hamming distance of 48.51%. The Speed Optimized HybridOscillator Multiplexer based PUF has a distribution from40 to 60% with an average Hamming distance of 49.60%.The Hamming distance distribution of Speed OptimizedHybrid Oscillator Multiplexer based PUF is shown inFig. 13.7.2 ReliabilityReliability is the ability of a PUF to generate the same keyagain over a period of time resisting the temperature andsupply voltage variations. In the IoT environment, forsuccessful communication between the devices, the reliability of the PUF key generated is of high importance.Figure 14 shows the distribution of Hamming distance withtemperature and supply voltage variations. The Hammingdistance was varied from 0.8 to 4.3% with a mean of 2.5%.This reliability can still be increased by employing different ring oscillator designs such as temperature resistantRO, and a reconfigurable PUF design.7.3 RandomnessRandomness is another parameter for the validation of aCRP generated using PUFs. In the key generated by a PUF123
438Analog Integr Circ Sig Process (2017) 93:429–44114002000Hamming DistanceGaussian fit1200Hamming DistanceGaussian 550556006501Hamming Distance2345Hamming DistanceFig. 12 Distribution of intra-PUF hamming distance of poweroptimized hybrid oscillator arbiter PUFFig. 14 Distribution of intra-PUF hamming distance of hybridoscillator arbiter PUF160058Hamming DistanceGaussian fit140056Percentage of Bit 44424045505560Hamming Distance40050100150200No. of RunsFig. 13 Distributi
multi-front research on process variations analysis and its mitigations. As a paradigm shift of that trend the present article explores the use of semiconductor manufacturing variations for enhancing security of systems using FinFET technology as an example. FinFETs were introduced to replace high-j transistors in nanoelectronic applications.
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