2021 IEEE 71st Electronic Components And Technology .
2021 IEEE 71st Electronic Components and TechnologyConferenceTechnical Program(ECTC)ECTC 2021Session 1: 2D and 3D Chiplets Interconnects in FO-WLP/PLPCommittee: Packaging TechnologiesSession Co-Chairs:Steffen KroehnertESPAT Consulting, GermanyT 49 351 2758 1287steffen.kroehnert@espat-consulting.comAlbert LanApplied MaterialsT 886-3-5793588Albert Lan@amat.com1. Die Embedding Challenges for EMIB Advanced Packaging TechnologyGang Duan - Intel CorporationYosuke Kanaoka - Intel CorporationRobin McRee - Intel CorporationBai Nie - Intel CorporationRahul Manepalli - Intel Corporation2. Advanced HDFO Packaging Solutions for Chiplets Integration in HPC ApplicationLihong Cao - Advanced Semiconductor Engineering, Inc.Teck Lee - Advanced Semiconductor Engineering, Inc.Yungshun Chang - Advanced Semiconductor Engineering, Inc.SimonYL Huang - Advanced Semiconductor Engineering, Inc.JY On - Advanced Semiconductor Engineering, Inc.Emmal Lin - Advanced Semiconductor Engineering, Inc.Owen Yang - Advanced Semiconductor Engineering, Inc.3. Reliability of 3D-Opto-MID Packages for Asymmetricc Optical Bus CouplersLukas Lorenz - Technische Universität DresdenFlorian Hanesch - Technische Universität DresdenKrzysztof Nieweglowski - Technische Universität DresdenMohd-Khairulamzari Hamjah - FAU Erlangen-NürnbergJörg Franke - FAU Erlangen-NürnbergGerd-Albert Hoffmann - Leibniz Universität HannoverLudger Overmeyer - Leibniz Universität HannoverKarlheinz Bock - Technische Universität Dresden1ECTC 2021 Technical Program
4. Package Design Optimization of the Fan-out Interposer SystemSang Kyu Kim - Samsung Electronics Company, Ltd.Sangwook Park - Samsung Electronics Company, Ltd.Seung Yong Cha Sang Nam Jung - Samsung Electronics Company, Ltd.Gyoungbum Kim - Samsung Electronics Company, Ltd.Dan(Kyung Suk) Oh - Samsung Electronics Company, Ltd.Joonsung Kim - Samsung Electronics Company, Ltd.Sang-Uk Kim - Samsung Electronics Company, Ltd.Seok Won Lee - Samsung Electronics Company, Ltd.5. SoIS- An Ultra Large Size Integrated Substrate Technology Platform for HPC ApplicationsJiun Yi Wu - Taiwan Semiconductor Manufacturing Company, Ltd.Chien-Hsun Chen - Taiwan Semiconductor Manufacturing Company, Ltd.Chien-Hsun Lee - Taiwan Semiconductor Manufacturing Company, Ltd.Chung-Shi Liu - Taiwan Semiconductor Manufacturing Company, Ltd.Douglas C. H. Yu - Taiwan Semiconductor Manufacturing Company, Ltd.6. FOWLP-Based Flexible Hybrid Electronics with 3D-IC Chiplets for Smart Skin DisplayYuki Susumago - Tohoku UniversityTomo Odashima - Tohoku UniversityMasatsugu Ichikawa - Tohoku UniversityHiroki Hanaoka - Tohoku UniversityHisashi Kino - Tohoku UniversityTetsu Tanaka - Tohoku UniversityTakafumi Fukushima - Tohoku University7. Enabling D2W / D2D Hybrid Bonding on Manufacturing Equipment Based on Simulated ProcessParametersCatharina Rudolph - Fraunhofer IZM-ASSIDAnke Hanisch - Fraunhofer IZM-ASSIDMartin Voigtländer - Fraunhofer IZM-ASSIDPeter Gansauer - Fraunhofer IZM-ASSIDH. Wachsmuth - Fraunhofer IZM BerlinSimon Kuttler - Fraunhofer IZM-ASSIDO. Wittler - Fraunhofer IZM-ASSIDThomas Werner - Fraunhofer IZM-ASSIDIuliana Panchenko - Fraunhofer IZM-ASSIDM. Jürgen Wolf - Fraunhofer IZM-ASSIDSession 2: Wafer/Panel Level System Integration and Process AdvancesCommittee: Packaging TechnologiesSession Co-Chairs:Raj PendseFacebook FRL (Facebook Reality Labs)T 1-(510)709-8076rajd@fb.comKuo-Chung YeeTaiwan Semiconductor Manufacturing Corporation, Inc.T 886-3-5636688 Ext. 7222920/7223012kcyee@tsmc.com1. Deca & Cadence Breakthrough Heterogeneous Integration Barriers with Adaptive Patterning (TM)Edward Hudson - Deca TechnologiesDan Baldwin - CadenceTim Olson - Deca TechnologiesCraig Bishop - Deca TechnologiesJan Kellar - Deca TechnologiesRobin Gabriel - Deca Technologies2ECTC 2021 Technical Program
2. nSiP(System in Package) Platform for Various Module Packaging ApplicationsLewis(In Soo) Kang - NEPES CorporationJay Kim - NEPES CorporationJK Lee - NEPES CorporationWS Shin - NEPES CorporationNamChul Kim - NEPES CorporationSY Park - NEPES Corporation3. Chip-Last HDFO (High Density Fan-Out) Interposer PoPJaeYoon Kim - Amkor TechnologyKyeRyung Kim - Amkor TechnologyEunYoung Lee - Amkor TechnologySeHwan Hong - Amkor TechnologyJiHyun Kim - Amkor TechnologyJiYeon Ryu - Amkor TechnologyJiHun Lee - Amkor TechnologyDavid Hiner - Amkor TechnologyWonChul Do - Amkor TechnologyJinYoung Khim - Amkor Technology4. The Influence of Layer Thicknesses on Crackstops’ Mechanical Strength and RobustnessNicholas Polomoff - GLOBALFOUNDRIESMohamed Rabie - GLOBALFOUNDRIES5. Advanced Outlier Die Control Technology in Fan-Out Panel Level Packaging Using FeedforwardLithographyJohn Chang - Onto InnovationJian Lu - Onto InnovationBurhan Ali - Onto Innovation6. A High Performance Package with Fine-Pitch RDL Quality ManagementJen-Kuang Fang - Advanced Semiconductor Engineering, Inc.Cher-Min Fong - National Sun Yat-sen UniversityJhao-Cheng Chen - Advanced Semiconductor Engineering, Inc.Huang-Hsieh Chang - Advanced Semiconductor Engineering, Inc.Peng Yang - Advanced Semiconductor Engineering, Inc.Wen-Long Lu - Advanced Semiconductor Engineering, Inc.Hung-Jung Tu - Advanced Semiconductor Engineering, Inc.Min-Lung Huang - Advanced Semiconductor Engineering, Inc.7. Reliability Considerations for Wafer Scale SystemsNiloofar Shakoorzadeh - University of California, Los AngelesRandall Irwin - University of California, Los AngelesYu-Tao Yang - University of California, Los AngelesHaoxiang Ren - University of California, Los AngelesSubramanian S. Iyer - University of California, Los Angeles3ECTC 2021 Technical Program
Session 3: Advanced Heterogenous Chiplet and Integration for HPCCommittee: Packaging TechnologiesSession Co-Chairs:Ning GeConsultantT 1-650-966-4796greene.ge@gmail.comJaesik Leejaesikl@google.com1. Analysis on Distortion of Fan-Out Panel Level Packages (FOPLP)Yongjin Park - Samsung Electronics Company, Ltd.Bongsoo Kim - Samsung Electronics Company, Ltd.Tae-Ho Ko - Samsung Electronics Company, Ltd.Sung-Hoan Kim Seok-Won Lee Tae-Je Cho2. S-Connect Technology: Multi-chip, Fan-Out Interposer for Next-Generation, HeterogeneousIntegrationJihun Lee - Amkor TechnologyGamhan Yong - Amkor TechnologyMinSu Jeong - Amkor TechnologyJongHyun Jeon - Amkor TechnologyDongHoon Han - Amkor TechnologyWonChul Do - Amkor TechnologyJinYong Khim - Amkor TechnologyMinKeon Lee - Amkor TechnologyMike Kelly - Amkor TechnologyDave Hiner - Amkor TechnologyTEunSook Sohn - Amkor Technology3. Wafer Level System Integration of the Fifth Generation CoWoS-S with High Performance SiInterposer at 2500 mm2Ping Kang Huang - Taiwan Semiconductor Manufacturing Company, Ltd.Chung Yu Lu - Taiwan Semiconductor Manufacturing Company, Ltd.Vincent Wei - Taiwan Semiconductor Manufacturing Company, Ltd.Christine Chiu - Taiwan Semiconductor Manufacturing Company, Ltd.K.C. Ting - Taiwan Semiconductor Manufacturing Company, Ltd.Clark Hu - Taiwan Semiconductor Manufacturing Company, Ltd.Chung Hao Tsai - Taiwan Semiconductor Manufacturing Company, Ltd.Shang Y. Hou - Taiwan Semiconductor Manufacturing Company, Ltd.Wen Chih Chiou - Taiwan Semiconductor Manufacturing Company, Ltd.Chuei Tang Wang - Taiwan Semiconductor Manufacturing Company, Ltd.Douglas C. H. Yu - Taiwan Semiconductor Manufacturing Company, Ltd.4. Advanced System Integration for High Performance Computing with Liquid CoolingJeng-Nan Hung - Taiwan Semiconductor Manufacturing Company, Ltd.Hung-Chi Li - Taiwan Semiconductor Manufacturing Company, Ltd.Po-Fan Lin - Taiwan Semiconductor Manufacturing Company, Ltd.Terry Ku - Taiwan Semiconductor Manufacturing Company, Ltd.C. H. Yu - Taiwan Semiconductor Manufacturing Company, Ltd.KC Yee - Taiwan Semiconductor Manufacturing Company, Ltd.Douglas C. H. Yu - Taiwan Semiconductor Manufacturing Company, Ltd.4ECTC 2021 Technical Program
5. A New Semiconductor Package Design Flow and Platform Applied on High Density Fan-out ChipChen-Chao Wang - Advanced Semiconductor Engineering, Inc.Chih-Yi Huang - Advanced Semiconductor Engineering, Inc.Keng-Tuan Chang - Advanced Semiconductor Engineering, Inc.Youle Lin - Advanced Semiconductor Engineering, Inc.6. Development of a Novel Lead Frame Based Double Side Liquid Cooling High Performance SiC PowerModuleGongyue Tang - Institute of Microelectronics, A*STARLeong Ching Wai - Institute of Microelectronics, A*STARSiak Boon Lim - Institute of Microelectronics, A*STARYong Liang Ye - Institute of Microelectronics, A*STARBoon Long Lau - Institute of Microelectronics, A*STARKazunori Yamamoto - Institute of Microelectronics, A*STARXiaowu Zhang - Institute of Microelectronics, A*STAR7. Scaling M-Series for ChipletsClifford Sandstrom - Deca TechnologiesBenedict San Jose - Deca TechnologiesTim Olson - Deca TechnologiesCraig Bishop - Deca TechnologiesSession 4: Heterogeneous Integration Using 2.xD/3D PackagingTechnologiesCommittee: Packaging TechnologiesSession Co-Chairs:John KnickerbockerIBM CorporationT 1-914-945-3306knickerj@us.ibm.comSubhash L. ShindeNotre Dame UniversityT 1-574-631-1425sshinde@nd.edu1. InFO oS (Integrated Fan-Out on Substrate) Technology for Advanced Chiplet IntegrationYung-Ping Chiang - Taiwan Semiconductor Manufacturing Company, LtdShih-Peng Tai - Taiwan Semiconductor Manufacturing Company, LtdWei-Cheng Wu - Taiwan Semiconductor Manufacturing Company, LtdJohn Yeh - Taiwan Semiconductor Manufacturing Company, LtdChuei-Tang Wang - Taiwan Semiconductor Manufacturing Company, LtdDouglas C. H. Yu - Taiwan Semiconductor Manufacturing Company, Ltd2. Direct Bonded Heterogeneous Integration (DBHi) Si BridgeKamal Sikka - IBM CorporationRavi Bonam - IBM CorporationYang Liu - IBM CorporationPaul Andry - IBM CorporationDishit Parekh - IBM CorporationAakrati Jain - IBM CorporationMarc Bergendahl - IBM CorporationRama Divakaruni - IBM CorporationMaryse Cournoyer - IBM CorporationPascale Gagnon - IBM CorporationCatherine Dufort - IBM Corporation5ECTC 2021 Technical Program
3. Fan-Out (RDL-First) Panel-Level Hybrid Substrate for Heterogeneous IntegrationJohn Lau - Unimicron TechnologyGary Chen - Unimicron TechnologyJones Huang - Unimicron TechnologyRicky Chou - Unimicron TechnologyChanning Cheng-Lin Yang - Unimicron TechnologyHsing-Ning Liu - Unimicron TechnologyTJ Tseng - Unimicron Technology4. 2.2D Die last Integrated Substrate for High Performance ApplicationsDyi Chung Hu - SiPlus Co.Er Hao Chen - SiPlus Co.Jeffrey ChangBing Lee - iST-Integrated Service Technology Inc.Chia Peng Sun - CoreTech System Co.Chih Chung Hsu - CoreTech System Co.5. Novel High-Power Delivery Architecture for Heterogenous Integration SystemsKannan Kalappurakal Thankappan - University of California, Los AngelesSubramanian S. Iyer - University of California, Los Angeles6. TSV-Last Integration to Replace ASIC Wire Bonds in the Assembly of X-ray Detector ArraysJennifer Ovental Hicks - MicrossDean Malta - MicrossDavid Bordelon - MicrossDaniel Richter - MicrossJaesub Hong - Harvard UniversityJonathan Grindlay - Harvard UniversityBranden Allen - Harvard UniversityDaniel Violette - Harvard UniversityHiromasa Miyasaka - California Institute of Technology7. Chiplets in Wafers (CiW) – Process Design Kit and Demonstration of High-Frequency Circuits withGaN Chiplets in Silicon InterposersFlorian Herrault - HRL Laboratories, LLCJoel Wong - HRL Laboratories, LLCIgnacio Ramos - HRL Laboratories, LLCHaw Tai - HRL Laboratories, LLCMatthew King - HRL Laboratories, LLCSession 5: Technologies for Advanced Substrates and Flip-Chip BondingCommittee: Packaging TechnologiesSession Co-Chairs:Kuldip JohalAtotechT 18033700669kuldip.johal@atotech.comLuu NguyenPsi QuantumT 1-408-551-9117lnguyen@psiquantum.com1. Miniaturized 3D Functional Interposer Using Bumpless Chip-on-Wafer (COW) Integration withCapacitorsTatsuya Funaki - Tokyo Institute of TechnologyYoshiaki Satake - Murata Manufacturing Co., Ltd.Kyosuke Kobinata - Tokyo Institute of TechnologyChih-Cheng Hsiao - Industrial Technology Research InstituteHitoshi Matsuno - Murata Manufacturing Co., Ltd.6ECTC 2021 Technical Program
Shunsuke Abe - Murata Manufacturing Co., Ltd.Youngsuk Kim - Tokyo Institute of TechnologyTakayuki Ohba - Tokyo Institute of Technology2. Multi-frequency Miniaturized RF Components Using Hybrid SubstratesSaikat Mondal - Michigan State UniversitySaranraj Karuppuswami Deepak Kumar Premjeet Chahal3. Next Generation of Adhesion Enhancement System for High Speed Substrate ManufacturingThomas Thomas - AtotechPatrick Brooks - AtotechFabian Michalik - AtotechWonjin Cho - Atotech4. Two-Step Fabrication Process for Die-to-Die and Die-to-Wafer Cu-Cu BondsJia Juen Ong - National Chiao Tung UniversityKai-Cheng Shie - National Chiao Tung UniversityKing-Ning Tu - National Chiao Tung UniversityChih Chen - National Chiao Tung University5. Cu Pillar Bump Design Parameters for Flip Chip IntegrationShengmin Wen - SynapticsJason Goodelle - Synaptics IncVanDee Moua - Synaptics IncKenny Huang - Synaptics IncChristine Xiao - Synaptics Inc6. Design, Materials, Process, Fabrication, and Reliability of Mini-LED RGB Display by Fan-Out PanelLevel PackagingJohn Lau - Unimicron TechnologyCT Ko - Unimicron TechnologyCurry Lin - Unimicron TechnologyTJ Tseng - Unimicron TechnologyHenry Yang - Unimicron TechnologyTim Xia - Unimicron TechnologyBruce Lin - Unimicron TechnologyTony Peng - Unimicron TechnologyEagle Lin - Unimicron TechnologyLeo Chang - Unimicron TechnologyNing Liu - Unimicron Technology7. Self-assembly and Mass Reflow of Copper Bumps for Flip-Chip Hybridization in Photonic ApplicationsThierry Mourier - CEA-LETIJ. Auffret - CEA-LETILaura Boutafa - CEA-LETINadia Miloud-Ali - CEA-LETILaurent Mendizabal - CEA-LETIPatrick Peray - CEA-LETIOlivier Castany - CEA-LETI7ECTC 2021 Technical Program
Session 6: Advanced Optoelectronics PackagingCommittee: PhotonicsSession Co-Chairs:Harry G. KellziMicropac IndustriesT 1(972)272-3571harrykellzi@micropac.comAjey JacobUniversity of Southern California (USC)T 1-703-248-6171ajey@isi.edu1. High Density Multi-Chip Module for Photonic Reservoir ComputingJean Benoit Heroux - IBM CorporationToshiyuki Yamane - IBM CorporationHidetoshi Numata - IBM CorporationDaiju Nakano - IBM Corporation2. Integrated Laser Attach Technology on a Monolithic Silicon Photonics PlatformYusheng Bian - GLOBALFOUNDRIESKoushik Ramachandran - GLOBALFOUNDRIESBo Peng - GLOBALFOUNDRIESBrittany Hedrick - GLOBALFOUNDRIESKeith Donegan - GLOBALFOUNDRIESJorge Lubguban - GLOBALFOUNDRIESBenjamin Fasano - GLOBALFOUNDRIESArmand Rundquist - NeophotonicsAsli Sahin - GLOBALFOUNDRIESAjey Jacob - GLOBALFOUNDRIES3. Packaging High-power Photodiodes for Microwave Photonic ApplicationsPeng Yao - Phase Sensitive InnovationsMatthew Konkol - Phase Sensitive InnovationsVictoria Carey - Phase Sensitive InnovationsJesse Buchan - Phase Sensitive InnovationsJeffery Whitson Kevin Shreve - Phase Sensitive InnovationsFuquan Wang - Phase Sensitive InnovationsDennis Prather - Phase Sensitive Innovations4. FOWLP and Si Interposer for High Speed Photonic PackagingTeck Lim - Institute of MicroelectronicsEva Wai Leong Ching - Institute of MicroelectronicsJong Ming Ching - Institute of MicroelectronicsLoh Woon Leng - Institute of MicroelectronicsDavid Soon Wee Ho - Institute of MicroelectronicsSurya Bhattacharya - Institute of Microelectronics5. Low ESL High voltage Si-IPD as enabler for 140W LD output and less 1ns FWHM LiDAR ModuleMohamed Mehdi Jatlaoui - Murata Integrated Passive SolutionsYves Aubry - Murata Integrated Passive SolutionsStephane Longuet - Murata Integrated Passive SolutionsSophie Gaborieau - Murata Integrated Passive SolutionsLaurent Dubos - Murata Integrated Passive SolutionsHiroyuki Nakano - MurataTakahiro Matsuoka - MurataTakahito Kushima - MurataTatsuya Ohara - Murata8ECTC 2021 Technical Program
Shota Ando - Murata6. Heterogeneous Integration of a Compact Universal Photonic Engine for Silicon PhotonicsApplications in HPCHsing-Kuo Hsia - Taiwan Semiconductor Manufacturing Company, Ltd.C.H. Tsai - Taiwan Semiconductor Manufacturing Company, Ltd.K.C. Ting - Taiwan Semiconductor Manufacturing Company, Ltd.F.W. Kuo - Taiwan Semiconductor Manufacturing Company, Ltd.C.C. Lin - Taiwan Semiconductor Manufacturing Company, Ltd.C.T. Wang - Taiwan Semiconductor Manufacturing Company, Ltd.S.Y. Hou - Taiwan Semiconductor Manufacturing Company, Ltd.W.C. Chiou - Taiwan Semiconductor Manufacturing Company, Ltd.Douglas Yu - Taiwan Semiconductor Manufacturing Company, Ltd.7. Integrated Connector for Silicon Photonic Co-Package Optics with Strain Relief AccommodationThrough Fiber BendingAlexander Janta-Polczynski - IBM CorporationMartin Robitaille - LXsimSession 7: 3D TSV and InterposerCommittee: InterconnectionsSession Co-Chairs:Lei ShanTekollectshanlei@yahoo.comPeter RammFraunhofer EMFTT 49-89-54759-539peter.ramm@emft.fraunhofer.de1. Heterogenous Integration of Silicon Ion Trap and Glass Interposer for Scalable Quantum ComputingEnabled by TSV, Micro-bumps, and RDLPeng Zhao - 1IME,Singapore. 2NTU, SingaporeHong Yu Li - Institute of Microelectronics, SingaporeJing Tao - Nanyang Technological University, SingaporeYu Dian Lim - Nanyang Technological University, SingaporeWen Wei Seit - Institute of Microelectronics, SingaporeLuca Guidoni - Laboratoire Matériaux et Phénomènes QuantiquesChuan Seng Tan - Nanyang Technological University, Singapore2. Pre-bond Qualification of Through-Silicon Via for the Application of 3-D Chip StackingLuke Hu - United Microelectronics CorporationChun-Hung Chen - United Microelectronics CorporationM. J. Lin - United Microelectronics CorporationC. F. Lin - United Microelectronics CorporationC. T. Yeh - United Microelectronics CorporationC. H. Kuo - United Microelectronics CorporationTony Lin - United Microelectronics CorporationSteven Hsu - United Microelectronics Corporation3. 3D Die-Stack on Substrate (3D-DSS) Packaging Technology and FEM Analysis for 55um-75um MixedPitch Interconnections on High Density LaminateKatsuyuki Sakuma - IBM CorporationMukta Farooq - IBM CorporationPaul Andry - IBM CorporationCyril Cabral - IBM Corporation9ECTC 2021 Technical Program
Sankeerth Rajalingam - IBM CorporationDale McHerron - IBM CorporationShidong Li - IBM CorporationRussell Kastberg - IBM CorporationTom Wassick - IBM Corporation4. I/O Architecture, Substrate Design, and Bonding Process for a Heterogeneous Dielet-Assemblybased Waferscale ProcessorSaptadeep Pal - University of California, Los AngelesKrutikesh Sahoo - University of California, Los AngelesIrina Alam - University of California, Los AngelesHaris Suhail - University of California, Los AngelesRakesh Kumar - University of Illinois at Urbana ChampaignSudhakar Pamarti - University of California, Los AngelesPuneet Gupta - University of California, Los AngelesSubramanian S. Iyer - University of California, Los Angeles5. Monitoring of the Effect of Thermal Shock on Crack Growth in Copper Through-Glass Via SubstratesChukwudi Okoro - Corning IncorporatedShrisudersan Jayaraman - Corning IncorporatedScott Pollard - Corning Incorporated6. Cost Effective 2.3D Packaging Solution by Using Fanout Panel Level RDLJoonsung Kim - Samsung Electronics Company, Ltd.Jae-Hoon Choi - Samsung Electronics Company, Ltd.San-Uk Kim - Samsung Electronics Company, Ltd.Jooyoung Choi - Samsung Electronics Company, Ltd.Yongjin Park - Samsung Electronics Company, Ltd.Gyoungbum Kim - Samsung Electronics Company, Ltd.Sang Kyu Kim - Samsung Electronics Company, Ltd.Sangwook Park - Samsung Electronics Company, Ltd.Hwasub Oh - Samsung Electronics Company, Ltd.Seok-Won Lee - Samsung Electronics Company, Ltd.Tae-Je Cho - Samsung Electronics Company, Ltd.7. A TSV-Last Approach for 3D-IC Integration and Packaging using WNi Platable Barrier LayerMurugesan Mariappan - Tohoku UniversityK. Mori - T-MicroM. Koyanangi - Tohoku UniversityT. Fukushima - Tohoku UniversitySession 8: Chiplet Integration and Fan-Out InterconnectionsCommittee: InterconnectionsSession Co-Chairs:Katsuyuki SakumaIBM CorporationT 1-914-945-2080ksakuma@us.ibm.comTom GregorichZeiss Semiconductor Manufacturing TechnologyT 1 208-297-0138tmgregorich@gmail.com1. A Novel Wafer-level Packaging Technology : A Key Enabler for New-era High-performanceComputingMin Jung Kim - Samsung Electronics Company, Ltd.Seok Hyun Lee - Samsung Electronics Company, Ltd.10ECTC 2021 Technical Program
Kyoung Lim Suk - Samsung Electronics Company, Ltd.Jae Gwon Jang - Samsung Electronics Company, Ltd.Gwang-Jae Jeon - Samsung Electronics Company, Ltd.Won Kyoung Choi - Samsung Electronics Company, Ltd.2. The Dynamic Behavior of Electromigration in a Novel Cu Tall Pillar/Cu Via Interconnect for Fan-OutPackagingChien-Lung Liang - National Cheng Kung UniversityMin-Yan Tsai - Advanced Semiconductor Engineering, Inc.Yung-Sheng Lin - Advanced Semiconductor Engineering, Inc.I-Ting Lin - Advanced Semiconductor Engineering, Inc.Sheng-Wen Yang - Advanced Semiconductor Engineering, Inc.Min-Lung Huang - Advanced Semiconductor Engineering, Inc.Jen-Kuang Fang - Advanced Semiconductor Engineering, Inc.Kwang-Lung Lin - National Cheng Kung University3. Electrical Design Challenges in High Bandwidth Memory and Advanced Interface Bus Interfaces onHD-FOWLP TechnologyMihai Rotaru - Institute of Microelectronics, A*STARLi Kangrong - Institute of Microelectronics, A*STAR4. Advances in Photosensitive Polymer Based Damascene RDL Processes: Toward SubmicrometerPitches with More Metal LayersEmmanuel Chery - IMECJohn Slabbekoorn - IMECNelson Pinho - IMECAndy Miller - IMECEric Beyne - IMEC5. Ultra-High Strength Cu-Cu Bonding under Low Thermal Budget for Chiplet HeterogeneousApplicationsZhong-Jie Hong - National Chiao Tung UniversityDemin Liu - National Chiao Tung UniversityHan-Wen Hu - National Chiao Tung UniversityMing-Chang Lin - Innolux CorporationTsau-Hua Hsieh - Innolux CorporationKuan-Neng Chen - National Chiao Tung University6. Effectiveness of Inorganic Dielectric Layer on Submicron-scale Cu Traces against Thermal OxidativeStressHiroshi Kudo - Dai Nippon Printing Co., Ltd.Takamasa Takano - Dai Nippon Printing Co., Ltd.Kouji Sakamoto - Dai Nippon Printing Co., Ltd.Daisuke Kitayama - Dai Nippon Printing Co., Ltd.Haruo Iida - Dai Nippon Printing Co., Ltd.Masaya Tanaka - Dai Nippon Printing Co., Ltd.Takahiro Tai - Dai Nippon Printing Co., Ltd.Yumi Okazaki - Dai Nippon Printing Co., Ltd.Jyunya Suzuki - Dai Nippon Printing Co., Ltd.Shingi Maekawa - Dai Nippon Printing Co., Ltd.7. Reliability of Chip-Last Fan-Out Panel-Level Packaging for Heterogeneous IntegrationJohn Lau - Unimicron TechnologyCT Ko - Unimicron TechnologyTony Peng - Unimicron TechnologyHenry Yang - Unimicron TechnologyTim Xia - Unimicron Technology11ECTC 2021 Technical Program
Bruce Lin - Unimicron TechnologyJean-Jou Chen - Unimicron TechnologyPo-Chun Huang - Unimicron TechnologyTJ Tseng - Unimicron TechnologyEagle Lin - Unimicron TechnologyLeo Chang - Unimicron TechnologySession 9: Advances in Cu BondingCommittee: InterconnectionsSession Co-Chairs:C. Key ChungTongFu Microelectronics Co. Ltd.T 86-15365568052key.chung@tfme.com; chungckey@hotmail.comChih-Hang TungTaiwan Semiconductor Manufacturing CompanyT ( 886)-3-5636688chtungc@tsmc.com1. Low Temperature Wafer-to-Wafer Hybrid Bonding by Nanotwinned CopperWei-Lan Chiu - Industrial Technology Research InstituteOu-Hsiang Lee - Industrial Technology Research InstituteChia-Wen Chiang - Industrial Technology Research InstituteHsiang-Hung Chang - Industrial Technology Research Institute2. Room Temperature KlettWelding Interconnect Technology for High Performance CMOS LogicFarough Roustaie - NanoWired GmbHSebastian Quednau - NanoWired GmbHFlorian Weissenborn - NanoWired GmbHOlav Birlem - NanoWired GmbHDavid Riehl - TU DarmstadtXiang Ding - TU DarmstadtAndreas Kramer - TU DarmstadtKlaus Hofmann - TU Darmstadt3. Low Temperature Cu-Cu Bonding with Electroless Deposited Metal Passivation for Fine-Pitch 3DPackagingYuan-Chiu Huang - National Chiao Tung UniversityDemin Liu - National Chiao Tung UniversityKuma Hsiung - National Chiao Tung UniversityTzu-Chieh Chou - National Chiao Tung UniversityHan-Wen Hu - National Chiao Tung UniversityArvind Sundarrajan - National Chiao Tung UniversityHsin Chi Chang - National Chiao Tung UniversityYi-Yu Pan - National Chiao Tung UniversityMing-Wei Weng - National Chiao Tung UniversityKuan-Neng Chen - National Chiao Tung University4. Low Temperature Hybrid Bonding for Die to Wafer Stacking ApplicationsGuilian Gao - Xperi CorporationGill Fountain - Xperi CorporationDominik Suwito - Xperi CorporationJeremy Theil - Xperi CorporationThomas Workman - Xperi CorporationCyprian Uzoh - Xperi CorporationGabe Guevara - Xperi CorporationBongsub Lee - Xperi CorporationLaura Mirkarimi - Xperi Corporation12ECTC 2021 Technical Program
Michael Huyhn - Xperi CorporationPawel Mrozek - Xperi Corporation5. Low-Temperature All-Cu Interconnections Formed by Pressure-Less Sintering of Cu Pillars withNanoporous-Cu CapsRamon Sosa - Georgia Institute of TechnologyKashyap Mohan - Texas Instruments, Inc.Antonia Antoniou - Georgia Institute of TechnologyVanessa Smet - Georgia Institute of TechnologyDenise Thienpont - On Semiconductor CorpYY Tan - On Semiconductor Corp6. Key Elements for Hybridization Technology Development of 2000x2000 Pixels Infrared Focal PlaneArraysJulien Roumegoux - LynredYannick Loquet - LynredBastien Brosse - LynredEric Micoud - LynredH. Leininger - Lynred7. Numerical Investigation on Microfluidic Electroless Deposition for Uniform Copper Pillar MicrobumpsInterconnectionYonglin Zhang - Hong Kong University of Science and TechnologyHaibin Chen - Hong Kong University of Science and TechnologyHaibo Fan - NexperiaJinglei Yang - Hong Kong University of Science and TechnologyJingshen Wu - Southern University of Science and TechnologySession 10: Surface Preparation for Cu BondingCommittee: InterconnectionsSession Co-Chairs:Jian CaiTsinghua UniversityT 86-13501114301jamescai@tsinghua.edu.cnDingyou ZhangBroadcom Inc.Tdingyouzhang.brcm@gmail.com1. Plasma Activated Low-temperature Die-level Direct Bonding with Advanced Wafer DicingTechnologies for 3D Heterogeneous IntegrationKatsuyuki Sakuma - IBM CorporationDishit Parekh - IBM CorporationMichael Belyansky - IBM CorporationJuan-Manuel Gomez - IBM CorporationSpyridon Skordas - IBM CorporationDale McHerron - IBM CorporationIsabel De Sousa - IBM SystemsMarc Phaneuf - IBM SystemsMartin M. Desrochers - IBM SystemsMing Li - ASMPTYiu Ming Cheung - ASMPT2. Multi-stack Wafer Bonding Demonstration utilizing Cu to Cu Hybrid Bonding and TSV EnablingDiverse 3D IntegrationTaeSeong Kim - Samsung Electronics Company, Ltd.13ECTC 2021 Technical Program
Sohye Cho - Samsung Electronics Company, Ltd.SeonKwan Hwang - Samsung Electronics Company, Ltd.Kyuha Lee - Samsung Electronics Company, Ltd.YiKoan Hong - Samsung Electronics Company, Ltd.HakSeung Lee - Samsung Electronics Company, Ltd.Hyokyung Cho - Samsung Electronics Company, Ltd.KwangJin Moon - Samsung Electronics Company, Ltd.HoonJoo Na - Samsung Electronics Company, Ltd.KiHyun Hwang - Samsung Electronics Company, Ltd.3. In-Depth Parametric Study of Ar or N2 Plasma Activated Cu Surfaces for Cu-Cu Direct BondingLiangxing Hu - Nanyang Technological UniversitySimon Chun Kiat Goh - Nanyang Technological UniversityJing Tao - Nanyang Technological UniversityYu Dian Lim - Nanyang Technological UniversityPeng Zhao - Nanyang Technological UniversityMichael Joo Zhong Lim - Nanyang Technological UniversityChuan Seng Tan - Nanyang Technological University4. Dielectric Materials Characterization for Hybrid BondingVivek Chidambaram - Institute of Microelectronics, A*STARPrayudi Lianto - Asia Product Development Center (APDC), Applied MaterialsXiang Yu Wang - Institute of Microelectronics, A*STARGilbert See - Asia Product Development Center (APDC), Applied MaterialsNicholas Wiswell - Applied Materials, Inc.Masaya Kawano - Institute of Microelectronics, A*STAR5. Hybrid Bonding of Nanotwinned Copper/Organic Dielectrics with Low Thermal BudgetKai-Cheng Shie - National Chiao Tung UniversityPin-Syuan He - National Chiao Tung UniversityYu-Hao Kuo - National Chiao Tung UniversityJia Juen Ong - National Chiao Tung UniversityK.N. Tu - National Chiao Tung UniversityBenson Tzu-Hung Lin - MediaTek IncChia-Cheng Chang - MediaTek IncChih Chen - National Chiao Tung University6. Comprehensive Study on Chip to Wafer Hybrid Bonding Process for Fine Pitch High DensityHeterogeneous ApplicationsSharon PeiSiang Lim - Institute of MicroelectronicsSer Choong Chong - Institute of MicroelectronicsVivek Chidambaram Nachiappan - Institute of Microelectronics7. Feasibility Study of Nanotwinned Copper and Adhesive Hybrid Bonding for HeterogeneousIntegrationChih-Cheng Hsiao - Industrial Technology Research InstituteHuan-Chun Fu - Industrial Technology Research InstituteChia-Wen Chiang - Industrial Technology Research InstituteOu-Hsiang Lee - Industrial Technology Research InstituteTsung-Yu Ou Yang - Industrial Technology Research InstituteHsiang-Hung Chang – Industrial Technology Research Institute14ECTC 2021 Technical Program
Session 11: Advanced Chip to Chip/Package Interconnections for 3D andHeterogeneous IntegrationCommittee: InterconnectionsSession Co-Chairs:Zhang ChaoqiQualcomm IncT ( 1)8588456604chaoqi.gt.zhang@gmail.comSeung Yeop KookGLOBALFOUNDRIEST ( 1. Scaling Solder Micro-Bump Interconnect Down to 10 μm Pitch for Advanced 3D IC PackagesZhaozhi George Li - Intel CorporationYoshihiro Tomita - Intel CorporationAdel Elsherbini - Intel CorporationPilin Liu - Intel CorporationHolly Sawyer - Intel CorporationJohanna M. Swan - Intel CorporationShawna Liff - Intel Corporation2. Fluxless Bonding of Large Area ( 900 mm2) Dies - Opportunities and Challenges.Adeel Bajwa - Kulicke & Soffa Industries Inc.Tom Colosimo - Kulicke & Soffa Industries Inc.Tim Grant - Kulicke & Soffa Industries Inc.Bob Chylak - Kulicke & Soffa Industries Inc.3. Laser As
Chien-Hsun Chen - Taiwan Semiconductor Manufacturing Company, Ltd. Chien-Hsun Lee - Taiwan Semiconductor Manufacturing Company, Ltd. Chung-Shi Liu - Taiwan Semiconductor Manufacturing Company, Ltd. . Tae-Ho Ko - Samsung Electronics Company, Ltd. Sung-Hoan Kim Seok-Won Lee Tae-Je Cho 2. S-Connect Technology: Multi-chip, Fan-Out Interposer for .
IEEE 3 Park Avenue New York, NY 10016-5997 USA 28 December 2012 IEEE Power and Energy Society IEEE Std 81 -2012 (Revision of IEEE Std 81-1983) Authorized licensed use limited to: Australian National University. Downloaded on July 27,2018 at 14:57:43 UTC from IEEE Xplore. Restrictions apply.File Size: 2MBPage Count: 86Explore furtherIEEE 81-2012 - IEEE Guide for Measuring Earth Resistivity .standards.ieee.org81-2012 - IEEE Guide for Measuring Earth Resistivity .ieeexplore.ieee.orgAn Overview Of The IEEE Standard 81 Fall-Of-Potential .www.agiusa.com(PDF) IEEE Std 80-2000 IEEE Guide for Safety in AC .www.academia.eduTesting and Evaluation of Grounding . - IEEE Web Hostingwww.ewh.ieee.orgRecommended to you b
Standards IEEE 802.1D-2004 for Spanning Tree Protocol IEEE 802.1p for Class of Service IEEE 802.1Q for VLAN Tagging IEEE 802.1s for Multiple Spanning Tree Protocol IEEE 802.1w for Rapid Spanning Tree Protocol IEEE 802.1X for authentication IEEE 802.3 for 10BaseT IEEE 802.3ab for 1000BaseT(X) IEEE 802.3ad for Port Trunk with LACP IEEE 802.3u for .
the Regiment (HLI). The 71st was initially the 73rd (Highland) Foot, redesignated 71st Highlanders in 1786; in1808 it was given the infantry roll, and in 1810 it became known as the 71st Highland Light Infantr In 1881y.the Regiment amalgamated with the 74th Highlanders to become the 1st & 2nd H.L.I. the reason I mention this, is,
Signal Processing, IEEE Transactions on IEEE Trans. Signal Process. IEEE Trans. Acoust., Speech, Signal Process.*(1975-1990) IEEE Trans. Audio Electroacoust.* (until 1974) Smart Grid, IEEE Transactions on IEEE Trans. Smart Grid Software Engineering, IEEE Transactions on IEEE Trans. Softw. Eng.
effort to get a much better Verilog standard in IEEE Std 1364-2001. Objective of the IEEE Std 1364-2001 effort The starting point for the IEEE 1364 Working Group for this standard was the feedback received from the IEEE Std 1364-1995 users worldwide. It was clear from the feedback that users wanted improvements in all aspects of the language.File Size: 2MBPage Count: 791Explore furtherIEEE Standard for Verilog Hardware Description Languagestaff.ustc.edu.cn/ songch/download/I IEEE Std 1800 -2012 (Revision of IEEE Std 1800-2009 .www.ece.uah.edu/ gaede/cpe526/20 IEEE Standard for SystemVerilog— Unified Hardware Design .www.fis.agh.edu.pl/ skoczen/hdl/iee Recommended to you b
IEEE 802.1Q—Virtual LANs with port-based VLANs IEEE 802.1X—Port-based authentication VLAN Support IEEE 802.1W—Rapid spanning tree compatibility IEEE 802.3—10BASE-T IEEE 802.3u—100BASE-T IEEE 802.3ab—1000BASE-T IEEE 802.3ac—VLAN tagging IEEE 802.3ad—Link aggregation IEEE
IEEE 1547-2003 IEEE P1032 IEEE 1378-1997 Controls IEEE 2030-2011 IEEE 1676-2010 IEEE C37.1 Communications IEC 61850-6 IEC TR 61850-90-1 & IEEE 1815.1-2015 IEC TR 61850-90-2 Cyber & Physical Security IEEE 1686-2013 IEEE 1402-2000
IEEE 610-1990 IEEE Standard Glossary of Software Engineering Terminology, IEEE, 1990 IEEE 829-2008 IEEE Std 829 IEEE Standard for Software and System Test Documentation, IEEE, 2008 IEEE 1012-2016 IEEE Standard for System, Software, and Hardware
