Introduction To LS1 New Dual ARM Cortex -A7 Solution - NXP
Introduction to LS1 New DualARM Cortex -A7 SolutionEUF-NET-T0585Gino Gatto Sr. FAE, Digital NetworkingJUNE.2014TMExternal Use
Agenda QorIQ LS1 Family Overview and Target MarketsPositioning the QorIQ LS1 FamilyDeliverables Schedule and EnablementPerformance DataCall to ActionQorIQ LS1 Family Use CasesCore IP OverviewTrust, Virtualization and SecurityNetworking & High Speed IOLow Speed IO and Pinout OverviewTMExternal Use1
Comprehensive Portfolio of Embedded Processors Basedon ARM TechnologyKinetisMicrocontrollersVybrid ControllerSolutionsi.MX ApplicationProcessorsDesign Potential. RealizedRich Apps in Real Time.Your Interface to the World.QorIQ Processorsbuilt on LayerscapeArchitectureReal-time, highly integratedsolutions with best-in-class2D graphics to enableyour system to control,interface, connect,secure and scale.Industry’s most versatilesolutions for multimedia anddisplay applications, withmulticore scalability andmarket-leading power,performance & integration.Industry’s first softwareaware, core-agnosticnetworking systemarchitecture for the smarter,more capable networks oftomorrow – end to end.Industry’s most scalableultra-low-power, mixedsignal MCU solutionsbased on the ARM Cortex -M and Cortex M0 architectures.Accelerating the Network’s kingFreescale has the industry’s broadest range of solutions built on ARM technology forautomotive, industrial, consumer and networking applications.Find your ideal solution at the price, performance and power level you desire,and leverage the extensive software and tool bundles available to speed and ease your design process.TMExternal Use2
LS1 Processor Family - Target Markets and Applications 1.9B SAM in 2015Enterprise Networking High-speed interfacesSecurity engineECC-protected orking35%WLANEnterprise APNASA&DIndustrial Automation andControl Industrial interfaces LCD for HMI support Industrial protocol supportCarrier LineCardsIndustrialAutomationand Control25%IoT Gateways High-speed interfaces Multi-protocol support High-bandwidth LAN/WAN plianceSurveillanceEnergyGatewayService ProviderRes GatewayMulti-ProtocolGatewayThe LS1 processor familyextends Freescale’s marketleadershipIoT Gateways25%Source: IDC and IMS Research, World Marketfor Internet connected Devices, August, 2012TMExternal Use4David Kramer, 10/16/13
QorIQ LS1 Processor Family – Differentiated FeaturesPerformance starts with the core Dual ARM Cortex-A7 cores delivering over 6,000 CoreMark ofperformance at under 3W (typical) for improved performance withoutincreased power utilizationDefense-in-depth security protection Secure boot, ARM TrustZone and manufacturing protectionCortex-A7Cortex-A7Serial IOL1 Cache w/ECCL1 Cache w/ECCSecurity &TrustL2 Cache w/ECCDDR3L/4ControllerARMv7 32b CoreARMv7 32b CoreEthernetUSB3.0w/PHYLCDCont.PCIeSATA 3QUICCEngineBroadest range of peripheral and I/O features in its class Only product in its class to offer ECC protection for both L1/L2 caches,meeting networking requirements for high reliability Virtualization support enables partitioning of CPU resources on low-powerparts for increased system productivity First in its class to offer support for DDR4 memory ensuring continuedperformance efficiencyLS102x Target ApplicationsMulti-service IoT GatewayIndustrial automation & controlPoint of Sale terminalsATM Machines Only communications processor to combine LCD controller, USB 3.0 withintegrated PHY, SD /MMC and SATA3 on a single SoC to enable lowersystem-level costsSecure Access Point QUICC Engine provides proven support for protocols required inindustrial, building and factory automation applicationsSmart Energy GatewayTMExternal Use5Hot SpotsManagement processorRobotics
LS102x Product Family SnapshotLS1021ACore TypeLS1020AARM Cortex -A7 MPCore NEONCores/ThreadsFrequency2/2Up to 1GHzL1 I/DUp to 600MHz32kB / 32kB with ECCL2 (Unified)512kB Shared with ECCSRAMDDRLS1022A128kB with ECC1x(16/32B ECC) DDR3L/4up to 1.6GT/sDDR3L (8/16B)up to 1.0GT/s4x up to 6.0GHz1x up to 5GHz3 x 1GE2 x 1GE2 x Gen 2.0 (up to 5.0GT/s)1x Gen 2.01 up to 6.0GHzNoUSB1 x USB 3.0 and 1 x USB 2.01 x USB 2.0CANUp to 4Up to 42NoSerDesEthernetPCIeSATA 3.0TDM/HDLCUART/I2C/SPIUp to 10 / 3 / 2I2SLCDUp to 41 x ControllerAccelerationNoSEC,QESECTrusted architectureTMPin Compatible6 0.8mm pitchExternal19x19mm,Use
Positioning QorIQ andi.MX ProcessorsTMExternal Use7
Comparing Price / Performance of Freescale Processorsbased on ARM Performance/FeaturesFor High performance, “Packet Centric” applications: Adds ARM to the QorIQ portfolio starting in 2014Extend high-performance networking for industrial and IoT marketsDeliver comprehensive ecosystem for ARM, focus on Ease of UseStart with 32-bit, intro 64-bit in next generation64-bitEfficient and scalable “pixel-centric” controllers 32-bitDelivering ARM-based products since 2001Focusing on automotive, consumer, and industrialStrong ecosystem with i.MX Community supportLow-power architecture to meet green strategyPriceLowestTMExternal Use8/ /Highest
Customer Application Continuum“Packet”centricQorIQLS SeriesGeneral EmbeddedChoose QoriQ LS1 Support for high bandwidth I/O, coherentPCIe applications & multi-lane SerDes Hardware coherency of CPU & acceleratorswhen requirements call for: High reliability – “always on / alwaysavailable” enabled by ECC protection Application Partitioning and Virtualization Security focused performance – securityengine, secure boot, Trust Architecture Support for industrial protocols: Profibus,RS4xx, others via microcode/QuiccEngine Performance focus in a given powerenvelope and DDR4 supportTMExternal Use9“Pixel”centricChoose i.MXwhen requirements call for: Clear choice for networking applicationsi.MX Clear choice for display-centric applicationsGraphics acceleration processors 3D, 2D, composition enginesH/W video acceleration Decode - 1080p60 H.264 Encode - 1080p30 H.264LPDDR2 enabled battery friendly designsMultiple display interfaces RGB, LVDS, HDMI, MIPICamera sensor interfaces Parallel and MIPIMicrosoft WinCE, Android support needed
LS1 and i.MX6 Security Comparison LS1 and i.MX6 support different feature sets of the same compatibleSecurity Engine (SEC) The LS1 SEC engine is performance optimized i.MX6 SEC is power optimized Comparing security protocol throughput performance of both products LS1 SEC raw performance is 5x to 6x higher than i.MX6The LS1 SEC engine also features hardware protocol offload support (i.e.IPSec, SSL/TLS) which is not supported by the i.MX6 SEC engine LS1 raw AES performance is 5x to 6x higher than i.MX6 raw AES performance LS1 IPSec performance increases the delta difference (8x to 10x higher compared toi.MX6) since the SEC 5.5 supports IPSec protocol off loadTMExternal Use10
Comparing Features of QoriQ LS1 and i.MX 7 FamiliesFeatureCoresStd Temp FreqInd. Temp FreqL1/L2 CacheMemoryInterfaceVirtualizationThreat ProtectionAcceleratorsi.MX 7Soloi.MX 7DualQorIQ LS1022AQorIQ LS1020AQoriQ LS1021A1x A7 – 1xM0 2x A7 – 1xM42x A72x A72x A7800MHz / 166MHz500MHz32K/128K800MHz / 166MHz32K/512K600MHz600MHz32K/512K ECC1GHz1GHz32K/512K ECC1GHz1GHz32K/512K ECCLP-DDR2/3 /3L16-bit 533MHzN/ALP-DDR2/3/3L16-bit 533MHzN/ADDR3L/4 ECC16-bit 1GHzKVM, IODDR3L/4 ECC32-bit 1.6GHzKVM, IODDR3L/4 ECC32-bit 1.6GHzKVM, IOSecure Boot /PCIPTS 4.0compliantN/ASecure Boot /PCIPTS 4.0 compliantSecure Boot/ ARMTrustZonePCIPTS 4.0N/ASecure Boot/ ARMTrustZonePCIPTS 4.0Security – 2GbsSecure Boot/ ARMTrustZonePCIPTS 4.0Security – 2Gbs2x GbEN/AN/A2x GbEN/A1-lane: PCIe21x USB2 w/PHY1xUSB2 HSIC/HostN/A2xUSB2 w/PHY1xUSB2 HSIC/HostN/A2x GbE(line rate)Class/Filter/Fwd1-lane: PCIe2,SATA3, SGMII1x USB2 ULPIEthernet / CANEthernet / CANEthernet / CAN3x GbE(line rate)Class/Filter/Fwd4-lane: PCIe2,SATA3, SGMII1x USB3 w/PHY1x USB2 ULPIHDLC, ProfiBUS,CAN, EthernetEthernet / Audio3x GbE(line rate)Class/Filter/Fwd4-lane: PCIe2,SATA3, SGMII1x USB3 w/PHY1x USB2 ULPIHDLC, ProfiBUS,CAN, EthernetEthernet / CAN20 bit Sensor20 bit sensor MIPI CSI-2N/AN/AN/ARGBN/AN/A2D-ACEFull PMIC EmbeddedRGB, LVDSMIPI-DSI, EPDLDO resMulti-Std SerDesUSBIndustrial ProtocolsIndustrialCamera InterfaceLCD controllerPower ManagementPower (Typ)N/ATMExternal Use11N/A
Deliverables Scheduleand EnablementTMExternal Use12
Rev A Datasheet Reference ManualRev1.0TapeoutRev1.0 AlphaSamplesAlphaBSPSoftwareSiliconQorIQ LS1021A ScheduleRev1.1 EngSamplesRev1.0Gen. AvailSamplesProd.QualUpdtSDKSDKBoardsProto TWRBoardsIoT GtwyBoardsAlpha QDSBoardsAugSepOctNovDecJanQ12013TMExternal Use13Q22014Q3Q4Q12015GASDK
LS1 Family Current DeliverablesLS102xA FamilyVersionAvailabilityLS1021A Reference ManualRev. CAvailable nowSEC Reference ManualRev. AAvailable nowLS1021A Hardware SpecRev. DAvailable nowLS1020A Hardware SpecRev. BAvailable nowLS1022A Hardware SpecRev BAvailable nowLS1021A Ball MapRev. AAvailable nowLS1021A Package Spec.Rev. AAvailable nowLS1021A Product BriefRev. AAvailable nowTWR-LS1021A SchematicsRev. AAvailable now All now available on: LS1021A Extranet siteTMExternal Use14
EcoMAP: QorIQ LS Series ARMDS-5 Atollic CodeWarrior Aricent Cosmic CrankSoftware GreenHills RadiSysSymmetricom VortiQa Oracle JVM IXXAT IAR Acontis VortiQa Koenig-KPA Kozio Beckhoff Skelmir Molex Crank Software Altia TMG MentorEmbedded Timesys Wind ARMRiverDS-5 CodeWarriorTap Arium IAR Mentor Segger WindRiver Aricent AdeneoEmbeededPhoenix MicroVitesse AC6 HILF Embest ADLink Congatec CurtissWright DigiInternational EmersonNetwork Power GE IntelligentPlatform Kontron Mercury Phytec TQ Systems RadisysSYSGO Timesys QNX Wind River - VxWorksEBSmodulesbased onthe LS1 Broadcom Ralink IDC Rohm Linear Sierra Wireless Qualcomm Atheros Silex VitesseTMExternal Use15VitesseArnewshISaGRAFENEA Crank Software RadisysRadisys IEEEArduinoMentor GraphicsCrank Software Green Hills Digi International AdeneoEmbeededAdeneoAdvantech Aricent Lauterbach GreenHills
ARM Development Tools Roadmap for QorIQ FamilyARM DS-5(available from ARM) 4000 yearly ( Probe 3500)Performance Analysis*CostCodeWarrior Networking Developers Suite 1999 yearly ( 500 CW TAP)Continuity with CodeWarriorfor 32B/64B ARMPerformance Analysis, CW Config SuiteIncl. CW tools for other processorsCodeWarriorLS1Tower Edition 200 (stops working after 1/2 year)Bound to LS1Tower boardCMSIS-DAP, On-board JTAG ProbeIncludes Linux GDB AppTimeTMExternal Use16
LS1 Family Customer Enablement BoardsTower-based EvaluationPlatform Rapid prototyping platformfor Industrial applications Multi-protocol supportfor IoT devices Modular design supports arange of connectivity options High speed WAN / LANfor Cloud connectivity Cost-effective, open sourcedevelopment platform Designed to simplify productevaluationCost-effective, opensource developmentplatform Designed to acceleratetime to marketTMExternal UseIoT GatewayReference Design17
QorIQ LS1 Family Software - Board Support Package (BSP)Early engineering release for QDS board available April 2014Functionality Supported: U-Boot ARM A7 Core initialization in u-boot DDR (static setting) RCW, Serdes UART FlexTimer in u-boot (2-signals output) PCIe RC, Ethernet(e1000) NOR boot I2C and EEPROM DDR (SPD) SD VeTSEC IFC NAND & NOR (Flash programming) USB 2.0 NAND boot SD boot ESBC SATA3 DSPI driverTMExternal Use18 Linux ARM A7 Core initialization in kernel DUART in kernel RAMDISK LPUART I2C controller & I2C EEPROMs WDOG eSDHC (SD) DSPI in kernel eDMA & DMAMUX (Same as in Faraday) QE (UART) Power Management (TMU) PCIe (RC mode) eSDHC (SDIO, SDXC) VeTSEC IFC NAND & NOR USB 2.0 (Host, Gadget mode, OTG) GPIO SATA3.0 CAAM FlexCAN
TWR-LS1021A Development SystemFeatures Memory Connectivity Generic Connectivity AvailabilityExternal Use19Up to 3 x RJ45 GigEUp to 1 SATA2 x USB 3.02 x mini PCIe 2.0 (x1 x1) or(x1 x2)Display via HDMI or TWR-LCDor TWR-LCD-RGBAudio OUT via HDMI or Jackplug or TWR EVELConsole port/JTAG via USB2.0Tower Boards supportedvia TWR-EVEL TMDDR3 1GBParallel NOR Flash 128MBorQuadSPI NOR Flash 16MBTWR-IND-IO2 x CAN, RS485, RS232up to 2 boards supportedTWR-LCDTWR-LCD-RGBTWR-ETHERCAT-SLV
TWR-LS1021A – Tower System Development Platform(subject to change)IFC 1EEPROMTMExternal Use20SD/MMC SlotBOTTOMSecondary lCardCLKDDRFullCard1588PHYPrimary ElevatorSATAPHYPHYUSBHUBmPCIeRJ45x2K20Secondary ElevatorRJ45 X2USB3Primary ElevatorJTAGRSTMiniUSB2Dual mPCIeconnectors for.11n/ac Wi-Ficards
TWR-LS1021A – Tower System Development Platform Feature Set 1 Gb Parallel NOR Flash128Mb Qual SPI Flash1 GB DDR3LFull-size SDHC slot—up to 32 GB4Kb EEPROM2x One Gb/s Ethernet (SGMII)1x One Gb/s Ethernet (RGMII)2x mini PCIe (x1) slots1x mSATA slotMuxed LCD/QE interface 24-bit LVDS LCD interface1x HDMI connector2x QE UART to TWR-ELEV forPROFIBUS or RS485 (externaltransceiver needed)Audio Audio OUT via HDMI or Jack plugAudio IN via onboard micTMExternal Use21 USB 3.0 2x ports—USB-A2x ports to mini PCIe slots 2x SPI bus and 3x I2C bus OpenSDA debug support Run-control debugFlash programmerUART to USB converterTower Boards supportedvia TWR-EVEL TWR-IND-IO(2 x CAN, RS485,RS232, up to 2 boards LVTWR-MCLV3PH
QorIQ LS1021A IoT Gateway Reference DesignWifi 802.11QSPImPCIe x1LANE ASATASERDES R3LDiscrete x38Gbit 1GbyteMT41K256M16 – 32 Meg x 16 x 8 banks ECC4GB8 bit SDHC/MMC/SDIOSDHCLANE B2D-ACESAI2Silicon ImageHDMITransmittercellular modem/wifi 802.11mPCIe x1LANE CSGMIIPHYMAGNETICSLS1021ALANE DEC2UART1(2-Wire)LP UART1(4 wire)RS232 xcrSerial toUSBTerminalZigbee/mesh networkSAI2 USB3.0SuperSpeedADCSPIUSB3.0HUBTMExternal Use22UARTArduino ShieldConnectorFor low speedwireless
QorIQ LS1021A IoT Gateway Reference Design – Feature Set 1 Gb QSPI NOR Flash 1 GB DDR3L SDHC slot—up to 32 GB 24-bit LVDS LCD interfaceQE UART to header for PROFIBUS orRS485 (external transceiver required)TMExternal Use2x ports—USB-A2x ports to mini PCIe slots 4 GB populated1x One Gb/s Ethernet (SGMII)1x One Gb/s Ethernet (RGMII)2x mini PCIe (x1) slots1x mSATA slot1x Terminal (USB to UART)1x Four wire LP-UART to Arduinoconnector (ZigBee)Muxed LCD/QE interface USB 3.02313x GPIO or 8x FTM (PWM) 6x Interrupts 1x SPI I2C1 bus Board EEPROMBoot EEPROMArduino ConnectorSensors/PHYs, etc., TBD I2C2 GPIO expansionADCSensors/PHYs, etc., TBD
QorIQ LS1021A IoT Gateway – POC Demo (16-July-14)Freescale MMA8451QaccelerometerLS1021A-IOTGateway PlatformArkessa server storesCO2 readings and usesaccelerometer values tocontrol the robotTelit HE910 3Gmodem(Running Arkessa Client)ArkessaDatabaseGSS COZIR CO2sensorTMExternal Use24
Performance DataTMExternal Use25
LS102xA Performance StrategyKey design objective of LS1 family is to deliver the highestlevel of performance and integration within a sub-4W totaldesign power (TDP) envelope Theoreticalpeak DDR bandwidth: 6.4GByte/s (32-bit * 1.6GHz data rate) Theoretical internal bus bandwidth: 4.8GByte/s (128-bit * 300MHz) IPfwd: 2Gbps at IMIX packet size IPSec: 1Gbps at IMIX packet size(up to 2Gbps at large packet size)NOTE: All performance targets for LS102x are pending actualbenchmarking in silicon, these numbers are preliminary and subjectto changeTMExternal Use26
Comparison (2x Cortex-A7 vs 1x Cortex-A9)7Relative to ARM Cortex-A56QorIQ LS102x processor with ARMCortex-A7 core delivers unmatchedpower/performance efficiency54DDMIPS3DPower22xA72xA71A50A7A9A15 A53A5A7A9A15 A53Dynamic PowerPerformancePerformance is Specint2000 at synthesized frequencyArea is core with Neon L1 cache, with L2 controller, MP1 configuration, no L2 RAM includedPower measured as Dhrystone at nominal voltageTMExternal Use27A5A7A9A15 A53AreaCortex A7 1.9 DMIPS/MHzCortex A9 2.5 DMIPS/MHz
Cortex-A7 Power AdvantageCortex-A7 gives much lower power for the same performance(and much more performance for power-constrained devices)TMExternal Use28
LS102xA System Latency LS102xA benefits from L1 cache prefetching(new to this class of device) Up to 3 outstanding L1 Data cache pre-fetches permitted Significant latency improvement, as shown below.L1 Prefetch of 3L1 Pref. DisabledLatency (core clocks)1201008060DDR40L220L10Data Set Size (KB)TMExternal Use29
QorIQ LS1020A Processor – Higher Performance at 4WCoremarksCoremarkPerformancePwrWattsPwr3.6 TDP5,080@1Ghz x2LS1020A delivers42% more CPUperformance atsub-4W powerCoremarkPerformance2,930@500MHz x2Assumed Features 2x ARM Cortex-A9 256KB L2 16/32*-bit DDR3/3LLS1020A Features 2x ARM Cortex-A7 512KB L2 16/32-bit DDR3L/4(2.8 Typ) Up to 1600 Mtps 3x GbE2x PCIe 2.0USB3.0 w/PHY1x SATA 3.010x UARTS6GHz SERDES 1066 Mtps 2x PCIe 1.02x GbEUSB2.0 w/PHY2x DUARTSAdditional Features 2x I2S Flextimers/PWMDual A9LS1020A2.93 Coremarks/MHz2.54 Coremarks/MHzAt same power, 2x ARM Cortex-A7 based QorIQ LS1020 processor achieves 42% higherperformance compared to 2x ARM Cortex-A9 based SoCTMExternal Use30
QorIQ LS1 Family Use CasesTMExternal Use31
Secure GatewayLess than 3WattsTrusted NodeCryptoTMExternal Use32
Access GatewayLess than 3 WattsTrusted NodeConnectivityTMExternal Use33
Mobile Wireless Gateway [Car] 3WattsTrusted NodeCryptoConnectivityTMExternal Use34
Wireless Hot SpotLess than 3WattsTrusted NodeCryptoTMExternal Use35
Point of Sale StationConnectivityTrusted NodeCryptoTMExternal Use36
Automatic Teller MachineConnectivityTrusted NodeCryptoTMExternal Use37
Programmable Logic ControllerProtocolsTrusted NodeConnectivityTMExternal Use38
Human Machine InterfaceProtocolsTrusted NodeConnectivityTMExternal Use39
Secure Wireless Access pointLess than 3WattsTrusted NodeCryptoTMExternal Use40
Asset Management (M2M) 3WattsTrusted NodeCryptoConnectivityLiteTMExternal Use41
Secure Network Attached StorageLess than 3WattsTrusted NodeCryptoTMExternal Use42
QorIQ LS1 Core IPTMExternal Use43
QorIQ LS1 Family CPU Core Complex and L2 Cache Dual ARM Cortex-A7 cores configured as: Up to 1.0GHz operation Limited to 600MHz on LS102232KB I-cache and 32KB D-cache per core with ECCprotection512KB shared L2 cache with ECC protectionFPU and NEON VFPv4 supportedCoreSight Embedded Trace Macrocell (ETM) supported fordebug traceTMExternal Use44
Interconnect and System IP ARM CCI-400 Coherent Interconnect Crossbarw/ 128-bit data buses, operating at up to 300MHz All IP can be hardware coherent if desired(like previous QorIQ, but unlike most Cortex-A9 SoCs) Including IO coherency for inbound PCIe (unlike most SoCs) ARM GIC-400 Interrupt Controller Analogous to QorIQ MPIC.Further details at www.arm.comTMExternal Use45
QorIQ LS1 Family DDR Memory Controller 32-bit Data 4-bit ECC 16-bitData 2-bit ECC, 8-bit Data 1-bit ECC Only 16-bit Data supported on LS1022 Operation from 1.0GHz to 1.6GHz DDR3L (1.35V) and DDR4 (1.2V) supported Only DDR3L supported on LS10224 chip selects supportedTMExternal Use46
DMA LS102x supports two different DMA Controllers: eDMA (as used on i.MX and Vybrid) Used for relatively low-speed offload of data movement to/from low-speedperipherals (SPI, LPUART, SAI, ASRC, FlexCAN) qDMA (specific to Digital Networking, formerly known as eDMA) Optimized for high bandwidth to / from DDR and / or PCIeTMExternal Use47
Timers QorIQ LS102x processors support three different Timer-related IP FlexTimer (as used on i.MX and Vybrid) 8instances of Flextimer (similar to Kinetis K series MCUs and Vybrid F seriescontroller solutions) Can be used either as software general-purpose timer, or for PWM Industrial motor control or dimmable LED control, etc. WatchdogTimer (as used on i.MX and Vybrid) 2instances of Watchdog timer (similar to i.MX 6 series and Vybrid F seriescontroller solutions) Can be used to either raise interrupt or request SoC reset ARM’sGeneric Timer Compatiblewith Section B.8 of ARMv7-A Architecture Reference Manual Intended for use by softwareTMExternal Use48
Network Standby with LS102xAPrimary Application Running· Performance is maximized· Connectivity is maximizedManagement Request·Decrease CPU freq.· Disable some I/OActiveNo more work· Save system state.· Remove power tonon-essentialcomponents.ManagementManagement Request· Restore power as neededDeep SleepTMNo useful work· Performance is zero· Connectivity is maintainedExternal UsePrimary Application Request· Restore state· Restore power· Increase CPU frequency49
Goals of Network Standby1.Minimize power2.Whatever is connected on the network should not know thatthe product is in Deep Sleep. No3.changes needed to legacy software or the rest of the world.Minimize power .TIP: Optimize for the common caseHome and office networks typically have traffic 24 hours a day (even if “idle”)TMExternal Use50
Power Management: Deep Sleep QorIQ LS102x processors support QorIQ P1022-style DeepSleep Wake on: RGMII Ethernet, or Timer, or GPIO etc. 150mW total SoC power (including IO) Enabling 0.5W AC system design solutionsSupports core Dynamic Frequency Scaling (DFS) Sameas supported on QorIQ P3/P4/P5 productsTMExternal Use51
QorIQ LS1 Family Trust,Virtualization and SecurityTMExternal Use52
QorIQ LS1 Family Security Architecture Overview (p1/3) TrustZone As per Vybrid and i.MX6Hardware compliant to ARM Trusted Base System Architecture (TBSA v1.0)Enablement of this will be from customers or ecosystem, not FreescaleTrusted execution environment for security-critical SW Secure & Normal Worlds (processor modes) Complemented by custom hardware firewalls QorIQ Trust Architecture Secure Boot As per QorIQ P3/P4/P5 ProductsSecurity library embedded in tamper-proof on-chip ROMAuthenticated boot: protect against unauthorized SW Verify SW signature during boot RSA-1024/2048 keys anchored to OTP fingerprint (SHA-256) Encrypted boot to protect software confidentiality Decrypt SW during boot AES-128/256 keys protected by HW master key (AES-256) Run every time SoC is resetImage Version Control (on-chip OTP-based)TMExternal Use53
QorIQ LS1 Family Security Architecture Overview (p2/3) HW Cryptographic Accelerators (SEC 5.5) Secure Storage Programmable TrustZone protected region within On-chip RAM (64Kbytes)Off-chip storage protected by HW master key (AES-256)Secure Real-Time Clock Support for wireline protocols, plus Wi-Fi and Wimax,Not supported: Kasumi, Snow, ZUC, ARC4Symmetric: AES, DES, 3DES, ARC4Hash & HMAC: MD5, SHA-1, SHA-224, SHA-256Hardware random number generator (SP800-90)Export control supportOn-chip, separately-powered real-time clock (1.0V)HW Firewalls Control access from CPU & DMA peripherals to on-chip peripherals on-chip memory off-chip memory Integrated with TrustZoneTMExternal Use54
QorIQ LS1 Family Security Architecture Overview (p3/3) Secure Debug Secure Debug Challenge/Response as per QorIQ P3/P4/P5 productsPhysical Tamper Detection Tamper input signal available for: Cover seal Clock, voltage, temperature detectors Active tamper detectionHardware and software tamper responseTMExternal Use55
Secure Monitor (SecMon) SecMon HP – System Power Domain SystemSecurity Monitor Zeroizable Master Key Programming Mechanism Master Key Control block Non-Secure Real Time Counter with Alarm SecMon LP – Dedicated Power Domain ZeroizableMaster Key Secure Non-Rollover Real Time Counter with Alarm Non-Rollover Monotonic Counter Power Glitch Detector General Purpose Register Tamper Detection MonitorTMExternal Use56SecMonSecMon HPSecure System Monitor-Secure State MachineT-SecureKey Program MechanismTime AlarmReal Time CounterIP Bus Interface & CntrlHP-LP InterfaceSecMon LPSecret Zeroizable KeyPower Glitch DetectorSecure Monotonic CountSecure Gen. Purp. Reg.LP ControlTamper DetectionTime AlarmSecure Real Time Count
Physical Memory Isolation Peripheral Isolation TZASC (TrustZone AddressSpace Controller) Monitors MonitorsAXI bus to DDR controller Programmableaddress regions Secure world access only Shared access ProgrammedCSU (Central Security Unit)peripheral bus Programmable Secure world access only Shared access Programmedby Secure Worldfor each peripheral Lockableby Secure Worldper-peripheral eneral RAMCSUProtected RAMTMExternal lTrustedDMA
Virtualization – CPU modesNon-Secure WorldVirtual MachineApplicationApplicationVirtual ureSupervisorSecure WorldGuest OSGuest rHypervisor (KVM or similar.)HardwareNormal Memory& PeripheralsTMExternal Use58MonitorSecure OSProtected Memory& PeripheralsSecureSupervisor
Virtualization Support by S-MMU System-MMU for 2nd stage translation of Intermediate Physical Address(IPA) to Physical Address (PA) addressesAnalogous concept to PAMU on QorIQ P3/P4/P5 Benefits of using System MMU’s for virtualizations are: Full HW Virtualization support (a.k.a. “IO Virtualization”) Better performance than SW virtualization (“Para-Virtualization”) Simpler (thus faster) porting of the Virtualized (“guest”) OS Support for 4GB address space, for 32-bit bus masters S-MMU features: Up to 64 TLB entries in TLB cache Address translation in HW, for best performance TLB size configurable, to best suite each master needsTMExternal Use59
OS-14GB spaceVA IPAmapping by OSVA to IPA is onlyAvailable for ARMcores.Peripherals operateIn IPA addresses.IPA PAmapping by hypervisorVA IPAmapping by OSVirtualization: 2nd stage address translationOS-24GB spaceVirtual Address (VA)for OS and each applicationon each VMUp to 4GB spaceDue to HW 32-bit limitationTMExternal Use60MMU handles 2ndstage translation:- IPA PA in TLBIntermediate Physical Address (IPA)for each VMPhysical Address (PA)Per OS - 4GB( /- Peripheral space)8GB DDR Peripheral
Networking & High Speed I/OTMExternal Use61
SATA / USB / VeTSEC SATA Enhanced from previous generation QorIQ products One SATA Gen1/2/3 controller (up to 6.0 GBaud) USB 1 USB 3.0/2.0 Host/Device/OTG controller with integrated PHY (Upto 5.0GBaud) AdditionalUSB 2.0 Host/Device/OTG controller with ULPI interface toexternal PHY (Up to 480Mbps)VeTSEC Similar to QorIQ P10xx products. 3 Ethernet MACs, supporting RGMII (3), SGMII (2) and MII (2) interfaces. IEEE1588 hardware support.TMExternal Use62
LS1021A PCI Express 2.0 Controller and SERDES 2 PCI Express Controllers can support x1/x2/x4 operation Fordual PCIe, maximum of 2-lane operation can be supported Only single lane SERDES supported on LS1022 MSI supported (but not MSI-X) USB 3.0 Phy integrates its own dedicated SERDESLS102x SERDES Protocol combinationsSERDES LanesProtocol OptionsAB1CDPCIe#1 x42PCIe#1 x2PCIe#2 x23PCIe#1 x1SATA 1PCIe #2 x24PCIe#1 x1SGMII 1PCIe #2 x1SGMII 25PCIe#1 x1SATA 1SGMII 1SGMII 26PCIe#1 x2SATA 1SGMII 27PCIe#1 x2PCIe #2 x1SGMII 28PCIe#1 x2SGMII 1SGMII 2PCIe #2 x1SGMII 29PCIe x1TMExternal Use63SATA 1
LS102x QUICC Engine Feature Overview Summary Identical to T1040 QE – subset of P1021 QEProtocols and Interfaces HDLC/Transparent(bit rate up to 70Mbps) HDLC BUS (bit rate up to 10Mbps) Asynchronous HDLC (bit rate up to 2Mbps) UART (including ProfiBus support) BISYNC (bit rate up to 2Mbps) Two TDM interface supporting 64 multichannel, each running at 64Kbps Time Slot Assigner and Two TDM Interfaces IndependentRx and Tx routing RAM with 512 routing entries each Time slot assigner with bit or byte resolutionTMExternal Use64
LS1021A 2D-ACE(Two Dimensional Animation and Compositing Engine)FeatureLS1021Resolution1280 x 1024@72HzFor single plane1280 x 768@72HzUp to 2 planes (WXGA)1024 x 768 @72HzUp to 3 planes1024 x 768 @60HzUp to 4 planesa-blend / chroma key4-PlanesBlendingInput PlanesInput Plane BWPixel FormatsCursorPostProcessingSub-Plane selection from 16-layersPixel format per layerTile TexturingDCU blends selected pixels from16-layers of imagesbased on priority. Only displayed layers’ pixelscontribute to input BW.Up to 2.4GByte/s)Limited by internal memory bandwidth assuming fullypopulated blend planes32-bit RGB8 8-bit palleteYCbCrTransparencyLuminanceTransparency a-component used to mixforeground/background colors (gradient).Luminance values add to pixel components below theluminance blend plane (intensity).256xH (8K-pixel) 1-bit pixel, blinkingA blend plane can be used for enhanced cursor supportGamma CorrectionComponent DitheringSafety Pixel TaggingDCU supports dithering to improve color depth andpixel tagging to check tagged input pixels are displayedin blended output24-bit RGB (12-bit DDR pin interface)Display InterfaceCommentsTMExternal Use65
QorIQ LS1 Low-speed I/OInterfaces and PinoutTMExternal Use66
Low-speed Interfaces Audio I2C similar to Vybrid F series controller solutions4 instances of SAI for I2S support ( Synchronous Audio Interface)1 instance of S/PDIF (Sony/Philips Digital Interconnect Format)1 instance of ASRC (Asynchronous Sample Rate Converter )3 instances of I2C (similar to Kinetis K-series and Vybrid F series controller solutions)SPI 2 instances of regular SPI (similar to Vybrid F series controller solutions) Can operate in master or slave modeUART 2 instances of 16550-compatible DUARTs (similar to QorIQ P series processors) Can be configured as two 4-wire, or four 2-wire6 instances of high-spe
Virtualization N/A N/A KVM, IO KVM, IO KVM, IO Threat Protection Secure Boot / PCIPTS 4.0 compliant Secure Boot / PCIPTS 4.0 compliant Secure Boot/ ARM TrustZone PCIPTS 4.0 Secure Boot/ ARM TrustZone PCIPTS 4.0 Secure Boot/ ARM TrustZone PCIPTS 4.0 Accelerators N/A N/A N/A Security - 2Gbs Security - 2Gbs Ethernet Features 2x GbE
Structure and Function (middle) 7.LS1.1: Develop and construct models that identify and explain the structure and function of major cell organelles as they contribute to the life activities of the cell and organisms. 7.LS1.1.a: Ability to identify that cells have internal structures . 7.LS1.1.b: Ability to identify components of a cell . 7.LS1.1.c:
PR-15775 LS7 High Perf. One Piece Thick Wall Pushrod 5/16" x 7.750" x .106" 16 ICE300514 LS1, LS3 BLACK ICE High Perf. Pushrod 1 ICE315740 LS1, LS3 BLACK ICE One Piece Thick Wall Pushrod 1 Elgin Part # Fits Description Qty. Needed R-907 LS1, LS3 Straight Design 8 or 16 R-908 LS1, LS3 Offset Design 8 R-912 LS7 Exh. 8 R-919 LS7 Int. 8
UNIT 3: Transport Across Membranes The questions below address will assist in mastery of the following Learning Targets: HS10-LS1-3.4 ( . equilibrium. HS10-LS1-3.5 Explain how cells maintain homeostasis when placed in various solutions: hypertonic, hypotonic, isotonic. HS10-LS1-3.6 Differentiate between active and passive transport (ex. con
Avionics: Honeywell 6-Tube EFIS. Enrolled on Honeywell HAPP. Dual Honeywell SPZ-8400 Digital Auto Pilot Dual Honeywell FZ-820 Flight Guidance Computers Dual Honeywell NZ-2010 LR NAV/FMS w/ 6.1 Software Dual Collins VHF-422B COMM (8.33 Spacing) Dual Collins VIR-432 NAV w/ FM Immunity Dual Collins ADF-462 Dual Collins DME-442
1.2.7 Dual monitor set-up screen*9) This page is concerning the dual monitor usage. Use the dual monitor function Check here when you wish to use dual monitor function. OS management dual monitor Select whether it is OS management dual monitor or video card management dual monitor. It is
The LS1 is a state of the art, high performance and universal communications hardware. It makes the communication hardware independent of the TCOSS server. The following new features are supported with LS1. Universal Port solution: Fax and Voice can share the same physical ISDN line, where fax and voice have to use different inbound numbers.
1999-02 LS1 PCM pinouts (Camaro, Firebird) Corvette similar PCM connector (BLUE) Pin Wire Color Circuit No. Function . 14 RED/BLK 380 A/C Refrigerant Pressure Sensor Signal 15 RED 225 Generator Turn ON Signal 16 -- -- Not Used 17 DK GRN/WHT 762 A/C Request Signal 18 DK GRN 59 A/C Compressor Clutch Supply Voltage 19 -- -- Not Used .
Fourth Grade NGSS/Benchmark Alignment " Life Science " 4-Life Science1 (4-LS1) From Molecules to Organisms: Structures and Processes Benchmark Unit 3 Life Science: Observing Nature NGSS Standard Benchmark 4-LS1-1 Construct an argument that plants, and animals have internal and external structures that function to support survival, growth .
