CO-PO-PSO Matrix - BPPIMT
B. P. PODDAR INSTITUTE OF MANAGEMENT & TECHNOLOGYDEPARTMENT OF COMPUTER SCIENCE & ENGINEERINGACADEMIC YEAR: 2018-2019 ODD SEMESTERAnalog and Digital Electronics (CS301)COURSE OUTCOMECourse OutcomesCognitive LevelCO2Explain the difference between analog and digital systems, logicgates and number representations, different weighted and nonweighted codesDescribe and illustrate the basic postulates of Boolean algebraand simplification of K maps and solve related problemsCO3Define the outline of formal procedures and compare differentdigital components like multiplexers, flip flops, decoders, adders.CO1CO4CO5CO6UnderstandapplyAnalyzeDiscuss the difference between combinational and sequentialcircuits and Design registers and counters.createRecall transistors, basic OPAMP circuits and explain the conceptof feedback, logic families and A/D, D/A converter.UnderstandEvaluate AND, OR, XOR gates in different sequential andcombinational circuits to get minimum number of gate delays.evaluateCO-PO-PSO PO4PO5PO6PO7PO8PO9PO10PO11222231.8Prepared byAyesha AliPO121233232.33PSO1PSO21222221.8
B. P. PODDAR INSTITUTE OF MANAGEMENT & TECHNOLOGYDEPARTMENT OF COMPUTER SCIENCE & ENGINEERINGACADEMIC YEAR: 2018-2019 ODD SEMESTERAnalog and Digital Electronics (CS301)LESSON T1T1BBT1PPTBBBBPPTR1,W1R1,W1Adder and Subtractor circuits (half &full subtractor) continuedEncoder, Decoder, Comparator,MultiplexerDe-Multiplexer and Parity Generator,Hamming codeBasic Flip-flop & LatchFlip-flops -SR, JKBBT1BBT1PPTT1BBBBT1T117Flip-flops -Master-slave Flip Flops,Mealy and Moore state machinePPTT1,R11819202122Registers (SISO,SIPO)Registers (PIPO,PISO)Ring counter,Johnson counterUniversal shift registerBasic concept of Synchronous andAsynchronous countersBasic concept of Synchronous andAsynchronous counters continuedDesign of Mod N CounterDesign of Mod N Counter continuedBBBBPPT, BBPPT, .6.7.8.9.101112131415232425Topics to be coveredBinary Number System & BooleanAlgebra (recapitulation )BCD, ASCII, EBDIC, Gray codes andtheir conversions .Signed binary number representationwith 1’s and 2’s complementmethodsBinary arithmetic, Venn diagram,Boolean algebra (recapitulation)Representation in SOP and POS formsMinimization of logic expressions byalgebraic method.Minimization of logic expressions byalgebraic method continuedK Map method to simplify expressionsSolving problems on K Map techniqueAdder and Subtractor circuits (half &full adder)T1T1
262728293031323334353637383940A/D and D/A conversion techniques– Basic conceptsD/A :R-2-R only A/DSuccessive approximationLogic families- TTL, ECL - basicconcepts.Logic families- MOS and CMOS basic concepts.Different Classes of Amplifiers (Class-A, B, AB and C)basic concepts, power, efficiency ofdifferent amplifiersRecapitulation of basic concepts ofFeedback and OscillationPhase ShiftWein Bridge oscillatorsAstable & MonostableMultivibratorsSchimtt Trigger circuits555 TimerSolving questions on amplifierDiscussions on last year ation byexample,ProblemSolvingProblemSolvingRequired Text Books:T1.S.Salivahanan, A.Arivaszhagan- Digital Circuit designT2.D.Chattopadhyay,P.C.Rakshit-Electronics Fundamental and applicationRequired Reference Books:R1.Morris M.Mano- Digital Logic and Computer designWeb orialspoint.com/digital circuits/index.htmPrepared byAyesha Ali
B. P. PODDAR INSTITUTE OF MANAGEMENT & TECHNOLOGYDEPARTMENT OF COMPUTER SCIENCE & ENGINEERINGACADEMIC YEAR: 2018-2019 ODD SEMESTERAnalog and Digital Electronics (CS301)GAP IN AND BEYOND SYLLABUSGap in the SyllabusSl. CourseNo Code1 CS 301CourseNameAnalog andDigitalElectronicsFacultyNameAyesha AliTopicPOCOPSOUniversalShift registerPO1, PO2PO3CO1,CO3PSO2Gap beyond the SyllabusSl. CourseNo Code1CS 301CourseFacultyNameNameAnalog and Ayesha on)POPSOPO1, PO2, PO3PSO2Gap beyond syllabus: t.com/digital electronics/error correction in hamming sses/codenotes/Hamming.pdfPrepared byAyesha Ali
B. P. PODDAR INSTITUTE OF MANAGEMENT & TECHNOLOGYDEPARTMENT OF COMPUTER SCIENCE & ENGINEERINGACADEMIC YEAR: 2018-2019 ODD SEMESTERAnalog and Digital Electronics (CS301)Gaps addressed by a resource person/Teaching Methodology - labusResource PersonAyesha AliDocumentGaps included in COs (CS301.1, CS301.3)Lecture 21 included in Lesson Plan to address relevant teachinglearning and assessed through Assignments towards fulfilment ofGaps within the syllabusNot Applicable(Addressed viaweb resources)Document addressing gaps is included in Lesson Plan w.r.tTextbooks/References:1.S.Salivahanan, A.Arivaszhagan- Digital Circuit design2.Morris M.Mano- Digital Logic and Computer designAvailable l electronics/error correction in hamming code.aspData Communication and Networking by Behrouz A. ForouzanError Detection and Correction in the International Standard BookNumber by Peter Waweru KamakuPrepared byAyesha Ali
B. P. PODDAR INSTITUTE OF MANAGEMENT & TECHNOLOGYDEPARTMENT OF COMPUTER SCIENCE & ENGINEERINGACADEMIC YEAR: 2018-2019 ODD SEMESTERBRIGHT Students SUMMARYCourse Name: ANALOG AND DIGITAL ELECTRONICS (CS 301)Course code: CS301Academic year: 2018-2019Program: CSE Section: B Year: 2ndName of the faculty: Ayesha AliLIST OF BRIGHT STUDENTS [1ST LIST].Serial Number12345678910Roll 50011707611500117080Trisha MajiSupriti AthaSoumyadeep PaulShreyasi GhoshSatyaki SenSanah AsgarSamyadeep BhowmickSamidha SinghiRahul LohiaPreeti Jha% of students : 17%Parameter-1: SGPA above 8.0Parameter-2: Class performanceParameter 3: Class test markBright student engagement plan :1.Sharing the question bank and study material for GATE and other competitive exams.
B. P. PODDAR INSTITUTE OF MANAGEMENT & TECHNOLOGYDEPARTMENT OF COMPUTER SCIENCE & ENGINEERINGACADEMIC YEAR: 2018-2019 ODD SEMESTERBRIGHT Students SUMMARYCourse Name: ANALOG AND DIGITAL ELECTRONICS (CS 301)Course code: CS301Academic year: 2018-2019Program: CSE Section: B Year: 2ndName of the faculty: Ayesha AliLIST OF BRIGHT STUDENTS [2ND LIST].**Parameter selection: Considering performance in class and attendance, students have been put in this list.Serial Number1234567891011Roll 5001170731150011705711500117032Tathagata JanaSamyadeep BhowmickSamidha SinghiSubhadeep BandyopadhyaySoumyadeep PaulPunit KhandelwalUpasana BitShreyasi GhoshRajsekhar Roy ChowdhurySaronee DasSupriti Atha% of students : 19%Bright student engagement plan :1. Giving some advanced level problems to solve.2.Sharing the question bank and study material for GATE and other competitive example
B. P. PODDAR INSTITUTE OF MANAGEMENT & TECHNOLOGYDEPARTMENT OF COMPUTER SCIENCE & ENGINEERINGACADEMIC YEAR: 2018-2019 ODD SEMESTERBRIGHT Students SUMMARYCourse Name: ANALOG AND DIGITAL ELECTRONICS (CS 301)Course code: CS301Academic year: 2018-2019Program: CSE Section: B Year: 2ndName of the faculty: Ayesha AliLIST OF BRIGHT STUDENTS [3RD LIST].**Parameter selection: 1st internal Test ResultSerial Number123456789101112Roll a JanaSreeja PaulSamyadeep BhowmickSoumyadeep PaulSanah AsgarSamidha SinghiSudip Kumar JhaSaronee DasUpasana BitSupriti AthaSayantan SinghaShreyasi Ghosh% of students : 20%Prepared byAyesha Ali
B. P. PODDAR INSTITUTE OF MANAGEMENT & TECHNOLOGYDEPARTMENT OF COMPUTER SCIENCE & ENGINEERINGACADEMIC YEAR: 2018-2019 ODD SEMESTERAnalog and Digital Electronics (CS301)ASSIGNMENT CS301OUTCOME BASED EDUCATION (OBE)Question No.Knowledge DomainCOs1,3,CreateCO 32,7ApplyCO 24AnalyzeCO 1, CO 35,6,8CreateCO 2,CO 49,10AnalyzeCO 2,CO 31. Design a SR flip flop using a NAND gate, and construct the corresponding characteristicand excitation table.2. Minimize the function:f (A,B,C,D) m(4,8,10,11,12,15) ℇ(9,14)3. Design a JK flip flop using a NOR gate, and find the expression of J and K respectively.4. Design an OR and a XOR gate from 2:1 MUX5. Design a circuit to generate odd parity if the data is represented with 4 bits and constructthe corresponding K-Map to obtain the simplified expression.6. Design a 1-bit full adder with two half adders and minimum number of additional gates7. Use Boolean Algebra to show that A’BC’ AB’C’ AB’C ABC’ ABC A BC’8. Implement a Full Subtractor using a 3 to 8 Decoder9. Implement the following function with 8x1 multiplexer. F(A,B,C,D) Σ(0,1,3,4,8,9,15)with A,B,C connected to S0, S1, S2 respectively.10. Find the Boolean function that a 8x1 multiplexer implement with A,B,C connected toselect lines S2,S1,S0 respectively, if I0 0, I1 D, I2 0, I3 D‟, I4 I5 D, I6 0, I7 1Prepared byAyesha Ali
B. P. PODDAR INSTITUTE OF MANAGEMENT & TECHNOLOGYDEPARTMENT OF COMPUTER SCIENCE & ENGINEERINGACADEMIC YEAR: 2018-2019 ODD SEMESTERAnalog and Digital Electronics (CS301)ASSIGNMENT CS301OUTCOME BASED EDUCATION (OBE)Question No.Knowledge DomainCOs1,4,8UnderstandCO 52UnderstandCO 13,6,7,9AnalyzeCO 2, CO 35CreateCO 410EvaluateCO 61. What do you mean by power amplifier? Explain the working of Class B push pullamplifier ?2. Explain grey code. Why is grey code called reflected code?3. Implement the following Boolean function using a single 4 to 1 Multiplexer.F (A,B,C,D) Σ m ( 0, 1, 2, 4, 6, 9, 12, 14 )4. Explain A/D converter. What is the advantage of R-2R type D/A converter over any othertype of D/A converter.5. Explain the working of a ring counter with timing diagram.6. Design and implement a comparator circuit that compares 3 two bit binary numbers.7. Derive SR flip flop from JK flip flop. Construct the master-slave flip flop. Why is it socalled ?8. Explain and draw the Schmitt trigger circuit.9. Write a short note on Priority encoder and parity generator.10. Design a 1-bit full adder with two half adders and minimum number of additional gatesPrepared byAyesha Ali
B. P. PODDAR INSTITUTE OF MANAGEMENT & TECHNOLOGYDEPARTMENT OF COMPUTER SCIENCE & ENGINEERINGACADEMIC YEAR: 2018-2019 ODD SEMESTERAnalog and Digital Electronics (CS301)QUIZOUTCOME BASED EDUCATION (OBE)Question No.Knowledge DomainCOs1.CreateCO 4, CO 12AnalyzeCO 3, CO 23CreateCO 44EvaluateCO 6The terminal count of a modulus-11 binary counter is .A.1010B.1000C.1001D.11002.3.Convert SR Flip flop to T flip flop. Show proper steps and the final circuit diagram.Construct the block diagram and timing diagram of a 3-bit up Ripple counter.4.How many flip-flops are required to make a MOD-32 binary counter?A.3B.45C.5D.65.1,5Construct a MOD-12 counter from MOD-16 counter.13213
26 A/D and D/A conversion techniques - Basic concepts BB T1,R1 27 D/A :R-2-R only A/D BB W1,T1 28 Successive approximation BB W1,T1 29 Logic families- TTL, ECL - basic concepts. PPT T1,W2 30 Logic families- MOS and CMOS - basic concepts. PPT T1,W2 31 Different Classes of Amplifiers - (Class-A, B, AB and C) PPT T2 32 basic concepts, power, efficiency of
CONTENTS CONTENTS Notation and Nomenclature A Matrix A ij Matrix indexed for some purpose A i Matrix indexed for some purpose Aij Matrix indexed for some purpose An Matrix indexed for some purpose or The n.th power of a square matrix A 1 The inverse matrix of the matrix A A The pseudo inverse matrix of the matrix A (see Sec. 3.6) A1 2 The square root of a matrix (if unique), not elementwise
A Matrix A ij Matrix indexed for some purpose A i Matrix indexed for some purpose Aij Matrix indexed for some purpose An Matrix indexed for some purpose or The n.th power of a square matrix A 1 The inverse matrix of the matrix A A The pseudo inverse matrix of the matrix A (see Sec. 3.6) A1/2 The square root of a matrix (if unique), not .
CONTENTS CONTENTS Notation and Nomenclature A Matrix Aij Matrix indexed for some purpose Ai Matrix indexed for some purpose Aij Matrix indexed for some purpose An Matrix indexed for some purpose or The n.th power of a square matrix A 1 The inverse matrix of the matrix A A The pseudo inverse matrix of the matrix A (see Sec. 3.6) A1/2 The square root of a matrix (if unique), not elementwise
CONTENTS CONTENTS Notation and Nomenclature A Matrix A ij Matrix indexed for some purpose A i Matrix indexed for some purpose Aij Matrix indexed for some purpose An Matrix indexed for some purpose or The n.th power of a square matrix A 1 The inverse matrix of the matrix A A The pseudo inverse matrix of the matrix A (see Sec. 3.6) A1 2 The sq
SYLLABUS OF M A MUSIC . 2 Programme Specific Outcomes (PSO) for (MA MUSIC) PSO 1 Familiarise the students to the vast repertoire of compositions in Carnatic Music. PSO 2 Cultivate an awareness of the cultural and artistic heritage of India PSO 3 Creatively put in practice dedicated music
Further Maths Matrix Summary 1 Further Maths Matrix Summary A matrix is a rectangular array of numbers arranged in rows and columns. The numbers in a matrix are called the elements of the matrix. The order of a matrix is the number of rows and columns in the matrix. Example 1 [is a ] 3 by 2 or matrix as it has 3 rows and 2 columns. Matrices are .
neural network based compare with PSO neural network such as Prasain (2010)[18] applied PSO for option pricing, found that the execution time of sequential PSO algorithm is slightly higher than binomial lattice algorithm. Rosli et al., (2016)[12] developed and intelligent
N. Suttle 2010. Mineral Nutrition of Livestock, 4th Edition (N. Suttle) 1 1 The Requirement for Minerals Early Discoveries All animal and plant tissues contain widely vary-ing amounts and proportions of mineral ele-ments, which largely remain as oxides, carbonates, phosphates and sulfates in the ash after ignition of organic matter. In the .
