Si MOSFET Roadmap For 22nm And Beyond - 東京工業大学
Si MOSFET Roadmap for 22nmand beyondDecember 1６, 2009Jadavpur University @Kolkata, IndiaHiroshi IwaiTokyo Institute of Technology1
Outline1. Scaling2. ITRS Roadmap3. Voltage Scaling/ Low Power and Leakage4. SRAM Cell Scaling5.Roadmap for further future2
1. Scaling3
Scaling Method: by R. Dennard in 1974111SDWdepLeakage currentK 0.7forexampleKWdep: Space Charge Region(or Depletion Region) WidthWdep has to be suppressedOtherwise, large leakageIbetween S and DPotential in space charge region is0high, and thus, electrons in source areattracted to the space charge region.X , Y , Z : K,K1V : K,0V1Na : 1/KBy the scaling, Wdep is suppressed in proportion,and thus, leakage can be suppressed.WdepGood scaled I-V characteristicsK WdepV/Na: KKI0I: K0VK4
Downscaling merit: Beautiful!Geometry &Supply voltageDrive currentin saturationId per unit WgLg, WgTox, VddKScaling K : K 0.7 for exampleCo: gate C per unit areaId vsatWgCo (Vg‐Vth)IdKId/µm1Id per unit Wg Id / Wg 1Cg εoεoxLgWg/toxGate capacitanceCgKSwitching speedτKClock frequencyf1/KChip areaAchipαIntegration (# of Tr)Nα/K2Power per chipPαWg (tox –1)(Vg‐Vth) Wgtox ‐1(Vg‐Vth) KK‐1K Kτ CgVdd/IdKK/K KKK/K Kf 1/τ 1/Kα: Scaling factorNfNCV2/2α/K2In the past, α 1 for most cases 1/K2 , when α 1K‐1(αK‐2)K (K1 )2 α 1, when α 15
2 Generationsk 0.72 0.5 and α 1Single MOFETVdd0.5Lg0.5Id0.5Cg0.5P (Power)/Clock0.53 0.1250.5τ (Switching time)ChipN (# of Tr)f (Clock)P (Power)1/0.52 41/0.5 216
- The concerns for limits of down-scaling havebeen announced for every generation.- However, down-scaling of CMOS is still the‘royal road’* for high performance and low power.- Effort for the down-scaling has to be continuedby all means.*Euclid of Alexandria (325BC?-265BC?)‘There is no royal road to Geometry’Mencius (Meng-zi), China (372BC?-289BC?)(Rule of right vs. Rule of military)7
Actual past downscaling trend until year 200010 210 110 010 -1Past 30 years scaling10 3Minimum logic Vdd (V)M PULg (µm)X(j µm)Id/µm(mA/µm)tox (µm)10 110 -110 -210 -31970198019902m ） Hz)m（size cy 0 -31970200019801990Source. Iwai and S. Ohmi, Microelectronics Reliability 42 (2002), pp.1251-1268Change in 30 yearsIdealscalingRealChangeLgtoxKK(10 –2)10‐2‐210VddK(10 –2)10‐1101AchipαMerit:Demerit: P increaseVdd scaling insufficientAdditional significant2000increase inId, f, PRealChangeIdealscalingN, f increaseIdealscalingK (10 –2)10‐1fId/µm1101Nα/K2(10 5)104Pα(10 1) fαNCV2IdVd scaling insufficient, α increased1/K(10 2)RealChange103105N, Id, f, P increased significantly8
- Now, power and/or heat generation are thelimiting factors of the down-scaling- Supply voltage reduction is becoming difficult,because Vth cannot be decreased any more,as described later.- Growth rate in clock frequency and chip areabecomes smaller.9
2. ITRS Roadmap(for 22 nm CMOS logic)10
What is a roadmap? What is ITRS?Roadmap: Prediction of future technologiesITRS: International Technology Roadmap for Semiconductorsmade by SIA (Semiconductor Industry Association withCollaboration with Japan, Europe, Korea and m20031997199910EOT [nm]Physical Gate Length 99219941.5nm 19991 200119972003200520050.1119952005201519952005201511
1992 -1997:NTRS (National Technology Roadmap)1998 : ITRS (International Technology Roadmap)2008 ITRSupdate2007 ITRS2006 ITRSupdate
ITRS Roadmap does change every year!2007 Edition2006 Update2005 Edition2004 Update2003 Edition2002 Update2001 Edition2000 Updatehttp://www.itrs.net/reports.html13
Operation Frequency (a.u.)HP, LOP, LSTP for Logic CMOS100e)101Subthreshold Leakage (A/µm)Source: 2007 ITRS Winter Public Conf.14
What does ‘45 nm’ mean in 45 nm CMOS Logic?‘XX nm CMOS TechnologyCommercial Logic CMOS productsTechnologyname45 nmStartingYear200732 nm2009?ITRS 2008 Updatefor High Performance LogicYear2007200820092010Half Pitch Physical(1st Metal) Gate Length68 nm32 nm59 nm29 nm52 nm27 nm45 nm24 nm‘XX nm’ CMOS Logic Technology:- In general, there is no common corresponding parameterwith ‘XX nm’ in ITRS table, which stands for ‘XX nm’ CMOS.15
What does ‘45 nm’ mean in 45 nm CMOS Logic?8µm Æ 6µm Æ 4µm Æ 3µm Æ 2µm Æ 1.2µm Æ 0.8µm Æ 0.5µm- Originally, ‘XX’ means lithography resolution.- Thus, ‘XX’ was the gate length, and half pitch of lines- ‘XX’ had shrunk 0.7 in 3 years in average (0.5 in 6 years) those days.Logic 1st MetalHalf Pitch16
What does ‘45 nm’ mean in 45 nm CMOS Logic?Æ 350nm Æ 250nm Æ 180nm Æ 130nm Æ 90nm Æ 65nm Æ 45nm-‘XX’ values were established by NTRS* and ITRS with the termof ‘Technology Node**’ and ‘Cycle***’ using typical ‘half pitch value’.- The gate length of logic CMOS became smaller with one ortwo generations from the half pitch, and ‘XX’ names aheadof generations have been used for logic CMOS.ResistAshingResist- Memory still keeps the half pitch as the value of ‘XX’17
For example, Typical Half Pitches at ITRS 20072010HP 45nmToo aggressiveshrinkLg 18nmResistAshingResistSource: 2008 ITRS Summer Public Conf.18
Physical gate length in past ITRS was too aggressive.The dissociation from commercial product prediction will be adjusted.Physical gate length of High-Performance logic will shift by 3-5 yrs.Correspond to45nm 32nm 22nm Logic CMOS32nm25nm27nm20nm22nm16nm3 year shiftX0.71/3YITRS2007 earPrintLg2008 U2008UpdpdatePX0.71 / 3 Yearrint Lgate Phys.LgITRS 2007 Phys. Lg5 year shift2008UpdateX0.71 / 3.8 YearX0.71 / 3 YearITRS2007Source: 2008 ITRS Summer Public Conf.19
EOT and Xj shift backward, corresponding to Lg shiftEOT: 0.55 nm Æ 0.88 nm, Xj: 8 nm Æ 11 nm @ 22nm CMOSLikely in 2008 Update Correspond to 22nmSource: 2008/ ITRS Summer Public Conf.Likely in 2008 UpdateLikely in 2008 Update8Likely in 2008 Updatenon-steady trendcorrectedfilled in for metal gate EOT for 2009/10based on latest conference presentations20
What does ‘22 nm’ mean in 22 nm CMOS Logic?‘XX nm CMOS TechnologyCommercial Logic CMOS productsTechnologyname45 nmStartingYear200732 nm2009?22 nm2011? 2012?2013? 2014?16 nmITRS (Likely in 2008 Update)for High Performance LogicYear20072008200920102011201220132014Half Pitch Physical(1st Metal) Gate Length68 nm32 nm59 nm29 nm52 nm27 nm45 nm24 nm40 nm22 nm36 nm20 nm18 nm32 nm16 nm29 nmSource: 2008 ITRS Summer Public Conf.From ITRS2008 Update, maybe XX nm stands for the physicalGate length21
Clock frequency does not increase aggressively anymore.Even decreased!Advantage in SISCEra for ‘out of order’Advantage in RISCSimple configurationSource: Mitsuo Saito, ToshibaMulti CoreClock Performance22
ITRS2007d?eunintokCcol cyCre uenoC eqFrChip cyenuqerFCell Broadband Engine6GHz capabilityfor SRAMSource:IBM, Toshiba, SonyISSCC2008 and 08Source: 2007 ITRS Winter Public Conf.23
Max on chip frequency or ‘Core 2ITRS22 nm:6 GHz?Source: 2008 ITRS Summer Public Conf.24
Structure and technology innovation (ITRS 2007)Source: 2008 ITRS Summer Public Conf.25
Timing of CMOS innovations shifts backward.Bulk CMOS has longer life now!Correspond to 22nm Logic CMOSBulk extends 4 years!Multi G delays 4 years!Source: 2008 ITRS Summer Public Conf.26
Wafer size (ITRS 2007)Correspond to 22nmSource: ITRS 2007?Maybe delay?27
ITRS2008 Low-k Roadmap UpdateCorrespond to 22nm LogicITRS2007Update2008ITRS2007Update2007Source: 2008 ITRS Summer Public Conf.k value increases by 0.1 0.328
Historical Transition of ITRS Low-k ource: 2008 ITRS Summer Public Conf.29
Roadmap towards 22nm technology and beyond- Physical gate length downsizing rate will be lessaggressive.- Corresponding to the above, performance increasewould slow down – Clock frequency, etc.- Introduction of innovative structures – UTB SOI andDG delayed, and bulk CMOS has longer life thanpredicted by previous ITRS roadmaps.30
3. Voltage Scaling/ Low Power and Leakage31
Difficulty in Down-scaling of Supply Voltage: VddBecause, Vth cannotbe down-scaled anymore,Vdd down-scaling is difficult.VVoltddVdd – Vth determines theperformance (High Id)and cannot be too small.Vth Vth: Vth variationSubthreshold leakage current limitYear VthMargin for Vth variationis necessary32
Subtheshold leakage current of MOSFETIdSubthreshold CurrentIs OK at Single Tr. levelIonOFFSubthreshouldLeakage CurrentIoffONBut not OKFor Billions of Trs.VgVg 0VSubthresholdregionVth(Threshold Voltage)33
Ionsignificant Ioff increaseIoffVth: 300mV Æ 100mVIoff increaseswith 3.3 decades(300 – 100)mV/(60mv/dec) 3.3 decIoffLog Id per unit gate width ( 1µm)Vth cannot be decreased anymoreSubthreshold slope (SS) (Ln10)(kT/q)(Cox CD Cit)/Cox 60 mV/decade at RTLog scale Id plot10-3A10-4A10-5AVdddown-scaling10-6A10-7AVdd 0.5V10-8AVdd 1.5VVthdown-scaling10-9A10-10AVth 300mVVg (V)Vth 100mVVg 0VSS value:Constant and does not become small with down-scaling34
ITRS for HP logicIon/Ioff ratio2008up (bulk)2008up (UTB)2008up (DG)2007 (bulk)2007 (UTB)2007 (DG)2005 (bulk)2005 (UTB)2005 (DG)2003200119991.0E 919991.0E 71.0E 6011.0E 520Ion/Ioff ratio1.0E 82005 DG1.0E 4Others2003-20081.0E 32004200720102013201620192022Year35
ITRS for HP logicVth will bearound 0.1VVdd will stay higherin 2008 updateVdd1.20.4190.803,200990.60.35,20072008up (bulk)2008up (UTB)2008up (DG)2007 (bulk)2007 (UTB)2007 (DG)2005 (bulk)2005 (UTB)2005 (DG)20032001199920010.40.2020070.25201020132008 Values are fromITRS Public Conf.and still under discussionYear201620192022Vth (V)20Vdd (V)0.35200812004Vth0.220032005 DG2005 UTB0.150.10.052008up (bulk)2008up (UTB)2008up (DG)2007 (bulk)2007 (UTB)2007 (DG)2005 (bulk)2005 (UTB)2005 (DG)2003 (bulk)2005Blk2007, 20080200420072010Source: ITRS and2008 ITRS Summer Public Conf.2013Year20162019202236
Improper down-scalingMetal gateHigh-k oxdCould we squeeze technologiesfor ultimate CMOS scaling?SiSaturation of EOT thinning is a seriousroadblock to proper down-scaling.2008up (bulk)2008up (UTB)2008up (DG)2007 (bulk)2007 (UTB)2007 (DG)2005 (bulk)2005 (UTB)2005 (DG)2003 (bulk)20011999for HP LogicEOT (nm)1.210.8Interfacial C(Quantum eff)Inversion C(Quantum eff)Interfacial C@Metal gate andGate oxd.(EOT 0.2 0.3nm?)C1Gate Oxd CC2C3Inversion C(EOT 0.3 0.5nm?)0.60.42004200720102013201620192022EOT(C1) EOT(C3) 0.5nmSmall effect to decreaseEOT(C2) beyond 0.5nm?DelayIs 0.5nm real limit? SaturationYear37
EOT 0.5nm with Gain in Drive Current is PossibleDrain current (mA)La2O3 gate insulator(a) EOT 0.37nm**3.53 W/L 2.5/50µmoVth -0.04V(b) EOT 0.43nm**Vth -0.03VPMA 300 C (30min)(c) EOT 0.48nm4%upVth -0.02V14%up21000*1insufficientcompensation region0.20.6 0.80.80.2 0.40.4 0.6Drain voltage (V)1000.2 0.4 0.6 0.8 10.20.4voltage0.6 0.8Drain(V) 1000.2 0.4 0.6 0.8 10.20.4voltage0.6 0.8Drain(V) 1EOT scaling below 0.5nmStill useful for larger drain currentSource: K. Kakushima, K. Okamoto, K. Tachi, P. Ahmet, K. Tsutsui, N.i Sugii,T. Hattori, and H. Iwai, IWDTF 2008, Tokyo, November, 2008***Because Lg is very large (2.5µm), gate leakage is large in case (a). The gate leakagecomponent was subtracted from measured data for case (a). However, if we make smallgate length, the gate leakage current should become sufficiently small to be ignoredcompared with Id as we verified with SiO2 gate before (Momose et al.,IEDM 1994). Thegate leakage could be suppressed by modifying material and process in future.Estimated by Id value38
Thus, in future, maybe continuous development ofnew techniques could make more proper downscaling possible.It is difficult to say, but EOT and Vdd may becomesmaller than expected today.39
Normalized σVthRandom Variability Reduction Scenarioin ITRS 2007Source: 2007 ITRS Winter Public Conf.40
4. SRAM cell scaling41
Intel Xeon 7400 Series(Dunnington)45 nm high-k 6 cores16MB shared L3 cacheSource: Intel Developer Forum 2008Cache occupies huge areaÆ Cell size of SRAM should be minimizedÆ However, Isd-leak should be minimizedÆ Vth are often designed to be higher than Min. logic VthÆ Lg are often designed to be larger than Min. logic Lg42
Intel’s SRAM test chip trend SRAM down-scaling trendhas been kept until 32nmand probably so to 22nmSource: B. Krzanich, S. Natrajan, Intel Developer’s Forum s/idffall m2005P126645nm2007P126832nm2009P127022nm2011Only schedule has been publishedTechnologyCell sizeCapacityChip areaFunctional Si90 nm Process1.0 µm2cell50 Mbit109 mm2February ‘0210180nmCell area (µm2)Process Lithography 1st 199565 nm Process0.57 µm2cell70 Mbit110 mm2April ‘0432nm2000Year45 nm Process0.346 µm2cell153 Mbit119 mm2January ‘062005201032 nm Process0.182 µm2cell291 Mbit118 mm2September ‘0743
22 nm technology 6T SRAM Cell: Size 0.1µmSource: 42.wssAnnounced on Aug 18, 2008Static noise marginof 220 mV at 0.9 VConsortium: IBM (NYSE) , AMD,Freescale, STMicroelectronics, Toshibaand the College of Nanoscale Scienceand Engineering (CNSE)0.1µm cell size is almoston the down-scaling trendNew technologies introduced- High-NA immersion lithography- High-K metal gate stacks- 25 nm gate lengths- Thin composite oxide-nitride spacers- Advanced activation techniques- Extremely thin silicideSource: IEDM2008 Pre-conference Publicity- Damascene copper contactshttp://www.btbmarketing.com/iedm/44
Cell size reduction trends1/2 or 2/3 per cycle?Cell area (µm2)1Functional Si65nm Apr.200445nm Jan.20060.57µm20.5IntelIntel32nm Sep.20070.35µm2TSMCConference (IEDM)45nm Dec.20070.24µm20.20.11/20.18µm232nm Dec.2007TSMCIBM Alliancepe0.15µm22r c /3 p IBM(Consortium)erycAllcyian 0.1µm2 Conference (IEDM)leclece32nm Dec.200765nm 45nm 32nm 22nmPress release22nm Aug.200845
Normalizedto 180nmNMOS Mismatch Coefficient (C2)improvement with technology scalingSource: K.J.KuhnIEDM 2007C246
Mismatch improvement “tall” design90nm :1.0 µm2by layout (Intel)“wide”design65nm :0.57 µm2Source: K. J. KuhnIEDM2007 Tech. Dig. pp.471“wide” design(Square endcaps)45nm 0.346 µm247
Double patterning for square endcapCell evolution is similarTSMC 32nmTSMC 45nmIEDM 2007IEDM 2007IBM Alliance 32nmSource: M. Bohr, ICSICT2008IEDM 2004IEDM 2008IBM Alliance 22nmTSMC 45nmTSMC 32nmIBM Gr. 32nm48
Most Difficult part of SRAM down-scaling isVdd down-scalingDensity of on-chip cache SRAM memory is highand thus, Vth cannot be down-scaled too muchbecause of large Isd-leakAlso, under low Vdd, read- and write margindegrades, data retention degrade.Thus, Vdd down-scaling is more severe in SRAMthan logic part of the circuits49
Nehalem(Intel) 2,4 or 8 CoresVoltage/FrequencyPartitioningDDR VccCore VccUncore VccChipDynamic PowerManagement8T SRAMCell32kB L1 I -cache32kB L1 D-cache256kB L2 -cacheCore6T SRAMCell8 MB L3 cacheSource: Intel Developer Forum 200850
6T and 8T Cell6T CellCell size is smallFor high density useAdd separateread function8T CellCell sizeincrease 30%For low voltage useSource: Morita et. al, Symp. on VLSI Circ. 200751
5. Roadmap for further futureas a Personal View52
-There will be still 4 6 cycles (or technology generations) left untilwe reach 11 5.5 nm technologies, at which we will reach downscaling limit, in some year between 2020-30 (H. Iwai, IWJT2008).-Even After reaching the down-scaling limit, we could still continueR & D, seeking sufficiently higher Id-sat under low Vdd.-Two candidates have emerged for R & D1. Nanowire/tube MOSFETs2. Alternative channel MOSFETs (III-V, Ge)- Other Beyond CMOS devices are still in the cloud.5.5nm?*3 important innovationsITRS figureedited by IwaiSource: 2008 ITRS Summer Public Conf.* 5.5nm? was added by Iwai53
Si nanowire FET with Semi-1D Ballistic TransportMerit of Si-nanowire 0Reduction in Ioff (Isd-leak)Good control ofIsd-leak bysurrounding gateSource: Y. Lee., T. Nagata., K. Kakushima.,K. Shiraishi, and H. Iwai, IWDTF 2008,Tokyo, November, 2008Trade offCarrier scattering probabilitySmallLarge# of quantum channelSmallLargeIncrease in Ion (Id-sat)High Conduction (1D)Go 77.8µS/wireMultiple quantum channel(QC) used for conductionHigh-density lateraland vertical integrationSource: T. Ohno, K. Shiraishi, and T. Ogawa, Phys. Rev. Lett. ,199254
Si nanowire FET as a strong candidateafter CMOS limitation1. Compatibility withcurrent CMOS processOff電流のcut-off2. Good controllability of IOFFカットオフ3. High drive current1D ballisticconductionDrainsourceMulti OFFHigh integrationof el量子チャネルQuantum channelk55
TEM imagegate electrode10nmLarge drive currentsidewallwireLg 160nm, Tox 3nm40Vd 1.0VVd 50mV10-710-910-11Lg 160nmTox 3nm(A)10x10nm210-1310-15-1.0-0.500.5D r a in c u r r e n t ( µ A )D r a in c u r r e n t ( A )10-310-5Advantage of Si nanowire1.0Gate voltage (V)Nice cut-off35 Vg-Vth 1.2V3025(step 0.2V)20Our nanowire FETION 0.25mA/µm (with 2010Litho. tech.)Lg 160nmTox 3.0nmWith 2019 litho. tech.151050Spec. in 2019 by ITRSION 2.3mA/µmLg 11nm, Tox 0.6nm0 0.2 0.4 0.6 0.8 1.0Drain voltage (V)High driveION 2.3mA/µm will beobtained even withLg 80nm and Tox 1.5nmby the courtesy of Professor H.Iwai56
Our roadmap for R &DSource: H. Iwai, IWJT 2008Current IssuesSi NanowireControl of wire surface propertySource Drain contactOptimization of wire diameterCompact I-V modelIII-V & Ge NanowireHigh-k gate insulatorWire formation techniqueCNT:Growth and integration of CNTWidth and Chirality controlChirality determines conductiontypes: metal or semiconductorGraphene:Graphene formation techniqueSuppression of off-currentVery small bandgap orno bandgap (semi-metal)Control of ribbon edge structurewhich affects bandgap57
(Gate length etc）SizeLong term roadmap for developmentSource: H. Iwai, IPFA 2006We do know system andalgorithms are important!But do not know how it canbe by us for use of bio?New Materials, New Process, New Structure（Logic, Memory)Hybrid integration of different functional ChipIncrease of SOC functionality3D integration of memory cell3D integration of logic devicesMiniaturization of Interconnectson ＰＣＢ(Printed Circuit Board)5 nm?Low cost for LSI processRevolution for ＣＲ，Equipment, WaferSaturation of DownsizingIntroduction of algorithmof bio-systemBrain of insects, humanWe do not know how?Some time in 2020 - 2030After 2050?58
Thank youfor your attention!59
Si MOSFET Roadmap for 22nm and beyond December 16, 2009 Hiroshi Iwai Tokyo Institute of Technology Jadavpur University @ Kolkata, India. 2 Outline 1. Scaling 4. SRAM Cell Scaling 2. ITRS Roadmap 3. Voltage Scaling/ Low Power and Leakage 5.Roadmap for further future. 3 1. Scaling. 4
MOSFET Cross Section. 9/14/2015 2 Power MOSFET in OhmicRegion MOSFET Static Characteristics. 9/14/2015 3 MOSFET Depletion capacitance MOSFET Equivalent Circuit. . Neglect semiconductor device capacitances, MOSFET switching times, etc. Neglect conduction losses Neglect ripple in inductor current and capacitor voltage. 9/14/2015 .
SiC MOSFET is the optimal fit for High Power, High Frequency and High Temperature applications SiC MOSFET. SiC MOSFET Driving Requirements 14 Driving a SiC MOSFET is almost as easy as driving a silicon MOSFET: Just need V GS 20V to get the right R DS(on)
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Understanding power MOSFET data sheet parameters Power MOSFET single-shot and repetitive avalanche ruggedness rating Using RC Thermal models LFPAK MOSFET thermal design – part 1 LFPAK MOSFET thermal design – part 2 Using power MOSFETs in parallel Designing RC snubbers Failure signature of electrical overstress on power MOSFETs Abbreviations
Depletion-mode MOSFET Enhancement-mode MOSFET Both types of MOSFET devices have either an n-channel or a p-channel depending on their added impurities. Note that the MOSFET
a depletion/enhancement MOSFET. The n-channel MOSFET operates in the depletion mode when a negative gate-to-source voltage (V GS) is applied and in the enhancement mode when a positive gate-to-source voltage (V GS) is applied. D-MOSFET are generally operated in the depletion mo
MOSFET models are either p-channel or n-channel models; they are classified according to level, such as Level 1 or Level 50. This chapter covers the design model and simulation aspects of MOSFET models, parameters of each model level, and associated equations. MOSFET diode and MOSFET capacitor model parameters and equations are also described.
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