NoC Verification And Testing Platform
Proceedings of the World Congress on Engineering and Computer Science 2015 Vol IWCECS 2015, October 21-23, 2015, San Francisco, USACollaborative Verification and TestingPlatform for NoC-based SoCYing Zhang, Member, IEEE, Ning Wu, Fen Ge and Xin ChenAbstract—Verification and testing play important roles incomplex system chip design, especially for NoC-based SoC,which has been increasingly applied to complex system design.This paper proposes a collaborative verification and testingplatform for NoC-based SoC. Based on VMM verificationmethodology, a hierarchical NoC validation platform isconstructed and assigned to the function verification of NoCcommunication. Simulations on Mesh and Torus NoCsvalidated the satisfying function coverage of the softwareverification platform. Besides, a reconfigurable NoC testingplatform is implemented based on PowerPC and FPGA. Someexperiments of the testing platform are performed on NoCswith ITC’02 benchmark circuits. The experiment resultsshowed that the testing platform established the hardwareverification and capable of evaluating testing time and otherparameters. The function verification information can betransmitted to the testing platform by certain interfaces toreconstruct NoC, meanwhile the hardware simulation resultscan be acquired by the software platform to improve the NoCdesign. So that, the collaborative hardware and softwareverification is accomplished.Index Terms—verification,co-verification, VMMWtestingplatform,NoC,I. INTRODUCTIONITH the increasing development of the semiconductortechnology and chip integration, NoC (Network onChip) becomes an important solution to complex SoC(System on Chip) architecture[1]. In the mean time, thecorresponding validation and testing assignments faceunprecedented challenges. According to statistics, designverification and testing are expected to account for more than70% of the whole design work for complex system chips [2].The verification and testing platform for NoC willaccomplish the function verification and performanceevaluation efficiently. Therefore, how to construct theverification and testing platform has great significance forNoC research and application.There have been some research [3-5] discussing on thedesign of verification platforms for NoC-based SoC. AuthorsManuscript received July 10, 2015; revised August 4, 2015. This workwas supported in part by the National Natural Science Foundation of China(61376025), the Aeronautical Science Foundation of China under Grant(20140652008), and Prospective Joint Research Project of on the Integrationof Industry, Education and Research of Jiangsu Province (2014003-05).Ying Zhang is with the College of Electronic and InformationEngineering, Nanjing University of Aeronautics and Astronautics, Nanjing,China (e-mail: tracy403@nuaa.edu.cn).Ning Wu, Fen Ge and Xin Chen are with the same place of Ying Zhang.(e-mail:wunee@nuaa.edu.cn,gefen@nuaa.edu.cn, xin chen@nuaa.edu.cn).ISBN: 978-988-19253-6-7ISSN: 2078-0958 (Print); ISSN: 2078-0966 (Online)of [3] proposed an automated verification environment forNoC. The simulation results on Spidergon-STNoC withCadence Specman are satisfying, but the verificationplatform only focuses on function verification. S. Chai et al.[4] proposed a NoC simulation and verification platformbased on SystemC. Simulated by loading different networktraffic patterns, the platform has been applied to verificationof NoC architecture and routing algorithm. Also, the platformdoes not involve the hardware verification. T. Huang et al. [5]introduced a verification platform for NoC with 16microprocessors based on FPGA. 4 4 Mesh topology andwormhole routing mechanism are applied to the verificationplatform and an OFDM transceiver is mapped on theplatform. The platform can be effective to hardwareverification, while its scalability is limited and size overheadis relatively high. Our proposed solution is to take intoaccount the needs of the hardware and software verificationat the same time, which will greatly decrease thecomprehensive testing time and increase the testingefficiency.We propose a software/hardware co-verification platformfor NoC-based SoC. Based on SystemVerilog and VMMmethodology, a hierarchical verification platform is designedto confirm the functions of NoC communication. At the sametime, a reconfigurable NoC testing platform is implementedbased on PowerPC and FPGA. The verification informationwill transfer between software platform and hardwareplatform, in order to modify the NoC mapped to FPGA andimprove the system design, thus forming the effectiveco-verification of NoC-based SoC.Hereafter, Section II gives a brief introduction of thesoftware/hardware co-verification platform for NoC. SectionIII presents the design of collaborative verification andtesting platform. Section IV explains the experiment resultson NoCs constructed with ITC’02 benchmark circuits.Section V draws the conclusions.II. HARDWARE/SOFTWARE CO-VERIFICATION PLATFORMFOR NOC-BASED SOCThe collaborative verification and testing platformproposed in this paper is applied to NoC-based SoCs. NoCscan be defined as a set of structured routers andpoint-to-point interconnecting IP cores (Resources). Thetopology of NoC can be represented as an undirectedconnected graph G(N,L), where N {n1,n2, ni} is the set ofnodes and L {l1,l2, lj} is the set of links in thecorresponding network. The widely applied topologies areMesh, Torus, Ring, Hypercube, and Fat-tree [6]. Forregularity of its structure, Mesh network are easy toWCECS 2015
Proceedings of the World Congress on Engineering and Computer Science 2015 Vol IWCECS 2015, October 21-23, 2015, San Francisco, USAimplement and have good scalability. Each node in Meshnetwork is connected to neighbors through regular gridpoint-to-point links.The architecture of software/hardware co-verificationplatform for NoC-based SoC is shown in Fig. 1. Softwareverification platform is meant to accomplish the validationprocess by certain software tools and construct theenvironment with different abstraction levels. Furthermore,the verification platform is aimed to ensure correct functionand satisfying performance parameters. Hardware testingplatform is based on the configurability of FPGA to realizemodules, structure and system level hardware verification ofthe NuT (NoC under Test). The reusability of hardwaretesting components will effectively improve adaptability andexpandability. Through the Ethernet or serial interface,information can share or exchange between software andhardware platform, so as to realize the collaborativeverification and testing.verification and testing platform can implementindependent verification and testing process. So thatparallel application of verification and testing can berealized in theory and in practice.2. Information sharing between verification and testing.Errors found by verification and testing platform will beeasily notified to each other. Furthermore, the informationcan be used as the reference of the other. When there is anerror in any one of platforms, verification or testingprocess will be retriggered.3. Hierarchical and reusable feature of validation andtesting methods.Verification platform is built based on the VMMverification methodology and has the characteristics of thehierarchical and reusability. Testing platform consists ofmodular components and test structure can be onlinereconfigured to provide reusable characteristics.The design process of proposed collaborativeverification and testing platform is shown in Fig. 2.Function coverageFig. 1. Diagram of the software/hardware co-verification platformThe software validation environment in Fig. 1 providesthe transaction level based on VMM verification methodand the RTL level verification based on SystemVerilog orVerilog, etc. The input files of software verificationplatform include the test data files and hardwaredescription files of NuT. After acquiring data from thefiles, the platform will come into effect according to thepredetermined validation process. Validation results willbe compared with ideal results in the test files andcomparison results will be in the form of assertions in theoutput of the verification platform. If the results do notagree with the ideal results, which means design errorsexist, information will be sent to the test files and designmodules. And there will be the corresponding revise andresolution later. If the results of the hardware testingplatform show the need to modify the structure design, theanalysis report will be transmitted to the verificationplatform by the interfaces between two platforms.The hardware testing platform in Fig. 1 is based onmicrocontroller and FPGA and under test NoC is mappedto the FPGA. The function and performance of the systemchip can be tested through JTAG or Chipscope tool andtest results will compare with the ideal responses. Thecomparison results will be analyzed on-line or transmittedto the PC and the analysis results will feedback to softwareplatform, or remap directly to the hardware platform aftermodification.The verification and testing platform for NoC-basedSoC has the following features:1. Parallel implementation of verification and testing.As long as respectively obtained the required input,ISBN: 978-988-19253-6-7ISSN: 2078-0958 (Print); ISSN: 2078-0966 (Online)Fig. 2. Design process of the collaborative platformFirst of all, according to the requirement of thevalidation plan and system testing parameters, validationand testing behavior is divided into hardware and softwareverification objective. Software platform adopts the VMMmethodology to build hierarchical structure and consist oftesting layer, scenario layer, function layer, commandlayer, and signal layer. Each level provides a series ofservices to the upper level hiding low-level details throughthe abstract processing. Test cases are usually located inthe top of the verification platform, but in the practicalapplication, they can bypass other levels or interact withany component in order to achieve direct access to undertest parts. The flexibility of test cases and testingconfiguration makes it easy to implement the design ofsoftware verification platform. In the hardware platform,the behavior level, RTL level and logic level of under testNoC can be mapped to the FPGA, cooperating with themicrocontroller and basic peripheral interfaces providedby IP library, along with testing controller, memorymodules, etc. In that way, an efficient hardware testingplatform can be configured. Through appropriatemodification and module replacement, NoC can be easilyremapped on the software and hardware verificationplatform.WCECS 2015
Proceedings of the World Congress on Engineering and Computer Science 2015 Vol IWCECS 2015, October 21-23, 2015, San Francisco, USAIII. DESIGN OF COLLABORATIVE VERIFICATION ANDTESTING PLATFORM FOR NOC-BASED SOCThe hierarchical NoC verification platform is based on theVMM methodology, which adopts assertions, abstraction,automation, reuse mechanism in order to improve validationand productivity [10]. The platform is composed of multiplelevels of description and can react to each layer in the wholedesign process. Each level can provide services to its upperlevel or test cases, and hide low-level details by means ofabstraction. Different Layers are neatly partitioned and theflow transmission is achieved through channel mechanism.The verification platform contains multiple-layered testmodules and controls four steps of the test process, whichincludes generating random test vectors, establishingverification environment, executing verification andproducing the reports. The basic structure of the platform isshowed as Fig. 3, which consists of test cases, test vectorgenerator, test environment and NoC under test. Theenvironment includes driver module, monitor module,checker module, scoreboard module and function coveragemodule.the building, operating and ending of test process.The Config class determines whether send packets to thespecific node or not and the quantity of packets. According tothe configuration information, RU generator is responsiblefor generating random packets with constraints and sendingthem to next layer through the channel.The Driver receives packets from RU generator, thensends them to NoC and transmits to the Scoreboard throughcallback at the same time. Monitor concentrates on outputpackets from NoC and transmit data to the Scoreboard andCoverage class. Scoreboard achieves the expected packetsfrom Driver, gets actual packets from Monitor, thencompares them and induces the result.The Coverage class defines the related cover point and canmodify constraints based on the result of simulation.Function coverage is the important parameter to evaluate theefficiency of the verification platform, which refers to thevalidated function percentage of all the functions.Fig. 3. Basic structure of the hierarchical NoC testbenchAccording to the multi-layered infrastructure, theverification platform can be divided into Test layer, Scenariolayer, Function layer, Instruction layer and NoC under Test.Test layer provides test cases and the realization of testcases is the combination of the following elements:additional constraints of generator, new definition of randomscenes (scripts), synchronization mechanism betweentransaction processors, state monitor and directed stimulationfor the original design. Scenario layer provides generators ofdata and transactions which can be controlled andsynchronized. Function layer contains high-level driver andmonitor modules and can confirm verification results.Instruction layer is related to various interfaces and physicalprotocols of NuT. It provides a consistent and low-levelinterface which is not relevant to the modeling manner. TheRTL model is connected to the upper level module throughthe interface. An interface can be regarded as a bundle ofintelligent connections, which contain connection,synchronization, communication between two or moremodules.Each module of the verification platform is realized in theform of certain class, the UML class diagram to explain theirrelationship is shown as Fig. 4.The Environment class is the core of the verificationplatform. It is almost related to all the modules and controlsISBN: 978-988-19253-6-7ISSN: 2078-0958 (Print); ISSN: 2078-0966 (Online)Fig. 4. UML class diagram of NoC verification platformIn order to simulate system chip in module level and circuitlevel, we proposes a reusable multi-level testing platform forNoC-based SoC. The testing platform structure is shown asFig. 5.Fig. 5. Architecture of NoC testing platformWCECS 2015
Proceedings of the World Congress on Engineering and Computer Science 2015 Vol IWCECS 2015, October 21-23, 2015, San Francisco, USAAcquiring function verification information from softwareplatform, testing platform is constructed based onconfigurable interconnection modules. Moreover, testgeneration and test data analysis module are designed tosupport offline and online testing. The hardware platform notonly can be applied to NoC performance evaluation, but alsocan implement hardware validation for testing structure andtesting strategy.PowerPC (CPU) is responsible for interfaces managementand controlling data exchange between the PC and the FPGAon the testing platform. Test stimulus and response data canbe stored in the DDR or SATA and the FPGA configurationcan be accomplished through the JTAG input or online by thePROM. Hardware configuration and test process for NoC isshown in Fig. 6. Firstly, according to specific application, tothe size, topology and routing rules of the NoC will bedetermined. After that, the NoC mapping can be realized withthe corresponding test structure and traffic status. Then,configuration information will be provided to generatereconfigurable routers and corresponding configuration file.Test stimulus and ideal response data are generated by thesoftware on PC and transmitted to the testing platform.Finally, test response data can be stored in the chip ortransmitted to the PC and test results can be analyzed onlineor done post-process by the software on the PC.based on collaborative optimization of testing and mappingfor NoC [10], and the NoC mapping in Fig. 7 is on thecondition of W 16, α β 0.5 . TAS (Test Access Switch)in Fig. 7 means the testing data input/output port. To achievethe systemic reusability of the testing platform, theinterconnection mechanism with adaptable routing algorithmand the construction of online configuration mode arerequired in testing platform. The structure of reconfigurablenetwork interface and other modules will be demonstrated indetail later.Fig. 7. Diagram of internal modules in FPGA (W 16, g1023)z Network interface moduleNetwork interface (NI) is the bridge between localsynchronization system and NoC data transmission channel.Its main function is to provide network adapter services forIP cores, similar to the modem of computer network. Itimplements the separation of the communication andcomputing of NoC and this makes the IP core selection moreconcentrated to the function realization instead ofconsidering the communication architecture. The uppermodule of NI is the Core Interface (CI), while the lowerconnection module is routing interface module. Besidesrealizes the network protocol conversion between differentlevels, NI can also feedback part of the state information tothe local IP Core. So that, dynamic configuration willimplement and obtain better performance and functionalflexibility. The structure of network interface circuit is shownas Fig. 8.Fig. 6. Flow chart of hardware configuration and testingDynamic reconfiguration routing module is one of themain components on testing platform and it is composed ofTraffic Generator (TG), Traffic Receiver (TR), NetworkInterface (NI) and the reconfigurable router. Fig. 7 describesthe main function modules of FPGA and interface moduleson test platform. It adopts g1023 circuit of ITC’02benchmark [8] to map on 4 4 Mesh as an example. Test dataare transmitted into the Mesh network by the PowerPC orDDR module, and will be forwarded to another router orlocal IP core according to the routing algorithm, while eachIP core being with the IEEE 1500 compatible test wrappersupporting multi testing modes [9]. NoC mapping is realizedISBN: 978-988-19253-6-7ISSN: 2078-0958 (Print); ISSN: 2078-0966 (Online)Fig. 8. Architecture of network interface moduleNI is mainly composed of routing interface, data buffer,input/output channel management, pack/unpack module, etc.Routing module is applied to transform between differentclock domains, transfer order, end-to-end flow control, etc.Input/output management modules acknowledge to thetransmission network according to the buffer situation, themodules are mostly reconfigurable to support variouscommunication architectures.WCECS 2015
Proceedings of the World Congress on Engineering and Computer Science 2015 Vol IWCECS 2015, October 21-23, 2015, San Francisco, USAz Configuration moduleConfiguration information is in a binary file generated bythe PC, which contains three types of information:information of interconnection network (nodes, interconnect,network structure), information of the router structure(reconfigurable options), information of test data (TASaccess, test data packet format, transmission bandwidth). Theconfiguration file are transferred to CPLD from the CPU andstored in the Block Ram and registers of the CPLD. Thedisassembly module of CPLD will translate binary data inconfiguration file into corresponding control information ofNoC and modify them into synthesizable RTL codes, finallydownloaded to the FPGA. The process of configurationrelated modules structure is shown in Fig. 9.Configuation fileNetworkarchitectureinformationverification platform is provided. The simulation onSynopsys VCS with the 4 4 Torus NoC is shown as Fig. 11.In addition, the simulation on ModelSim with 4 4 MeshNoC is shown as Fig.12. The results in Fig.11 and Fig.12show that the data transmission among different IP cores isconsistent with the preset data, which verifies the correctnessof the data transmission function of the NoC. The softwareplatform can be easily adapted to other topology anddimension NoCs.CPLDLocal BusRouterRouterarchitectureinformationTGTest datainformationTRDynamicdownloadFPGAFig. 9. Diagram of configuration modulez Ethernet moduleDiagram of Ethernet data transmission processing isshown in Fig. 10. Ethernet module implements the datacommunication between the FPGA chip and Ethernetphysical layer (PHY). Data in the FPGA chip will packet andoutput through the PHY port and the data sent to PHY will befiltered and unpacked for transmition to the FPGA. Ethernetmodule mainly includes MAC IP core and UDP/IP protocolstack.Fig. 11. Veification platform simulation results on VCSFig. 10. Diagram of Ethernet data transmissionMAC IP core module includes client FIFO, AXI4-Litestate control machine and the physical layer interfacemodule.UDP/IP protocol stack module implements the UDP, IPv4,ARP protocol. The connection delay of the MAC layercontrol module is zero. The source port and destination portof sending UDP packets are completely controllable. Whendata are sent, they are allowed to be filtered through thesource port to the destination port. Sending and receivingdata from the IP layer broadcast address are both supported.The sending and receiving clock domain are independent ofeach other. The function of protocol stack has been verifiedin the 1 GBPS Ethernet field.IV. PERFORMANCE EVALUATION OF COLLABORATIVEVERIFICATION AND TESTING PLATFORMIn order to evaluate the proposed collaborative verificationand testing platform, some experiments are applied to NoCswith circuits of ITC'02 benchmark. Firstly, the simulation ofISBN: 978-988-19253-6-7ISSN: 2078-0958 (Print); ISSN: 2078-0966 (Online)Fig. 12. Veification platform simulation results on ModelSimChoosing g1023 circuit as the example and setting thesystem clock to 100 MHZ, test optimization mapping resultof testing platform is shown in Fig. 7. The test data of IP3 areoutput from FPGA to PowerPC through SGMII or PCIE,then transferred to the PC by serial or Ethernet ports, and thedata can also be stored in DDR3 of the testing platform. Thetest data transmission process is shown in Fig. 13. Becausethe capture range of Xilinx ISE Chipscope is limited, onlyone segment of the test response data is provided.Since the IP core in testing platform is not concrete logiccircuit, the experiment applies the preset test data, forexample, the input data for IP3 is 00000050, thecorresponding output data for 30000050, which can be seenin Fig 13 (a). Figure 13 (b) (c) show the corresponding testdata of the PCIE and Ethernet interface, later the data will betransmitted to the PC, which means to be sent to theverification platform. The same test data can be stored in theDDR, which are available for online test analysis, as Figure5.21 (d) shows. Note that the word width of the PCIE,WCECS 2015
Proceedings of the World Congress on Engineering and Computer Science 2015 Vol IWCECS 2015, October 21-23, 2015, San Francisco, USAEthernet, DDR is 64bit, while the original test data is 32bit.a) The test data of IP3 in the FPGAFig. 14. Photo of the test platformV. CONCLUSIONb) Output of test data through PCIEc) Output of test data through Ethernetd) Test data is output to DDR3Fig. 13. Test data transmission processThe testing optimized NoC mapping for g1023 circuit areapplied to different optimization proportions under testingplatform and comparison results of test time is shown inTABLE I. (the time unit in TABLE I is the number of clockcycles).TABLE ITHE TEST TIME OF TEST PLATFORMOptimization proportionα β 0.5W 16α 1, β 0Tc 1Tc 2Tc 3Tc 4Tmax7405 16863 15597 15003 1559714570 11275 14923 14108 14923α 0.8, β 0.2 13727 15003 10990 15148 15148W 32α β 0.5 .15597 12444 6369 15338 15597α 1, β 012721 10875 14916 11237 14916α 0.8, β 0.2 12149 14989 11057 11553 14989The result in TABLE I show that test time optimizationresults of hardware emulation are consistent with theoreticalalgorithm analysis [10], which not only verifies the validityof the testing optimized NoC mapping algorithm, but alsoshowed the effectiveness of the collaborative software andhardware platform.Fig. 14 shows the photo of the hardware platform. The ICunder the heat sink of bottom right is Freescale PowerPCP1010 and under heat sink of upper right (beside DDR slots)is Xilinx FPGA ffg900 XC7k325T-2.ISBN: 978-988-19253-6-7ISSN: 2078-0958 (Print); ISSN: 2078-0966 (Online)This paper presents the design of the software andhardware collaborative verification platform for the NoC.Based on SystemVerilog and VMM methodology, amulti-level NoC verification platform is constructed. Thesoftware platform can validate the NoC communicationfunction and easily adaptable to various network structures.With reconfigurable router module and RTL model of thecommunication structure, NoCs are mapped on the FPGA oftesting platform. The experiments on NoCs with ITC '02benchmark circuits indicated that the verification and testingplatform can effectively realize the on-chip NoC paralleltesting and can accomplish dynamic configuration. Dataexchange between the testing platform and the verificationplatform is implemented by the Ethernet and serial interfaces,so as to realizing the software and hardware co-verification.Moreover, the collaborative verification and testing platformcan be applied to analysis function and testing parameters.REFERENCES[1]T. Bjerregaard and S.A. Mahadevan. “Survey of Research andPractices of Network-on-Chip,” ACM Computing Surveys, vol. 38, no.1, 2006, pp. 1–51.[2] Chris Spear, SystemVerilog for Verification, Synopsys,Inc. 2006.[3] F. Vitullo, S. Saponara, E. Petri, et al. “A reusable coverage-drivenverification environment for Network-on-Chip communication inembedded system platforms,” in Proc. 7th IEEE Workshop onIntelligent solutions in Embedded Systems, Ancona, 2009, pp. 71–77.[4] S. Chai, C. Wu, Y. Li, et al. “A NoC simulation and verificationplatform based on SystemC,” in Proc. 2008 Computer Science andSoftware Engineering Conf., Wuhan, 2008, pp. 423–426.[5] T. Huang, Y. Chen, J. Hu, et al. “Network-on-chip emulator designwith FPGA array,” in Proc. 2010 ICCCAS Conf., Chengdu, 2010, pp.886–890.[6] Tayan, O. “Networks-on-Chip: Challenges, trends and mechanisms forenhancements,” in Proc. ICICT'09 Conf. Information andCommunication Technologies, Karachi, 2009, pp. 57–62.[7] J. Bergeron, E. Cerny, A. Hunter and A. Nightingale, “VerificationMethodology Manual for SystemVerilog”, Synopsys & ARM, Inc.2006.[8] E.J. Marinissen, V. Iyengar and K. Chakrabart[9] y. “A Set of Benchmarks for Modular Testing of SOCs,” in Proc.ITC’02 Conf., 2002, pp. 519–528.[10] Y. Zhang, N. Wu, F. Ge and L. Zhou. “Novel Core Test WrapperDesign Supporting Multi-mode Testing of NoC-based SoC,” IJCA, vol.6, no. 5, 2013, pp. 247–262.[11] Y. Zhang, N. Wu, F. Ge and X. Chen. “Collaborative Optimization ofTesting and Mapping for Network on Chip,” IEEE Trans. OnCAD/ICS(TCAD), submitted for publication.WCECS 2015
complex system chip design, especially for NoC-based SoC, which has been increasingly applied to complex system design. This paper proposes a collaborative verification and testing platform for NoC-based SoC. Based on VMM verification methodology, a hierarchical NoC validation platform is constructed and assigned to the function verification of NoC
May 2020 NOC April 2020 NOC March 2020 Modification of Section IV Table 11C.1 (New provision symbols: 30B#6.21N_1, 30B#6.21N_2) February 2020 NOC January 2020 Modification of Section II Chapter 1 and Chapter 2 with new Special Sections: AP30/P and AP/30A/P. December 2019 NOC November 2019 NOC October 2019 NOC September 2019
Once the design of the basic NOC architecture became established, new techniques evolved to address advanced issues such as dynamic load balancing on to a node of the NOC architecture, the shortest/fastest path for the data flow through NOC, and energy efficient NOC architecture design. Most researchers have focused on the
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Our NOC obtains both area and en-ergy benefits without compromising either performance or QOS guarantees. In a notional 256mm2 high-end chip, the proposed NOC consumes under 7% of the overall area and 23.5W of power at a sustained network load of 10%, a mod-est fraction of the overall power budget. Table 1: Scalability of NOC topologies. k .
To overcome these limitations, we propose an NoC-enabled PIM-based architecture that amalgamates: (a) multiple logic layers in conventional PIM, (b) M3D-based vertical integration, and (c) efficient 3D-NoC design for high-performance k-mer counting, while remaining within 85ᵒC temperature. To take advantage of and aid NoC design, we also
NOC The nursing outcomes classification (NOC) is a classification of nurse sensitive outcomes NOC outcomes and indicators allow for measurement of the patient, family, or community outcome at any point on a continuum from most negative to most positive and at different points in time. ( Iowa Outcome Project, 2008)
C. NoC Arbitration as a Reinforcement Learning Problem Reinforcement learning can be applied to the problem of NoC arbitration to learn an efficient arbitration policy for a given NoC topology. We can train the agent (a recommen-dation system for the arbiter) such that for a given state (a collection of input buffers at a router all competing for
Key elements of the Business Architecture may be produced elsewhere The enterprise mission, vision, strategy and goals may be produced as part of a wider business strategy or enterprise planning activity with its own life-cycle in the enterprise. The new architecture work will need to verify and update the currently documented business strategy and plans, and/or to bridge between high-level .
