Semiconductor Industry Speaker Series - MEPTEC
Semiconductor Industry Speaker Series“An EDA Perspective:What’s the Difference Between HeterogenousIntegration and System in Package (SiP)John ParkCadence Design SystemMarch 10, 2021www.meptec.orgwww.imaps.org
An EDA Perspective: What’s the Difference BetweenHeterogenous Integration and System in Package (SiP)John ParkAdvanced IC Packaging and Cross-Platform Solutions
OutlineOverview of SiP vs Heterogenous IntegrationWhat’s Driving Heterogenous Integration TrendsDesign Challenges for Heterogenous ArchitecturesDesign Flows for Next-Gen Packaging2 2020 Cadence Design Systems, Inc. All rights reserved.
Evolution of Advanced Multi-Chip(let) Packaging TechnologiesSystem inPackage(SiP)19983RF Module2004 2020 Cadence Design Systems, Inc. All rights reserved.2.5D-IC(Silicon Ultra-High-Density rogeneousIntegrationCo-PackagedOpticsNowFuture
SiP/MCM vs. Chiplet-Based (Heterogeneous Integration) ArchitecturesNew: The transition from system on a chip (SoC) to system in a package (SiP)BareDieUnpackaged dieChipletBareDieLaminateSubstratePCB to MCM/SiP pletBoard size/complexity reduction (SWaP)Disaggregated iconSubstrateSoC to HI BenefitsSmaller footprintReduced NRE costsPCB simplificationShorter time to marketHigher bandwidthLarger than reticle size designsLower powerMore flexible architectures 2020 Cadence Design Systems, Inc. All rights reserved.
Heterogenous Integration is Just a Different Way of LogicallyPartitioning an SoC and is Independent of Packaging Technology Leveraging SiP design-style approachbecoming a viable alternative to monolithic SoC– Modular approach vs monolithic approach– Not every logic function (IP) needs to be designed inthe same process node (heterogeneous integration)– Leveraging IP in the form of chiplets– IP that is physically realized working on astandard communication interface– Similar to board-level design– Multiple options are available for “packaging” chipletsChiplet– Includes latest IC packaging 2.5D/3D-IC,FOWLP and embedded bridgesSoft IPHard IPGDSII layoutTied to specifictechnology/node5 2020 Cadence Design Systems, Inc. All rights reserved.Synthesizable RTLGate-level netlistCan be targeted tospecifictechnology/nodePhysically realized andtested (hardened) IPwrapped with micro-buffersdriving standardcommunication interface,level-shifting, etc
SiP vs. Heterogenous IntegrationSystem in a Package (SiP)Heterogenous ller formfactorMuch lower costthan transition toSoCModularized/Disaggregate SoCReduced cost(relative toadvanced nodeSoC)Design/architecture flexibility andreduced time tomarketSchematic-drivenPCB-like designflowLittle/no STAMin/max/matchedrouting lengthsText/languagedriven IC-likedesign flowStill requiresformal IC-likesign-off processMin/max/matchinterconnect tomeet timingMoves devicescloser together(unpackagedchips)Shorter signalpaths, less powerBigger thermalchallengeDevices fatherapart (multiplechiplets)Longer signalpaths, more IO,larger form-factorBigger thermalchallenge when3D stackingEvery chiplet isflip-chip-likeattach55um and smallerpitchSiliconAlso, glass,embeddedbridges & FOWLPIntegration fabric6Flip-chip attach100um-180umBond-wire attachCan be stackedLaminate/organicsubstratesCeramic (LTCC) 2020 Cadence Design Systems, Inc. All rights reserved.Targetedintegration fabricWhy would we want to do this?What happened to PPA?
OutlineOverview of SiP vs Heterogenous IntegrationWhat’s Driving Heterogenous Integration TrendsDesign Challenges for Heterogenous ArchitecturesDesign Flows for Next-Gen Packaging7 2020 Cadence Design Systems, Inc. All rights reserved.
The End of Moore’s Law & The Beginning of “More-Than-Moore”For the past five decades, the electronic industry has thrived while enjoying thebenefits of Moore’s Law. But things are changing The economics ofsemiconductor logic scaling are gone Gordon Moore knew this day would come. He also predicted that ”It may prove tobe more economical to build large systems out of smaller functions, which areseparately packaged and interconnected.”Providing a possible alternative to advanced monolithic SoCs, multi-chiplet SiPshave become a very attractive option for cost-sensitive complex designsThe generation of “More Than Moore” is here 8 2020 Cadence Design Systems, Inc. All rights reserved.
The End of Moore’s Law Really? It’s more than the limitations of physics Cost per transistor has steadily increased since2012/3 (28nm) Designing IC’s at the latest nodes is hard andexpensive Low-volume businesses can’t justify the NRE costs ofdesigning an SoC at the latest node Requires huge teams of engineering specialists thataren’t always easy to find Systems and software companies now designing chipsand challenging the status-quo of SoC approach Today’s SoCs are reaching reticle limits but bigchips typically don’t yield anyways* More analog/RF content in today’s designs Analog/RF never have benefited from transistor scaling Cost of Analog IP recertification at every node probablydoesn’t make sense in many cases9 2020 Cadence Design Systems, Inc. All rights reserved.System on a Chip Design Costs ( M)35030025020015010050028nm22nm16nm10nm7nm
Why Large Die Don’t Yield?Big ChipsSmall Chips Defect Same size wafer, same number of defects: The wafer on the left produces 10 working chips - (62% yield) The wafer on the right produces 72 working chip(let)s - (92% yield)10 2020 Cadence Design Systems, Inc. All rights reserved.
Getting Your Chip Built, The Options Are 1610nm20187nm20205/3nm2022 2020 Cadence Design Systems, Inc. All rights reserved.633
The World of IC Design Turns To Packaging 3D Stacking is Old NewsPackage on Package (PoP)Wire-bonded199812 2020 Cadence Design Systems, Inc. All rights reserved.2002Multi-Die Packaging is Decades OldMulti-Chip-ModuleMCMWafer on waferChip(s) on wafer20152018System-in-a-packageSiPBump-less2020RF ModuleMonolithic 3D-ICTransistor stackingFuture
Final Hurdles for Chiplets to Move into MainstreamCommercialization/standardization of chipletsInterface ConsiderationsSerial, Parallel or Proprietary Today most chiplet-based designs are single vendorPackage type– Closed ecosystemReach The next step forward will likely require commercializationof chiplets– Standards and business model needed before IP companies proceed Ongoing work to define standards for chiplet-to-chipletcommunication interface and data-exchange formats– Must be low power, low BER and low latency No single PHY can do it all– Open Compute Project (OCP) and USG programs– BoW, OpenHBI, XSR, AIB, – What about Analog/RF?– What about test/KGD? Who “owns” design yield?– Who manages chiplet inventory. Board part providers? Will compromised PPA be acceptable for allapplications?13 2020 Cadence Design Systems, Inc. All rights reserved.Power (pJ/bit)LatencySpeedBandwidthRouting complexityTest, ESD, ?Monolithic eptable?PerformanceAcceptable?AreaAcceptable?
OutlineOverview of SiP vs Heterogenous IntegrationWhat’s Driving Heterogenous Integration TrendsDesign Challenges for Heterogenous ArchitecturesDesign Flows for Next-Gen Packaging14 2020 Cadence Design Systems, Inc. All rights reserved.
Bottom Line Design and Verification is Only Getting us velThermalMechanical15 2020 Cadence Design Systems, Inc. All rights reserved.
Design Tool/Flow Challenges for The Entire Layout Chain Requires design tools and flows that support crossfunctional collaboration (co-design) for all design teams– Complete system-level visualization in a single toolPackagingPCBDigitalICAnalogIC– With the ability to optimize the system-level design and crossdomain interconnect– Pin-out and floorplan (including stack) optimization– Signal name aliasing across domains– Direct read/write into multiplelayout domains and tools– Editing environment with userspecific design orientation– Cross-domain ECO loop– Domain-specific editing controls– Accept/Reject changesSystem-Level View16 2020 Cadence Design Systems, Inc. All rights reserved.Chip(let)-Level View
Design Tool/Flow Challenges for the Ecosystem Assembly Design Kits (ADK) Looking Beyond Design-Rule Manuals andReference Designs TechFilesLayer stack-upDesign GAThickness3D MechanicalPhysical/Electricallayout constraintsDevice placementconstraints basedon assembly pick &place equipmentCompliance KitsElectrical specvalidation ofchip(let)-to-chip(let)interfaces*Die to die spacingJitter toleranceBond-Wire profilesDevice to deviceInsertion lossIO modelsDevice to obstacleReturn lossThermal modelsPower models17Assembly Rules 2020 Cadence Design Systems, Inc. All rights reserved.Eye maskManufacturing RulesBoard/substratemanufacturing processRule DecksFoundry/semiconductormanufacturing processSubstrate checksDRCSoldermask checksLVSSoldering issuesMetal fillSilkscreen checks
Design Tool/Flow Challenges for the Package Design Team Advanced multi-chip(let) silicon-based packages requirespecialized layout features and formal physical/logical verificationcapabilities Layout features specific to silicon substrate designs– Advanced filleting and trace widening– Progressive shape and pad degassing algorithms– High-capacity design support Mask-level accurate output data (GDSII) from substrate layout tool– Advanced arc vectorization Seamless integration with IC physical verification tool with feedbackloop to layout1. Mask-level DRC2. Connectivity verification (LVS) of multi-chip(let) designs3. Region specific advanced metal fill (balancing)18 2020 Cadence Design Systems, Inc. All rights reserved.
Design Tool/Flow Challenges for the IC Design Architect Top-level design aggregation, management and system-level optimization– Integrated with sign-off tools for stack alignment and layout vs schematic (LVS) checkingStackManagementHierarchical DesignManagement19 2020 Cadence Design Systems, Inc. All rights reserved.Interface AlignmentValidationSystem-LevelConnectivity VerificationHierarchical Signal MappingAdvancedBump/TSV PlanningSystem-Level Connectivity Optimization
Design Tool/Flow Challenges for Electrical/Thermal Analysis Analysis at the system level requires multiple simulation solutions On-chip and off-chip EM modeling and analysis Device, interconnectand antenna Layout conditioning Chip/package/boardcross-domain coupling Back-annotation totop-level design In-design analysis andelectrical sign-offverification Thermal coupled withpower analysis Thermal self-heatingcoupled with CFD Seamless integrationwith layout tools20 2020 Cadence Design Systems, Inc. All rights reserved.
OutlineOverview of SiP vs Heterogenous IntegrationWhat’s Driving Heterogenous Integration TrendsDesign Challenges for Heterogenous ArchitecturesDesign Flows for Next-Gen Packaging21 2020 Cadence Design Systems, Inc. All rights reserved.
Transitioning to System-Level Design/Analysis Tools/FlowsMulti-Chip(let) DesignPlanning, Optimizationand ManagementDigital ICAnalog/RFIC/MMICInterposerFanout RDLBGA/LGAStackSystem-Level Design Planning and AggregationDesignImplementationDigital/SoC DesignAnalog/RFIC/MMIC DesignMulti-Chip(let)Package DesignPrinted Circuit Board DesignMulti-Chip(let)Electrical/ThermalAnalysis and Sign-OffOn/Off-Chip(let) Extraction22 2020 Cadence Design Systems, Inc. All rights reserved.Thermal AnalysisSignal/Power IntegrityChip-Stack EM/IREMI Analysis
Example of System-Level Co-Design/Analysis Flow for HISystem-LevelUnified LibraryHierarchical Top-Level SchematicRepresenting Complete System-Level SVSSRX1TX1RGBVCCPCBLayoutMask-LevelPhysical Verification(DRC/LVS)Tape-OutMIXIFRF 23Digital Chiplet 2020 Cadence Design Systems, Inc. All rights reserved.VCOMWave ChipletAnalog Chiplet
Question: What Is This?It’s Certainly “More Than Moore”. But is it Heterogenous Integration?24 2020 Cadence Design Systems, Inc. All rights reserved.
ConclusionWe have entered the More-than-More era andelectronic design will get harderSiP technologies being leveraged by IC designers tocreate heterogeneously integrated architecturesNew challenges face package designers and ICdesignersNew design tools and flows will be required25 2020 Cadence Design Systems, Inc. All rights reserved.
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Packaging Technologies Being Targeted for Heterogenous ferStacking(3D-IC) 2020 Cadence Design Systems, Inc. All rights reserved.
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Analysis and Sign-Off Transitioning to System-Level Design/Analysis Tools/Flows EMI Analysis Digital/SoC Design System-Level Design Planning and Aggregation Digital IC Analog/ RFIC/MMIC Interposer BGA/LGA Stack Analog/RFIC/MMIC Design Printed Circuit Board Design Signal/Power Integrity Design Implementation Multi-Chip(let) Package Design
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2.2 Jobs impact of the semiconductor industry 8 2.2.1 Jobs multiplier 10 3. The semiconductor workforce 11 3.1 Semiconductor workforce by state 11 3.1.1 Location quotients 12 3.2 Occupational profile 13 3.3 People who work in the semiconductor industry 14 3.3.1 Race and ethnicity 14 3.3.2 Age distribution 15
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