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IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, andVerification LanguageIEEE Computer Societyand theIEEE Standards Association Corporate Advisory GroupSponsored by theDesign Automation Standards CommitteeIEEE3 Park AvenueNew York, NY 10016-5997USA21 February 2013IEEE Std 1800 -2012(Revision ofIEEE Std 1800-2009)

IEEE Std 1800 -2012(Revision ofIEEE Std 1800-2009)IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, andVerification LanguageSponsorDesign Automation Standards Committeeof theIEEE Computer Societyand theIEEE Standards Association Corporate Advisory GroupApproved 5 December 2012IEEE-SA Standards Board

Abstract: The definition of the language syntax and semantics for SystemVerilog, which is a unifiedhardware design, specification, and verification language, is provided. This standard includessupport for modeling hardware at the behavioral, register transfer level (RTL), and gate-levelabstraction levels, and for writing testbenches using coverage, assertions, object-orientedprogramming, and constrained random verification. The standard also provides applicationprogramming interfaces (APIs) to foreign programming languages.Keywords: assertions, design automation, design verification, hardware description language,HDL, HDVL, IEEE 1800 , PLI, programming language interface, SystemVerilog, Verilog , VPIThe Institute of Electrical and Electronics Engineers, Inc.3 Park Avenue, New York, NY 10016-5997, USACopyright 2013 by The Institute of Electrical and Electronics Engineers, Inc.All rights reserved. Published 21 February 2013. Printed in the United States of America.IEEE, 802, and POSIX are registered trademarks in the U.S. Patent & Trademark Office, owned by The Institute ofElectrical and Electronics Engineers, Incorporated.Verilog is a registered trademark of Cadence Design Systems, Inc.P'): ISBN 978-0-7381-811 - 67'GT PULQW: ISBN 978-0-7381-811 - STDPD98078IEEE prohibits discrimination, harassment and bullying. For more information, visit -26.html.No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the prior written permission of thepublisher.

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ParticipantsThe SystemVerilog Language Working Group is entity based. At the time this standard was completed,the SystemVerilog Working Group had the following membership:Karen Pieper, Accellera Representative, Tabula, Inc., ChairNeil Korpusik, Oracle Corporation, Vice Chair, Technical ChairDennis Brophy, Mentor Graphics Corporation, SecretaryStuart Sutherland, Sutherland HDL, Inc., Technical EditorDmitry Korchemny, Intel CorporationDave Rich, Mentor Graphics CorporationNeil Sensarkar, Marvell Technology Group Ltd.Yatin Trivedi, Synopsys, Inc.Tony Tsai, Cisco Systems, Inc.Shalom Bresticker, Intel CorporationCharles Dawson, Cadence Design Systems, Inc.Josef Derner, Mentor Graphics CorporationJohn Goodenough, ARM, Ltd.Kaiming Ho, Fraunhofer IISHaim Kerem, Intel CorporationWork on this standard was divided among primary committees.The Champions Committee was responsible for ensuring consistency in the work done by each committee.Neil Korpusik, Oracle Corporation, ChairDave Rich, Mentor Graphics Corporation, Co-ChairBrad Pierce, Synopsys, Inc.Stuart Sutherland, Sutherland HDL, Inc.Shalom Bresticker, Intel CorporationSurrendra Dudani, Synopsys, Inc.Francoise Martinolle, Cadence Design Systems, Inc.The Basic/Design Committee (SV-BC) was responsible for the specification of the design features ofSystemVerilog.Matt Maidment, Intel Corporation, ChairBrad Pierce, Synopsys, Inc., Co-ChairFrancoise Martinolle, Cadence Design Systems, Inc.Dave Rich, Mentor Graphics CorporationArnab Saha, Mentor Graphics CorporationDaniel Schostak, ARM, Ltd.Steven Sharp, Cadence Design Systems, Inc.Stuart Sutherland, Sutherland HDL, Inc.Gordon Vreugdenhil, Mentor Graphics CorporationTom Alsop, Intel CorporationShalom Bresticker, Intel CorporationEric Coffin, Mentor Graphics CorporationPeter Flake, Accellera Systems InitiativeAlex Gran, Mentor Graphics CorporationMark Hartoog, Synopsys, Inc.Kaiming Ho, Fraunhofer IISviCopyright 2013 IEEE. All rights reserved.

The Enhancement Committee (SV-EC) was responsible for the specification of the testbench features ofSystemVerilog.Mehdi Mohtashemi, Synopsys, Inc., ChairNeil Korpusik, Oracle Corporation, Co-ChairRay Ryan, Mentor Graphics CorporationArturo Salz, Synopsys, Inc.Daniel Schostak, ARM Ltd.Nilotpal Sensarkar, Marvell Technology Group, Ltd.Steven Sharp, Cadence Design Systems, Inc.Brandon Tipp, Intel CorporationTony Tsai, Cisco Systems, Inc.Gordon Vreugdenhil, Mentor Graphics CorporationTom Alsop, Intel CorporationJonathan Bromley, Accellera Systems InitiativeDhiraj Goswami, Synopsys, Inc.Alex Gran, Mentor Graphics CorporationMark Hartoog, Synopsys, Inc.Scott Little, Intel CorporationFrancoise Martinolle, Cadence Design Systems, Inc.Dave Rich, Mentor Graphics CorporationThe Assertions Committee (SV-AC) was responsible for the specification of the assertion features ofSystemVerilog.Dmitry Korchemny, Intel Corporation, ChairTom Thatcher, Oracle Corporation, Co-ChairJacob Katz, Intel CorporationManisha Kulshrestha, Mentor Graphics CorporationScott Little, Intel CorporationAnupam Prabhakar, Mentor Graphics CorporationErik Seligman, Intel CorporationSamik Sengupta, Synopsys, Inc.Ashok Bhatt, Cadence Design Systems, Inc.Laurence Bisht, Intel CorporationEduard Cerny, Synopsys, Inc.Ben Cohen, Accellera Systems InitiativeDana Fisman, Synopsys, Inc.John Havlicek, Freescale, Inc.Tapan Kapoor, Cadence Design Systems, Inc.The C API Committee (SV-CC) was responsible for on the specification of the DPI, the SystemVerilogVerification Procedural Interface (VPI), and the additional coverage API.Charles Dawson, Cadence Design Systems, Inc., ChairGhassan Khoory, Synopsys, Inc., Co-ChairArnab Saha, Mentor Graphics CorporationArturo Salz, Synopsys, Inc.George Scott, Mentor Graphics CorporationBassam Tabbara, Synopsys, Inc.Jim Vellenga, Cadence Design Systems, Inc.Vitaly Yankelevich, Cadence Design Systems, Inc.Chuck Berking, Cadence Design Systems, Inc.Steve Dovich, Cadence Design Systems, Inc.Amit Kohli, Cadence Design Systems, Inc.Francoise Martinolle, Cadence Design Systems, Inc.Abigail Moorhouse, Mentor Graphics CorporationMichael Rohleder, Freescale, Inc.The Discrete Committee (SV-DC) was responsible for defining features to support modeling of analog/mixed-signal circuit components in the discrete domain.Scott Little, Intel Corporation, ChairAbhijeet Kolpekwar, Cadence Design Systems, Inc., Co-ChairFrancoise Martinolle, Cadence Design Systems, Inc.Arturo Salz, Synopsys, Inc.Sundaram Sangameswaran, Texas Instruments, Inc.Steven Sharp, Cadence Design Systems, Inc.Gordon Vreugdenhil, Mentor Graphics CorporationIan Wilson, Accellera Systems InitiativeShekar Chetput, Cadence Design Systems, Inc.Scott Cranston, Cadence Design Systems, Inc.Dave Cronauer, Synopsys, Inc.Mark Hartoog, Synopsys, Inc.John Havlicek, Freescale, Inc.Ghassan Khoory, Synopsys, Inc.viiCopyright 2013 IEEE. All rights reserved.

The following members of the entity balloting committee voted on this standard. Balloters may have votedfor approval, disapproval, or abstention.Japan Electronics and Information TechnologyIndustries Association (JEITA)Marvell Technology Group Ltd.Mentor Graphics CorporationOracle CorporationSynopsys, Inc.Accellera Systems InitiativeCadence Design Systems, Inc.Fraunhofer IISFreescale, Inc.Intel CorporationWhen the IEEE-SA Standards Board approved this standard on 5 December 2012, it had the followingmembership:Richard H. Hulett, ChairJohn Kulick, Vice ChairRobert M. Grow, Past ChairKonstantinos Karachalios, SecretarySatish AggarwalMasayuki AriyoshiPeter BalmaWilliam BartleyTed BurseClint ChaplinWael DiabJean-Philippe FaureAlexander GelmanPaul HouzéJim HughesYoung Kyun KimJoseph L. Koepfinger*David J. LawThomas LeeHung LingOleg LogvinovTed OlsenGary RobinsonJon Walter RosdahlMike SeavyYatin TrivediPhil WinstonYu Yuan*Member EmeritusAlso included are the following nonvoting IEEE-SA Standards Board liaisons:Richard DeBlasio, DOE RepresentativeMichael Janezic, NIST RepresentativeMatthew J. CegliaIEEE Manager, Professional ServicesMichelle TurnerIEEE Standards Program Manager, Document DevelopmentJoan WooleryIEEE Standards Program Manager, Technical Program DevelopmentviiiCopyright 2013 IEEE. All rights reserved.

IntroductionThis introduction is not part of IEEE Std 1800-2012, IEEE Standard for SystemVerilog—Unified Hardware Design,Specification, and Verification Language.The purpose of this standard is to provide the electronic design automation (EDA), semiconductor, andsystem design communities with a well-defined and official IEEE unified hardware design, specification,and verification standard language. The language is designed to coexist and enhance the hardwaredescription and verification languages (HDVLs) presently used by designers while providing the capabilitieslacking in those languages.SystemVerilog is a unified hardware design, specification, and verification language based on the AccelleraSystemVerilog 3.1a extensions to the Verilog hardware description language (HDL) [B3], published in2004.a Accellera is a consortium of EDA, semiconductor, and system companies. IEEE Std 1800 enables aproductivity boost in design and validation and covers design, simulation, validation, and formal assertionbased verification flows.SystemVerilog enables the use of a unified language for abstract and detailed specification of the design,specification of assertions, coverage, and testbench verification based on manual or automaticmethodologies. SystemVerilog offers application programming interfaces (APIs) for coverage andassertions, and a direct programming interface (DPI) to access proprietary functionality. SystemVerilogoffers methods that allow designers to continue to use present design languages when necessary to leverageexisting designs and intellectual property (IP). This standardization project will provide the VLSI designengineers with a well-defined IEEE standard, which meets their requirements in design and validation, andwhich enables a step function increase in their productivity. This standardization project will also providethe EDA industry with a standard to which they can adhere and that they can support in order to deliver theirsolutions in this area.aThe numbers in brackets correspond to those of the bibliography in Annex Q.ixCopyright 2013 IEEE. All rights reserved.

xCopyright 2013 IEEE. All rights reserved.

ContentsPart One: Design and Verification Constructs1.Overview. 21.11.21.31.41.51.61.71.81.91.101.11Scope. 2Purpose. 2Content summary . 2Special terms. 3Conventions used in this standard . 3Syntactic description. 4Use of color in this standard . 5Contents of this standard. 5Deprecated clauses. 8Examples. 8Prerequisites. 82.Normative references . 93.Design and verification building blocks . .Scheduling semantics. 234.14.24.34.44.54.64.74.84.94.105.General. 11Design elements . 11Modules . 11Programs . 12Interfaces. 13Checkers. 14Primitives . 14Subroutines . 14Packages. 14Configurations . 15Overview of hierarchy . 15Compilation and elaboration. 16Name spaces . 18Simulation time units and precision. 19General. 23Execution of a hardware model and its verification environment . 23Event simulation . 23Stratified event scheduler. 24SystemVerilog simulation reference algorithm . 29Determinism. 29Nondeterminism. 30Race conditions. 30Scheduling implication of assignments . 30PLI callback control points . 32Lexical conventions . 335.15.25.3General. 33Lexical tokens . 33White space. 33xiCopyright 2013 IEEE. All rights reserved.

5.45.55.65.75.85.95.105.115.125.136.Data types . nts . 33Operators. 33Identifiers, keywords, and system names . 34Numbers. 35Time literals . 40String literals. 40Structure literals . 42Array literals . 43Attributes . 43Built-in methods . 45General. 47Data types and data objects. 47Value set . 47Singular and aggregate types . 48Nets and variables . 49Net types . 50Net declarations . 61Variable declarations . 64Vector declarations . 66Implicit declarations . 67Integer data types . 68Real, shortreal, and realtime data types . 69Void data type . 69Chandle data type. 69Class. 70String data type . 70Event data type. 75User-defined types . 76Enumerations .

Verification Language. Sponsored by the . Design Automation Standards Committee. IEEE . 3 Park Avenue New York, NY 10016-5997 USA . 21 February 2013 . IEEE Computer Society and the IEEE Standards Association Corporate Advisory Group. IEEE Std 1800 -2012 (Revision of IEEE Std 1800-2009)

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The API is most useful when there is a need to automate a well-defined workflow, such as repeating the same tasks to configure access control for new vRealize Operations Manager users. The API is also useful when performing queries on the vRealize Operations Manager data repository, such as retrieving data for particular assets in your virtual environment. In addition, you can use the API to .