Simple VERILOG Example Using VIVADO 2015 With ZYBO FPGA Board V 0

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1AimI am FPGA novice and want to try classical FPGA design tutorials. I bought perfectmodern FPGA board ZYBO (ZYnq BOard) based on Xilinx Z-7010 from Digilent butlatest tools from Xilinx VIVADO 2015.2 more focused on AP SoC programming while Iwant to just pure FPGA design without any linuxes bootloaders etc. So I wrote thistutorial to help people like me :)In this example we make simple scheme: 2 signals IN and 4 OUT.SIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V1

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1Preconditions: Adding Zybo Board to VivadoVivado 2015.2 under Windows 7 64 bit was used with 16 GB of RAM.Before using Zybo with Vivado you should add Zybo Definitions File to Vivado.1. Good source for Board Definition files is Zynqbook website.DownloadThe Zynq Book Tutorial Sources Aug15.zip2. Copy zybo folder with content from Archive path \sources\zybo\setup\board partinto D:\Xilinx\Vivado\2015.2\data\boards\board files (if D:\Xilinx\Vivado\2015.2 is myPC you probably have C:\Xilinx etc.)3. In board files you should see other boards so now our Zybo known by Vivado.4. Download ZYBO Master.xdc from Digilent website unpack constraints files on localhard disk for example on Desktop.SIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V2

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1Phase 1. Preparation.I have latest Vivado Design Edition from Xilinx which comes with Digilent Zybo board.Launch your Vivado.SIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V3

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1Create new projectSIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V4

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1New ProjectClick NextSIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V5

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1Set project name.Set project name to gates2,Keep rest settings unchanged unless you know what you doing.SIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V6

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1Project TypeKeep default RTL(Register Transfer Level) project, Press NextAdd sourcesIn this tutorial we decided to use Verilog language so make sure it set correctly.Simulator language you can keep unchanged.SIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V7

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1Click on " " - Select - Create File.SIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V8

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1Create Source FileSet Filename to gates2. Keep the rest unchaged. Press OK. Press Next.SIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V9

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1Add Existing IPClick Next.SIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V10

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1Add ConstraintsClick " ", Add Files.SIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V11

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1Add Constraint file we downloaded at Precondition step.SIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V12

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1Make sure: Copy constraints files into project - Checked.Click - NextDefault PartClick on boards and select Zybo. If you still don't have it follow steps in Preconditions:Adding Zybo board to Vivado.SIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V13

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1If you don't see ZYBO goto Preconditions Step.Next.SIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V14

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1New Project SummaryFinishSIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V15

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1Phase 2. Editing ProjectProject files generated and ready for your design.We will implement 2 input gates and 4 output basic gates and, or, xor and nor.Define I/O ports as belowSIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V16

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1OKSIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V17

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1Select Verilog DesignClick on Source file in Project Manager Sources Design Sources - Source code onRight-hand side should appear.SIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V18

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1Changes to source code.Modify Verilog file - add lines as highlighted below.wire a,b;reg [3:0]z;always @(a or b)beginz[0] a & b;z[1] a b;z[2] a b;z[3] !(a b);endSIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V19

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1Create top fileRightclick on Design Sources and select Add Sources.1. Add or create design souces.SIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V20

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.12. " " Create FileSIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V21

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1File Type :Verilog,File name: top gates2OKFinishSIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V22

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1Define ModuleAdd sw and led as on image below.Replace default source code. timescale 1ns / 1psmodule top gates2(input [1:0] sw,output [3:0] ledSIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V23

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1);gates2 C1(.a(sw[0]),.b(sw[1]),.z(led));endmoduleSIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V24

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1Top DesignWe have single top design interface file which use our gates2 design as component.SIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V25

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1top designMake sure our top file became parent of gates2 file. Otherwise set it manually with Setas Top.SIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V26

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1Amend Constraints fileSelect xdc file from Sources ConstraintsSIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V27

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1Changes in xdc fileUncomment lines of I/O ports we need to use.Save file.SIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V28

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1Phase 3 - Synthesis and uploading to device.At Synthesis phase we convert our circuit from register transfer level (RTL) into adesign implementation in terms of logic gates.In Flow Navigator on Lefthand side.:Next steps can be Simulation Run Simulation or RTL Analysis Schematic but weskip them in this tutorial and come directly to Synthesis Run Synthesis.SIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V29

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1Synthesis complentionLeave default Run ImplementationOKSIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V30

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1Generate BitstreamSelect Generate BitstreamOKSIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V31

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1FinalPay attention to jumpers.JP7 - It should set to USB.JP5 can be JTAG or QSPIConnect ZYBO to PC with Micro-USB cable.Photo taken from mlSIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V32

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1Program ZYBONextSIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V33

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1NextSIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V34

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1Make sure you have similar setting like on picture below.Select xc7z010 1NextSIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V35

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1FinishProgram device xc7z010 1SIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V36

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1ProgramAs confirmation of successfull upload Greed Led will setSIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V37

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1Use switches to confirm and, or, xor and nor operations.Archive of project available.PDF version of this lesson available.Reference1. tutorial2. ief-Tutorial-Series-on-FPGADesi/?ALLSTEPS3. The ZYNQ BOOK - Make sure you download not only book archive but also tutorialsbook with sources.4. HDL Chip Design- A Practical Guide for Designing, Synthesizing and SimulatingASICs and FPGAs Using VHDL or Verilog. By Douglas J. Smith5. ZYBO Reference ManualSIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V38

Simple VERILOG example usingVIVADO 2015 with ZYBO FPGA boardv 0.1Files1. Project Archive2. ZYBO Board Definition File.3. ZYBO Master xdc file.Feedbackboris@borisivanov.comSIMPLE VERILOG EXAMPLE USING VIVADO 20150.1WITHZYBO FPGA BOARD V39

In this tutorial we decided to use Verilog language so make sure it set correctly. Simulator language you can keep unchanged. Simple VERILOG example using VIVADO 2015 with ZYBO FPGA board . ZYBO Reference Manual Simple VERILOG example using VIVADO 2015 with ZYBO FPGA board v 0.1 SIMPLE VERILOG EXAMPLE USING VIVADO 2015 WITH ZYBO FPGA BOARD V .