Power Supply Design For NXP I.MX 6 Using The TPS65023 - Texas Instruments
Application Report SLVA943 – February 2018 Power Supply Design for NXP i.MX 6 Using the TPS65023 ABSTRACT This document details the design considerations of a power management unit solution for the NXP i.MX 6Solo and 6DualLite processors using the TPS65023 power management IC (PMIC). The TPS65023 device has an input range from 2.5 to 6 V. The device has three low-dropout (LDO) regulators and three step-down converters that provide the 1.425-, 3-, 1.8-, 3.3-, and 1.35-V power rails in the appropriate power-up and power-down sequence that is required by the i.MX 6Solo and 6DualLite processors. For minor variations on this design to provide power to the i.MX 6 SoloX, SoloLite, SLL, UltraLite, and ULL processor variants, refer to the modified block diagrams in Appendix A. For an i.MX 6SL power solution targeted at IoT Gateway applications, refer to the VVDN design on the RadiumBoards website. Contents 1 Introduction . 2 2 Power Requirements . 2 3 Schematic . 7 4 Bill of Materials (BOM) . 9 5 Waveforms . 10 6 Transient Response. 14 7 Efficiency Curves . 16 8 Layout . 17 9 Conclusion . 17 10 References . 17 Appendix A Block Diagram Variations for i.MX 6 Processor Variants . 18 List of Figures 1 TPS65023 Power Solution Block Diagram for i.MX 6Solo and 6DualLite . 3 2 External Resistor Divider 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 . 6 TPS65023 Circuit for i.MX 6Solo and 6DualLite Power Requirements. 8 Power-Up Sequence for VRTC and DCDC2 . 10 Power-Up Sequence for DCDC2 and DCDC1 . 10 Power-Up Sequence for DCDC2, DCDC1, and DCDC3 . 11 Power-Up Sequence for DCDC1, DCDC3, and LDO1 . 11 Power-Down Sequence for DCDC1, DCDC3, and LDO1 . 12 Power-Down Sequence for DCDC2, DCDC1, and DCDC3 . 12 Power-Down Sequence for VSYS, DCDC2, and DCDC1 . 13 Power-Down Sequence for ENABLE, DCDC2, and VRTC . 13 Transient Response for DCDC1 . 14 Transient Response for DCDC2 . 15 Transient Response for DCDC3 . 15 DCDC1 Efficiency . 16 DCDC2 Efficiency . 16 DCDC3 Efficiency . 16 Layout Example of a DC-DC Converter . 17 SLVA943 – February 2018 Submit Documentation Feedback Power Supply Design for NXP i.MX 6 Using the TPS65023 Copyright 2018, Texas Instruments Incorporated 1
Introduction www.ti.com 19 TPS65023 Power Solution Block Diagram for i.MX 6SoloX . 18 20 TPS65023 Power Solution Block Diagram for i.MX 6SoloLite . 19 21 TPS65023 Power Solution Block Diagram for i.MX 6SLL . 20 22 TPS65023 Power Solution Block Diagram for i.MX 6UltraLite and 6ULL. 21 List of Tables 1 i.MX 6Solo and 6DualLite Power Requirements. 4 2 Bill of Materials 3 . 9 Transient Requirements and Results . 14 Trademarks All trademarks are the property of their respective owners. 1 Introduction This reference design applies to the NXP i.MX 6Solo and 6DualLite family of applications processors. This report provides all the required external components necessary to achieve the required output and sequence to power-up and power-down the i.MX 6 processor. This reference design provides a solution for a VSYS voltage being 5 V, DDR3L SDRAM requiring 1.35 V, and NVCC power domain requiring 3 V. However if DDR3, LPDDR2, or LPDDR3 SDRAM is desired, the required output can be achieved by modifying a resistor divider, which is detailed in Section 2.3 of this document. 2 Power Requirements Figure 1 shows a block diagram of the TPS65023 device and i.MX 6Solo and 6DualLite processor interfaces. Table 1 lists the power output capabilities of the TPS65023 and matches them to the power requirements of the i.MX 6Solo and 6DualLite processor.Figure 3 shows a circuit schematic detailing the TPS65023 device and the sequencing circuit. NOTE: The generic part number TPS65023 is used for simplicity in this document. The TPS65023B device is shown in the block diagram and schematic because the TPS65023B has improved I2C performance. The -B version is also on the BOM and should be assembled on the final solution. 2 Power Supply Design for NXP i.MX 6 Using the TPS65023 Copyright 2018, Texas Instruments Incorporated SLVA943 – February 2018 Submit Documentation Feedback
Power Requirements www.ti.com i.MX 6Solo, 6DualLite Processor VSYS 5.25 V max 1.425 V DCDC1 DCDC2 VRTC 1.7 A 1.2 A 30 mA VDD ARM, VDD SOC (LDO PU, LDO SoC, LDO ARM enabled) 3.0 V 3.0 V VDD HIGH IN (LDO 2P5, LDO 1P1, LDO SNVS enabled) VDD SNVS IN from internal LDOs HDMI VP, PCIE VP, PCIE VPTX TPS65023B PMIC NVCC LVDS2P5, HDMI VPH, PCIE VPH, NVCC MIPI 1.2, 1.35, or 1.5 V DCDC3 1.0 A VLDO1 01b 11b 2.8 1.8 V 3.3 3.3 V VLDOx options LDO1 200 mA V3V3 LDO2 200 mA NVCC DRAM, NVCC DRAM CKE 1.8 or 2.8 V Peripheral DRAM VREF from internal LDOs NVCC GPIO, NVCC SD1-3, NVCC ENET, NVCC CSI, NVCC EIM, NVCC LCD, NVCC NANDF, NVCC JTAG 3.3 V Peripheral TPS22915B 5 V, 2 A, 38 PŸ Load Switch USB HI VBUS, USB OTG VBUS DRAM Memory Module VDD, VDDQ, VDDCA, VDD1, VDD2 RREF VREF RREF Copyright 2018, Texas Instruments Incorporated Figure 1. TPS65023 Power Solution Block Diagram for i.MX 6Solo and 6DualLite SLVA943 – February 2018 Submit Documentation Feedback Power Supply Design for NXP i.MX 6 Using the TPS65023 Copyright 2018, Texas Instruments Incorporated 3
Power Requirements www.ti.com Table 1 lists the i.MX 6 power requirements which are determined from the i.MX 6Solo/6DualLite Applications Processors for Consumer Products Data Sheet and the i.MX 6Solo/6DualLite Applications Processors for Industrial Products Data Sheet. Table 1. i.MX 6Solo and 6DualLite Power Requirements TPS65023 (1) (2) (3) (4) i.MX 6Solo/6DualLite POWER-UP SEQUENCE POWER-DOWN SEQUENCE POWER SUPPLY (OUTPUT) OUTPUT CURRENT [mA] OUTPUT VOLTAGE [V] POWER SUPPLY (INPUT) NOMINAL RATING [V] MAX CURRENT [mA] 2 or 3 1 or 2 DCDC1 1700 1.425 VDD ARM, VDD SOC (1) Minimum: 1.35 Typical: 1.425 Maximum: 1.5 1510 (2) 2 2 DCDC2 1200 3 VDD HIGH IN (3) Minimum: 2.9 Maximum: 3.3 125 Maximum IO current 3 1 DCDC3 1000 1.35 NVCC DRAM, NVCC DRAM CKE Minimum: 1.283 Typical: 1.35 Maximum: 1.45 1000 3 1 LDO1 200 1.8 or 2.8 1.8-V or 2.8-V peripherals and NVCC rails not supplied by internal LDO regulators N/A N/A 3 1 LDO2 200 3.3 3.3-V peripherals and NVCC rails not supplied by internal LDO regulators N/A N/A 1 3 VRTC 30 3 VDD SNVS IN (4) 3 V 20% 1 LDO PU, LDO SoC, and LDO ARM internal LDO regulators are enabled to generate the specific voltage required by the ARM and SoC inputs. The maximum current for the VDD ARM and VDD SOC core rails is determined from the Typical max power section in the AN4576 Application Note. LDO 2P5, LDO 1P1, and LDO SNVS internal LDO regulators are enabled to generate voltages for all NVCC power inputs as well as the HDMI VPH and PCIE VPH supply voltages. Coin cell battery can be used as backup power for VDD SNVS IN, which is usually powered by the VDD HIGH IN supply voltage. The TPS65023 device fulfills all the power requirements with three step-down converters and three LDO regulators. To meet the power sequence requirements, a simple sequencing circuit is used, which is detailed in Figure 3. Combining the VDD ARM and VDD SOC core rails does not limit the clocking frequency when the LDO PU, LDO SoC, and LDO ARM internal LDO regulators are used to set the ideal voltage for the ARM and SoC point-of-load. As a result, all the clock frequency setpoints of 996 MHz, 792 MHz, 396 MHz, and sub-328 MHz can be supported by modifying the VDD ARM CAP, VDD SOC CAP, and VDD PU CAP LDO output setpoints. The input power rails of the i.MX 6 processor, USB HI VBUS and USB OTG VBUS, require 5 V (typical) and 5.25 V (maximum). The input power to this system, VSYS, must be 5 V and cannot be greater than 5.25 V because the TPS22915B load switch provides power to these two rails and a load switch does not convert voltage. The USB HI VBUS and USB OTG VBUS rails are not shown in Table 1 because they are not regulated voltages and are not supplied by the TPS65023B device. The TPS22615B load switch is enabled and disabled by the controller of the system for saving power. 4 Power Supply Design for NXP i.MX 6 Using the TPS65023 Copyright 2018, Texas Instruments Incorporated SLVA943 – February 2018 Submit Documentation Feedback
Power Requirements www.ti.com 2.1 Power-Up Sequence The required power-up sequence of the supply rails specified by the i.MX 6Solo/6DualLite data sheet is as follows: 1. VDD SNVS IN which is primarily supplied by the VRTC regulator 2. VDD HIGH IN which is supplied by the DCDC2 converter 3. VDD SOC and VDD ARM which are supplied by the DCDC1 converter, and NVCC DRAM and NVCC DRAM CKE which are supplied by the DCDC3 converter NOTE: The SRC POR B input pin of the i.MX6 processor controls the processor power-on reset (POR) and must be immediately asserted at power-up and stay asserted until the ARM and SoC core rails are in regulation. Additionally, the USB OTG VBUS and USB H1 VBUS rails are not part of the power supply sequence, and the load switches that provide these rails can be enabled at any time. The first step in the power-up sequence is turning on the VDD SNVS IN rail with the VRTC regulator. In the TPS65023 device one of the three LDO regulators is designated as VRTC with an output of 3 V. The VRTC regulator defaults to turning on when the TPS65023 device powers on, which means the VDD SNVS IN rail is always the first rail on. The second step is part of the sequencing circuit. A slider switch is used in the schematic; however, the switch can be replaced with an outside enable signal going HIGH. By setting the signal HIGH, it will set the D1 diode to forward bias, whereas, the D2 and D3 diodes are reverse bias. With the D1 diode in forward bias, the EN 1 signal goes HIGH and turns on the DCDC2 converter. The DCDC2 converter turns on at this time because no sequence requirements are required for what is powered by the DCDC2 converter. The threshold voltage for the enable input is 1.3 V. The DCDC2 converter has an output voltage of 3 V and must be used to turn on the remaining enable pins. The DCDC1 converter provides power to the core rails, VDD ARM and VDD SOC. The only power-up requirement for the iMX6 Solo and DualLite processors is that VDD SNVS IN rail is powered on first. As a result, an option to sequence the VDD1 voltage with the DCDC2 converter from the EN 1 signal (R12 installed) or with the DCDC3 converter from the EN 2 signal (R13 installed) is available. By default, the R13 resistor is installed and the DCDC1 converter will sequence at the same time as the DCDC3 converter. When the DCDC2 voltage is greater than 1.3 V, the DCDC2 output goes through an RC (R14 and C14) delay before enabling the DCDC3 converter and the remaining two LDO regulators. After reaching the operating level, the DCDC3 voltage goes through a resistor divider and RC delay before going to the PWRFAIL SNS pin, which sets the internal comparator for the PWRFAIL signal. The PWRFAIL output of the TPS65023 device is directly connected to the SRC POR B signal of the i.MX 6 processor with correct polarity. The USB HI VBUS and USB OTG VBUS rails do not require sequencing. As a result, the ON pin of the TPS22915B load switch is pulled up to the VSYS voltage and the switch is enabled by default when the system input voltage is greater than 1 V. The power-up sequence is complete. Figure 3 shows the schematic for the correct connections for the power-up sequence. 2.2 Power-Down Sequence The i.MX 6 data sheet lists no specific restrictions for the power-down sequence of the i.MX 6Solo/DualLite IC. Because of the analog power-up sequence implemented in this design, the processor is powered off in the reverse order of the power-up sequence. The power-down sequence of the supply rails is as follows: 1. VDD SOC and VDD ARM which are supplied by the DCDC1 converter, and NVCC DRAM and NVCC DRAM CKE which are supplied by the DCDC3 converter 2. VDD HIGH IN which is supplied by the DCDC2 converter 3. VDD SNVS IN which is primarily supplied by the VRTC regulator SLVA943 – February 2018 Submit Documentation Feedback Power Supply Design for NXP i.MX 6 Using the TPS65023 Copyright 2018, Texas Instruments Incorporated 5
Power Requirements www.ti.com To start the power-down sequence, the switch is turned off or the enable signal is set LOW which makes the D2 and D3 diodes forward biased. The PWRFAIL SNS signal becomes LOW which pulls the PWRFAIL output LOW. The EN 2 signal becomes LOW and causes the output of the DCDC3 converter and LDO regulators to ramp down. The D1 diode is now reverse biased, letting the C13 capacitor discharge into the R11 resistor, which creates a delay longer than the ramp down of the DCDC3 converter and LDO regulators. At this point, DCDC3 and DCDC1 converters are powered down in the correct order. The VRTC regulator is tied to the input voltage and, therefore, is only powered down when the input voltage starts ramping down. When a backup coin-cell battery is used, the VRTC regulator will remain on even when the main system input voltage is unavailable. This power-down sequence makes sure that the VRTC rail is the last rail on which fulfills all the requirements for the power-down sequence. Figure 3 shows the correct connections for the power-down sequence. 2.3 Adjusting the Step-Down Output Figure 2 shows the external resistor divider circuit. 10 R VCC VDCDC3 1 µF L L3 VINDCDC3 VO CO CI R1 DCDC3 EN DEFDCDC3 R2 AGND PGND Copyright 2016, Texas Instruments Incorporated Figure 2. External Resistor Divider The DEFDCDC1, DEFDCDC2, and DEFDCDC3 pins are used to set the output voltage for each stepdown converter. By using an external resistor divider, the output voltage can be set from 0.6 up to the input voltage, V(bat). The total resistance (R1 R2) of the voltage divider must be kept in the 1-MΩ range to keep a high efficiency at light loads. R1 R2 VOUT VDEFDCDCx R2 where V(DEFDCDCx ) 0.6 V æ VOUT R1 R2 ç è VDEFDCDCx 2.4 ö - R2 ø Adjusting the Sequencing Circuit In the schematic shown in Figure 3, the sequence circuit is designed with a DCDC3 output of 1.35 V. If DDR3, LPDDR2, or LPDDR3 SDRAM is desired over DDR3L SDRAM, then the resistor divider (R16 and R17) must be changed accordingly to provide 1 V to the PWRFAIL SNS pin. 6 Power Supply Design for NXP i.MX 6 Using the TPS65023 Copyright 2018, Texas Instruments Incorporated SLVA943 – February 2018 Submit Documentation Feedback
Schematic www.ti.com 3 Schematic Figure 3 shows the circuit schematic and details the external components required for the TPS65023 device to achieve the 1.425-, 3-, 1.8-, 3.3- and 1.35-V, power rails required by the i.MX 6Solo and 6DualLite processor. The sequencing circuit is also detailed to achieve the correct power-up and powerdown sequence. A slider switch is shown in the schematic; however, any switching mechanism can be used, for example, an external enable signal. SLVA943 – February 2018 Submit Documentation Feedback Power Supply Design for NXP i.MX 6 Using the TPS65023 Copyright 2018, Texas Instruments Incorporated 7
Schematic VSYS www.ti.com Input voltage of 5.25 V max VIO can be connected to any of the following rails: DCDC2 3.0 V, LDO1 1.8 V, LDO2 3.3 V, or an LDO output pin of one of the i.MX6 integrated LDOs VDD ARM, VDD SOC VIO C5 22µF R8 4.75k C1 C2 22µF U1 R1 37 VINDCDC1 6 36 5 VINDCDC2 GND VDD HIGH IN VCC SCLK SDAT 10 GND VINDCDC3 VINDCDC1 VINDCDC2 VINDCDC3 VRTC 30 29 C7 22µF 9 VDCDC1 2.6A L1 7 19 PWRFAIL SNS C16 1500pF DEFLDO2 GND GND HOT RESET VRTC R20 C17 4.7 µF GND EN 1 LOW BAT 38 39 PWRFAIL SNS LOWBAT SNS 26 TRESPWRON 12 13 DEFLD01 DEFLD02 2.6A L2 GND 16 22 31 VRTC LDO EN PWRFAIL 25 24 23 DEFDCDC1 DEFDCDC2 DEFDCDC3 10 32 1 4 SW3 DCDC1 EN DCDC2 EN DCDC3 EN DEFDCDC1 DEFDCDC2 DEFDCDC3 VREF DRAM VREF VDCDC3 GND VLDO1 20 LDO1 VLDO2 18 LDO2 INT C10 22µF L3 2.2uH LS VOUT USB HI VBUS USB OTG VBUS 28 C12 2.2 µF 27 RESPWRON R12 0 DNP C9 22µF VDCDC2 2.6A L3 VBACKUP VSYSIN HOT RESET SW2 2 NVCC DRAM NVCC DRAM CKE L2 2.2uH VDCDC3 15 14 11 35 VDD SNVS IN VDCDC1 33 VDCDC2 21 100k R13 0 EN 2 VINLDO C8 22µF L1 SW1 2.2uH VINLDO R10 100k C19 22µF GND GND GND C4 22µF C18 22µF R5 4.75k 1µF C3 22µF C6 22µF C11 2.2 µF Power supplies for DDR3L Memory IC PGND1 PGND2 PGND3 8 34 3 AGND1 AGND2 PAD 40 17 41 GND VDD, VDDQ, VDDCA VDD1, VDD2 GND R22 100k VREF VREF R23 100k TPS65023BRSBR GND VSYS On-Off Sequence Circuit U2 C20 16V A2 1uF VSYS D1 1 2 3 S1 EN 1 R19 GND 10k EN LS MBR0540T1G C13 1µF R11 100k VDCDC2 DNP C22 16V 0.1uF R14 2.0k GND D2 GND EN 2 B2 GND VIN VOUT ON GND TPS22915BYFPR LS VOUT A1 C21 16V 0.1uF B1 GND External resistors for setting DCDCx and LDOx Voltages GND Voltage Divider for DEFDCDC1 Set to 1.425 V Voltage Divider for DEFDCDC2 Set to 3.0 V Voltage Divider for DEFDCDC3 Set to 1.35 V for DDR3L VDCDC2 VDCDC3 Resistor options for DEFLDO2, control for VLDO1 (HI 1 -- LDO1 1.8V, LO 0 -- LDO1 2.8V) MBR0540T1G VDCDC1 R2 165k R16 35.2k VINLDO C14 1µF VDCDC3 R4 464k R15 10k R6 150k GND DEFDCDC1 DEFDCDC2 DEFDCDC3 DEFLDO2 D3 PWRFAIL SNS MBR0540T1G R17 100k R3 120k R9 115k R7 120k R18 DNP10k C15 1µF GND GND GND GND GND Copyright 2018, Texas Instruments Incorporated Figure 3. TPS65023 Circuit for i.MX 6Solo and 6DualLite Power Requirements 8 Power Supply Design for NXP i.MX 6 Using the TPS65023 SLVA943 – February 2018 Submit Documentation Feedback Copyright 2018, Texas Instruments Incorporated
Bill of Materials (BOM) www.ti.com 4 Bill of Materials (BOM) Table 2 lists the BOM for this design. Table 2. Bill of Materials Value Package Reference Designator Quantity Description Part Number Manufacturer !PCB 1 C1, C13, C14, C15 XX#### Any 4 1uF CAP, CERM, 1 µF, 16 V, /- 20%, X5R, 0603 0603 885012106017 Wurth Elektronik C2, C3, C4, C5, C6, C7, C8, C9, C10, C18, C19 11 22uF CAP, CERM, 22 µF, 10 V, /- 20%, X5R, 0603 0603 C1608X5R1A226M080AC TDK C11, C12 2 C16 1 2.2uF CAP, CERM, 2.2 µF, 10 V, /- 20%, X5R, 0603 0603 C0603C225M8PACTU Kemet 1500pF CAP, CERM, 1500 pF, 10 V, /- 10%, X5R, 0201 0201 GRM033R61A152KA01D C17 1 MuRata 4.7uF CAP, CERM, 4.7 µF, 10 V, /- 20%, X5R, 0402 0402 GRM155R61A475M MuRata 0603 GCM188R71C105KA64D MuRata Printed Circuit Board C20 1 1uF CAP, CERM, 1 uF, 16 V, /- 10%, X7R, AEC-Q200 Grade 1, 0603 C21 1 0.1uF CAP, CERM, 0.1 uF, 16 V, /- 10%, X7R, 0603 0603 GRM188R71C104KA01D MuRata D1, D2, D3 3 40V Diode, Schottky, 40 V, 0.5 A, SOD-123 SOD-123 MBR0540T1G ON Semiconductor H1, H2, H3, H4 4 Machine Screw, Round, #4-40 x 1/4, Nylon, Philips panhead Screw NY PMS 440 0025 PH B&F Fastener Supply H5, H6, H7, H8 4 Standoff, Hex, 0.5"L #4-40 Nylon Standoff 1902C Keystone 4 Bumpon, Hemisphere, 0.44 X 0.20, Clear Transparent Bumpon SJ-5303 (CLEAR) 3M L1, L2, L3 3 Inductor, Film, 2.2 uH, 2.6 A, 0.084 ohm, AEC-Q200 Grade 0, SMD 2.5x2mm TFM252012ALMA2R2MTAA TDK LBL1 1 Thermal Transfer Printable Labels, 0.650" W x 0.200" H - 10,000 per roll PCB Label 0.650 x 0.200 inch THT-14-423-10 Brady R1 1 10 RES, 10, 5%, 0.063 W, 0402 0402 CRCW040210R0JNED Vishay-Dale R2 1 165k RES, 165 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0402 0402 ERJ-2RKF1653X Panasonic R3, R7 2 120k RES, 120 k, 1%, 0.063 W, 0402 0402 CRCW0402120KFKED Vishay-Dale R4 1 464k RES, 464 k, 1%, 0.063 W, AEC-Q200 Grade 0, 0402 0402 CRCW0402464KFKED Vishay-Dale R5, R8 2 4.75k RES, 4.75 k, 1%, 0.063 W, 0402 0402 CRCW04024K75FKED Vishay-Dale R6 1 150k RES, 150 k, 1%, 0.063 W, 0402 0402 CRCW0402150KFKED Vishay-Dale R9 1 115k RES, 115 k, 1%, 0.063 W, AEC-Q200 Grade 0, 0402 0402 CRCW0402115KFKED Vishay-Dale R10, R11, R17, R20, R22, R23 6 100k RES, 100 k, 1%, 0.063 W, 0402 0402 CRCW0402100KFKED Vishay-Dale R13 1 0 RES, 0, 5%, 0.063 W, 0402 0402 MCR01MZPJ000 Rohm R14 1 2.0k RES, 2.0 k, 5%, 0.063 W, 0402 0402 CRCW04022K00JNED Vishay-Dale R15, R19 2 10k RES, 10 k, 5%, 0.063 W, AEC-Q200 Grade 0, 0402 0402 CRCW040210K0JNED Vishay-Dale R16 1 35.2k RES, 35.2 k, 0.1%, 0.1 W, 0603 0603 RT0603BRD0735K2L Yageo America S1 1 Switch, Slide, SPST, On-Off, 1 Pos, 0.4VA, 20V, SMT 10.03x9.14mm ES02MSABE C&K Components U1 1 POWER MANAGEMENT IC FOR LI-ION POWERED SYSTEMS, RSB0040B (WQFN-40) RSB0040B TPS65023BRSBR Texas Instruments U2 1 5.5V, 2A, 38mΩ Load Switch With Quick Output Discharge, YFP0004AAAA (DSBGA-4) YFP0004AAAA TPS22915BYFPR Texas Instruments C22 0 CAP, CERM, 0.1 uF, 16 V, /- 10%, X5R, 0402 0402 GRM155R61C104KA88D MuRata FID1, FID2, FID3 0 Fiducial mark. There is nothing to buy or mount. N/A N/A N/A R12 0 0 RES, 0, 5%, 0.063 W, 0402 0402 MCR01MZPJ000 Rohm R18 0 10k RES, 10 k, 5%, 0.063 W, AEC-Q200 Grade 0, 0402 0402 CRCW040210K0JNED Vishay-Dale H9, H10, H11, H12 2.2uH 0.1uF SLVA943 – February 2018 Submit Documentation Feedback Power Supply Design for NXP i.MX 6 Using the TPS65023 Copyright 2018, Texas Instruments Incorporated 9
Waveforms 5 www.ti.com Waveforms The following waveforms demonstrate the power-up and power-down sequence of the TPS65023 device as required by the i.MX 6Solo and 6DualLite processors. Figure 4 shows the start of the power-up sequence where the VSYS rail turns on with the primary enable switch (SW1) in the ON position (pins 1 and 3 shorted). The VRTC regulator turns on first and the DCDC2 converter turns on after a short delay. VSYS VRTC VDCDC2 Figure 4. Power-Up Sequence for VRTC and DCDC2 Figure 5 shows the start of the power-up sequence again where the VSYS voltage turns on with SW1 in the ON position. In this waveform, the timing shown is from the DCDC2 converter being enabled by the EN 1 signal to the DCDC1 converter being enabled by the EN 2 signal, which is driven high by the output of the DCDC2 converter. VSYS VDCDC2 VDCDC1 Figure 5. Power-Up Sequence for DCDC2 and DCDC1 10 Power Supply Design for NXP i.MX 6 Using the TPS65023 Copyright 2018, Texas Instruments Incorporated SLVA943 – February 2018 Submit Documentation Feedback
Waveforms www.ti.com Figure 6 shows the portion of the power-up sequence where the DCDC2 converter turns on after being enabled by the EN 1 signal. The output of the DCDC2 converter drives the EN 2 signal and is delayed by the RC delay (R14 and C14). This delay should make sure that DCDC2 converter reaches its final voltage and is in regulation before the DCDC1 and DCDC3 converters are enabled. After the EN 2 signal has risen to greater than the VIH threshold of the enable pin, both the DCDC1 and DCDC3 converters are enabled at the same. VDCDC2 VDCDC1 VDCDC3 Figure 6. Power-Up Sequence for DCDC2, DCDC1, and DCDC3 Figure 7 shows the portion of the power-up sequence where the DCDC1 and DCDC3 converters turn on at the same time. The LDO regulators, which are also controlled by the EN 2 signal, do not require any internal pre-biasing and seem to be enabled slightly before the DCDC1 and DCDC3 converters. This timing is acceptable because the LDO regulators are not part of the power-up sequence requirements of the i.MX 6 processor. Only one of the LDO regulators (LDO1) is captured; however, both LDO regulators share the same enable pin and are enabled at the same time. VDCDC1 VDCDC3 VLDO1 Figure 7. Power-Up Sequence for DCDC1, DCDC3, and LDO1 SLVA943 – February 2018 Submit Documentation Feedback Power Supply Design for NXP i.MX 6 Using the TPS65023 Copyright 2018, Texas Instruments Incorporated 11
Waveforms www.ti.com All power-down sequencing diagrams are shown as a reference only because the i.MX 6Solo and 6DualLite processors have no requirements for power-down sequencing. Figure 8 shows the power-down sequence for each output showing that the DCDC1 and DCDC3 converters turn off at the same time. The relative power-down timing of the LDO regulators (LDO1) is shown as a reference, but all three power rails shown in the diagram are controlled by the same EN 2 signal. The EN 2 signal is pulled low immediately when the SW1 switch is set to the OFF position (pins 1 and 2 shorted). VDCDC1 VDCDC3 VLDO1 Figure 8. Power-Down Sequence for DCDC1, DCDC3, and LDO1 Figure 9 shows the power-down sequence for each output showing that the DCDC2 converter turns off after the DCDC1 and DCDC3 converters turn off at the same time. The DCDC2 converter is controlled by the EN 1 signal, which is low when the voltage on the C13 capacitor has discharged through the R11 resistor and drops to less than the VIL threshold of the enable pin. The DCDC1 and DCDC3 converters have a load of 300 Ω applied at the output. VDCDC2 VDCDC1 VDCDC3 Figure 9. Power-Down Sequence for DCDC2, DCDC1, and DCDC3 12 Power Supply Design for NXP i.MX 6 Using the TPS65023 Copyright 2018, Texas Instruments Incorporated SLVA943 – February 2018 Submit Documentation Feedback
Waveforms www.ti.com Figure 10 shows the power-down sequence for the DCDC2 and DCDC1 converters again. This waveform shows that the VSYS input voltage can stay high when the SW1 switch is set to the OFF position. The EN 1 and EN 2 signals follow the change in position of the switch to disable the regulators and achieve power savings in the design, if desirable by the application. VSYS VDCDC2 VDCDC1 Figure 10. Power-Down Sequence for VSYS, DCDC2, and DCDC1 Figure 11 shows the power-down sequence timing from when the primary ENABLE signal is pulled low (the result of the SW1 switch in the OFF position) to when the DCDC2 converter turns off. The VRTC regulator is also shown to verify that this is the last voltage to turn off. In the waveform, the input voltage (VSYS) does not turn off, so the VRTC regulator stays on the entire time. The VRTC regulator stays on when the VSYS voltage does turn off but a backup battery is also available, attached to the VBACKUP pin of the TPS65023 device. ENABLE VDCDC2 VRTC Figure 11. Power-Down Sequence for ENABLE, DCDC2, and VRTC SLVA943 – February 2018 Submit Documentation Feedback Power Supply Design for NXP i.MX 6 Using the TPS65023 Copyright 2018, Texas Instruments Incorporated 13
Transient Response 6 www.ti.com Transient Response Table 3 lists the transient requirements and results for each DC-DC step-down converter. Transient requirements are provided by the i.MX 6Solo/6DualLite data sheet. Table 3. Transient Requirements and Results STEP-DOWN CONVERTER DCDC1 (mV) DCDC1 RESULTS i.MX 6 REQUIREMENTS MINIMUM (–) MAXIMUM ( ) MINIMUM (–) MAXIMUM ( ) MINIMUM (–) MAXIMUM ( ) DCDC1 (1.425-V typical voltage) 50 54.4 5% 5.44% 5.26% 12.3% DCDC2 (3-V typical voltage) 52 54.4 2.89% 3.02% 6.67% 10% DCDC3 (1.35-V typical voltage) 62 61.2 4.59% 4.53% 4.96% 7.41% Figure 12 shows the transient response of the DCDC1 converter with a load going from 450 to 1500 mA in 1-μs steps. The transient response shows that the DCDC1 converter fits within the required range of 1.425 V – 5.26% to 1.425 V 12.3%. Figure 12. Transient Response for DCDC1 14 Power Supply Design for NXP i.MX 6 Using the TPS65023 Copyright 2018, Texas Instruments Incorporated SLVA943 – February 2018 Submit Documentation Feedback
Transient Response www.ti.com Figure 13 shows the transient response of the DCDC2 converter with a load going from 360 to 1200 mA in 1µs steps. The transient response shows that the DCDC2 converter fits within the required range of 3 V – 6.67% to 3 V 10%. Figure 13. Transient Respo
Power Supply Design for NXP i.MX 6 Using the TPS65023 Application Report SLVA943-February 2018 Power Supply Design for NXP i.MX 6 Using the TPS65023 ABSTRACT This document details the design considerations of a power management unit solution for the NXP i.MX 6Solo and 6DualLite processors using the TPS65023 power management IC (PMIC).
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